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TC55V8200FT-10-TC55V8200FT-12-TC55V8200FT-15
2,097,152-WORD BY 8-BIT CMOS STATIC RAM
TOSHIBA TC55V8200FT-10,-12,-15
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2,097,152-WORD BY 8-BIT CMOS STATIC RAM
DESCRIPTION
The TC55V8200FT is a 16,7 7 7 ,216-bit high-speed static random access memory (SRAM) organized as
2,097,152 words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high
speed, it operates from a single 3.3 V power supply. Chip enable (CE) can be used to place the device in a low-
power mode, and output enable (OE) provides fast memory access. This device is well suited to cache memory
applications where high-speed access and high-speed storage are required. All inputs and outputs are directly
LVTTL compatible. The TC55V8200FT is available in plastic 54-pin TSOP with 400mi1 width for high density
surface assembly.
FEATURES
0 Fast access time (the following are maximum values) 0 Single power supply .' 3.3VK 5% (-10)
TC55V8200FT-10: 10 ns l 3.3V: 0.3V (-12, -15)
TC55V8200FT-12: 12 ns It Fully static operation
TC55V8200FT-15: 15 ns 0 All inputs and outputs are LVTTL compatible
0 Low-power dissipation 0 Output buffer control using OE
Cycle Time 10 12 15 ns dt Package: .
Standby: 4mA(max)
PIN ASSIGNMENT PIN NAMES
o A0 to A20 Address Inputs
TILE): E g 53 E 232D l/OI t_o l/08 Data Inputs/Outputs
NU2 l: 3 52 = NU2 CE Chip Enable Input
Iff, E g ll g 52: T Write Enable Input
|/08 = 6 49 = IIOS OE Output Enable Input
2431. E I g E ti', VDD Power(+ 3.3V)
tf l: l Cl' = tl GND Ground
A0 E 11 E 44 = A9 NC No Connection
N_CI: 12 - 43 = N_C NU1,NU2 Not Usable
CE I: 13 > 42 = OE
ml: 14 41 = GND
WE = 15 a. 40 = NU1
NC I: 16 O 39 2' A20
A19 I: 17 C, 38 = A10
A18 = 18 37 = A11
A17 1: 19 36 = A12
A16 l: 20 35 = A13
A15 = 21 34 = A14
l/Ol = 22 33 = I/O4
VDD = 23 32 = GND
l/O2 = 24 31 = I/O3
NU2 l: 25 30 = NU2
GND = 26 29 = VDD
NU2 = 27 28 = NU2
000707EBA2
O TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction
or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA
products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a mal unction or
failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent
TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor
Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
0 The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office
equipment, measurina equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for
usage in equipment t at requires extraordinarily high quality and/or reliability or a malfunction or failure of which m.ay cause loss of human life or
bodily injury CUnintended Usage"). Unintended Usage include atomic ener y control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, me ical instruments, all types of safety devices, etc.. Unintended Usage of
TOSHIBA products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade laws.
0 The information contained herein is presented only as a guide for the ap lications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights 0 the third parties which may result from its use. No license is granted
b implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
2000-07-11 1/8
TOSHIBA TC55V8200FT-10,-12,-15
BLOCK DIAG RAM
MEMORY
CELL ARRAY
BUF FER
DECODER
1,024 x 2,048 M 8
(16,777,216) GND
ROJVADDRESS
I/O2 F- -
SENSE AMP. D
l/O3 a ttt , ttt
l/O4 E tl © tl
l/O5 LL C) y,
< D < m
I/06 'a m COLUMN 'a
I/O? o o
DECODER
COLUMN ADDRESS
BUFFER
A10 A12 A14 A16A18 A20
A11 A13 A15 A17 A19
GENERATOR
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.5 to 4.6 V
VIN Input Terminal Voltage - 0.5* to 4.6 V
VI/O Input/Output Terminal Voltage - 0.5* to VDD + 0.5** V
PD Power Dissipation 1.8 W
Tsolder Soldering Temperature (10s) 260 ''C
Tstrg Storage Temperature - 65 to 150 "C
Topr Operating Temperature - 10 to 85 "C
.' -1.5V with a
: VDD+1.5V wit
ulse width of 20% . tRC min (4ns max)
a pulse width of 20% . tRC min (4ns max)
DC RECOMMENDED OPERATING CONDITIONS (Ta = ty' to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
-10 3.135 3.3 3.465
VDD Power Supply Voltage V
-12,-15 3.0 3.3 3.6
" Input High Voltage 2.0 - VDD + 0.3** V
VIL Input Low Voltage - 0.3* - 0.8 V
* : -1.0V with a pulse w1dth of 20% . tRC min(4ns max)
** : VDD+1.OV with a pulse width of 20% .tRC min(4ns max)
2000-07-11 2/8
TOSHIBA TC55V8200FT-10,-12,-15
DC CHARACTERISTICS (Ta = ty' to 70°C, VDD = 3.3V i 5% :-10, VDD = 3.3V i 0.3V : -12,-15)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input Leakage Current
. V =0 to V -1 - 1 A
(Except NU1 pin) IN DD #
E=V|H or W=V|L or oi-N/m
lLo Output Leakage Current VOUT= 0 to VDD - 1 - 1 yA
Input Current VIN = 0 to 0.8V - 1 - 20
h(NUI) (NU1 . ) prA
pln V|N=0 to 0.2V -1 - 1
IOH = - 2mA 2.4 - -
VOH Output High Voltage
lou-- -10OA Voo-0.2 - - v
IOL = 2mA - - 0.4
VOL Output Low Voltage
IOL=100#A - - 0.2
E: VIL, lout = 0mA tcycle =10ns - - 430
IDDO Operating Current a = " tcycle =12ns - - 400 mA
Other Inputs = I/oo - 0.2V or 0.2V tcycle =15ns - - 37o
|DDS1 E: VIHI Other Inputs-- " or " - - 105
Stand by Current E = VDD - 0.2V mA
loose - - 4
Other lnputs=Voo- 0.2V or 0.2V
CAPACITANCE (Ta = 25°C,f = 1.0 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 6 pF
CI/O Input/Output Capacitance VI/o = GND 8 pF
Note: This parameter is periodically sampled and is not 100% tested.
OPERATING MODE
MODE tr E WE I/OI to I/O8 POWER
Read L L H Output IDDO
Write L X L Input IDDO
Outputs Disable L H H High Impedance IDDO
Standby H X X High Impedance IDDS
X .' Don't care
Note: The NU1 and NU2 pins must be left unconnected or tied to GND or a voltage level of less than 0.8 V.
You must not apply a voltage of more than 0.8 V to the NU1 and NU2.
2000-07-11 3/8
TOSHIBA
TC55V8200FT-10,-12,-1 5
AC CHARACTERISTICS (Ta = 0° to 7ooc(Note 1), VDD = 3.3V l 5% :-1o, VDD = 3.3V i o.3v:-12,-15)
READ CYCLE
SYMBOL PARAMETER TC55V8200FT-10 TC55V8200FT-12 TC55V8200FT-15 UNIT
MIN MAX MIN MAX MIN MAX
tec Read Cycle Time 10 - 12 - 15 -
tAcc Address Access Time - 1O - 12 - 15
tco Chip Enable Access Time - 10 - 12 - 15
tog Output Enable Access Time - 5 - 6 - 8
tOH Output Data Hold Time from Address Change 3 - 3 - 3 - ns
tcoe Output Enable Time from Chip Enable 3 - 3 - 3 -
tOEE Output Enable Time from Output Enable 1 - 1 - 1 -
tCOD Output Disable Time from Chip Enable - 6 - 7 - 8
tooo Output Disable Time from Output Enable - 6 - 7 - 8
WRITE CYCLE
TC55V8200FT-10 TC55V8200FT-12 TC55V8200FT-15
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
twc Write Cycle Time 10 - 12 - 15 -
twp Write Pulse Width 7 - 8 - 10 -
tcw Chip Enable to End of Write 8.5 - 9 - 11 -
taw Address Valid to End of Write 8.5 - 9 - 11 -
tus Address Setup Time 0 - 0 - 0 -
tum Write Recovery Time 0 - 0 - 0 - ns
tos Data Setup Time 6 - 7 - 8 -
tDH Data Hold Time 0 - 0 - 0 -
tOEW Output Enable Time from Write Enable 1 - 1 - 1 -
toow Output Disable Time from Write Enable - 6 - 7 - 8
AC TEST CONDITIONS Lig._1 3.3V
Input Pulse Level 3.0V/0.0V
Input Pulse Rise and Fall Time 2ns 12000
. . l/O Zo=500 IIOpin
Input Timing Measurement 1.5V
Reference Level RL = 509 CL = 5pF 8700
Output Timing Measurement 1.5V CL = 30 'CC J
Reference Level h--- 1.5V (For tcos, tow tcoo,
Output Load Fig. 1 tooo, tOEW and toow)
2000-07-11 4/8
TOSHIBA
TIMING DIAGRAMS
READ CYCLE (See Note 2)
TC55V8200FT-10,-12,-1 5
ADDRESS
tCOD (See Note 6)
tpEE (See Note 6)
tCOE (See Note 6)
tooo (See Note 6)
VALID DATA OUT
INDETERMINATE
WRITE CYCLE 1 (W CONTROLLED) (See Note 5)
INDETERMINATE
ADDRESS X X
tas twp twe
Wt? N "N 7!
L. tcw '
"ttl'" R if
I toow (See Note 6) tOEW (See Note 6)
o 5?S?S?SNSNS?S?S?f_20000txx20_f?9SNS?S?S?S?9'
. ....
Dout 5NS?SNSNSNSNSt'
ooooooooo¢
ooooooooooo ooooooooo
2SNSNS?S?SNS?t. 2SNS?f?SNS?SN
' '0'! c'. 2S?f e e o e 2S?S?SNS?SNS?k'
o 'EST' ?SF. 'rNSNS6NSNSi
2S?SNSNRS?SN o
m _ Amos...” 2SNS?kxxxxxxxxxxxxxxxxxSNS?S?SNSNSN
INDETERMINATE
(See Note 4)
toc INDETERMINATE
DATA I N X
2000-07-11 5/8
TOSHIBA TC55V8200FT-10,-12,-15
WRITE CYCLE 2 (Cl CONTROLLED) (See Note 5)
4 twc _
ADDRESS X X
Us twp tWR
WE _ if
"'% tcw
-- S , f
_ r , r LODW(See Note 6)
t (See Note 6)
Dout COE y
INDETERMINATE tos tDH
Din VALID DATA IN
2000-07-11 6/8
TOSHIBA
TC55V8200FT-10,-12,-1 5
Note: (1) Operating temperature (Ta) is guaranteed for transverse air flow exceeding 400
linear feet per minute.
(mm remains HIGH for the Read Cycle.
(3) If tTrif goes LOW coincident with or after
at high impedance.
1Trfif goes LOW, the outputs will remain
(4) If UE goes HIGH coincident with or before 1TrtT goes HIGH, the outputs will remain
at high impedance.
(5) If tTE is HIGH during the write cycle, the outputs will remain at high impedance.
(6) The parameters specified below are measured using the load shown in Fig. 1.
(A) tCOE, tOEE, tOEw ......
(B) tCOD, tODO, tODw ......
Output Enable Time
Output Disable Time
A 0.2 v
INDETERMINATE
V 0.2V
VALID DATA OUT X
I INDETERMINATE A
2000-07-11 7/8
TOSHIBA TC55V8200FT-10,-12,-15
PACKAGE DIMENSIONS
Plastic TSOP (TSOPII 54-P-400-0.803)
Unit in mm
i'ipasrmummwuupspppssppi2i' -
IO.16:0.1 _‘ A
11.76 :02
tire""'?:.,,,,":).?,,,)),,',,,::,,?"""""),
0.71TYP L 1 Fa losztgjggm
1; 2222101 J, g ii
'i---' g l
Weight .' 0.559 (Typ)
2000-07-11 8/8
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