TC55V4366FF-150 ,131,072-WORD BY 36-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM
TC55V4400FT-12 ,4,194,304-WORD BY 4-BIT CMOS STATIC RAMTOSHIBA TC55V44OOFT-10,-12,-154,194,304-WORD BY 4-BIT CMOS STATIC RAMThe TC55V4400FT is a 16,777,21 ..
TC55V4400FT-12 ,4,194,304-WORD BY 4-BIT CMOS STATIC RAMTOSHIBA TC55V44OOFT-10,-12,-154,194,304-WORD BY 4-BIT CMOS STATIC RAMThe TC55V4400FT is a 16,777,21 ..
TC55V8128BFT-12 ,TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TC55V8128BFT-12 ,TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TC55V8128BJ-10 ,TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
TC9400CPD , VOLTAGE-TO-FREQUENCY/FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400CPD , VOLTAGE-TO-FREQUENCY/FREQUENCY-TO-VOLTAGE CONVERTERS
TC9400F ,SUMM-DELTA MODULATION SYSTEM DA CONVERTER WITH A BUILT-IN 8-TIMES OVER SAMPLING DIGITAL FILTER/DIGITAL ATTENUATORTC94OOF/NT(‘annF T(annNI Slit'--.---- ' I Slit'--.---."E-A MODULATION SYSTEM DA CONVERTER WITH A BU ..
TC9402CPD , VOLTAGE-TO-FREQUENCY/FREQUENCY-TO-VOLTAGE CONVERTERS
TC9402CPD , VOLTAGE-TO-FREQUENCY/FREQUENCY-TO-VOLTAGE CONVERTERS
TC9404FN ,SUMM-DELTA MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTERTC9404FNT(‘QAnAFNv I v I I I‘Z-A MODULATION SYSTEM DA CONVERTER WITH ANALOG FILTERTC9404FN is a 2'n ..
TC55V4366FF-133-TC55V4366FF-150
131,072-WORD BY 36-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM
TOSHIBA TC55V4366FF-167,-150,-133
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131,072-WORD BY 36-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM
DESCRIPTION
The TC55V4366FF is a 4,718,592-bit synchronous pipelined burst static random access memory (SRAM)
organized as 131,072 words by 36 bits. It is designed for use as a secondary cache to support microprocessor
units equipped with burst functions. A 2-bit burst address counter and control logic is integrated with a 128 K
M 36 static RAM. All inputs except out ut enable OF are synchronized to the rising edge of the CLK input.
Read operations are initiated by the ADJSP address status processor input or ADSU address status controller
input. Subsequent burst addresses can be generated internally under control of the ADV address advance
input. Write operations are internally self-timed and are initiated by the rising edge of CLK. Byte write
enables (BWl through BW4) allow one- to four-byte write operations to be performed. The TC55V4366FF uses
dual power supplies (3.3 V for core and 3.3 V/2.5 V for output buffer) and is available in a low-profile 100-pin
plastic QFP (LQFP).
FEATURES
Organization as 128K words by 36 bits.
Fast cycle time of 6ns per minimum (167MHz maximum)
Fast access time of 3.5ns maximum(from clock edge to data output)
Pipelined burst operation
2-bit burst address counter (interleaved or linear burst sequences)
Synchronous self-tiid write (global write or byte write)
Stop-clock mode for power down
Snooze mode pin(ZZ) for power down
2cyc1e Enable, 1 cycle Disable
LVTTL compatible interface
Dual power supply (3.3V for core and 3.3 V/2.5V for output buffer)
Available in 100-pin LQFP package(LaFP100-P-1420-0.65K:0.65mm pitch, 1.6mm height, typically 0.56
grams)
PIN ASSIGNMENT (TOP VIEW) PIN NAMES
A0toA16 Address Inputs
l/OI to I/O32 Data Inputs/Outputs
IIO P1 to I/O P4 Parity Inputs/Outputs
CLK Clock Input
E,m, CE2 Chip Enable
WSP Address Status Processor Input
W5C Address Status Controller Input
W Address Advance Input
"ttti/ Global Write Enable Input
BV/i? Byte Write Enable Input
Wtom Byte Write Enable Inputs
E Output Enable
MODE Mode Select Input
22 Snooze Input
NU Not Usable Input
VDD Power Supply for Core
Vss Ground for Core
VDDQ Power Supply for Output Buffer
2Ju'ts;trryrur-0:DuJinauJu"Ds-rNtr3s;tuuQ Vsso Ground for Output Buffer
§<<<<<<2239222222222 NC No Connection
000707EBA2
O TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction
or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizin TOSHIBA
products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a mal unction or
failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent
TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor
Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
0 The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office
equipment, measurina equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for
usage in equipment t at requires extraordinarily high quality and/or reliability or a malfunction or failure of which m.ay cause loss of human life or
bodily injury CUnintended Usage"). Unintended Usage include atomic ener y control instruments, airplane or spaceship instruments, transportation
instruments, traffic signal instruments, combustion control instruments, me ical instruments, all types of safety devices, etc.. Unintended Usage of
TOSHIBA products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade laws.
0 The information contained herein is presented only as a guide for the ap lications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights 0 the third parties which may result from its use. No license is granted
b implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
2002-09-25 1/20
TOSHIBA TC55V4366FF-167,-150,-133
BLOCK DIAGRAM
17 17 15 17
A163 D Address Q
Register
A1 to A0
ADV Binary Q1
Counter and Al'
BWI Byte 1 Q Byte 1
D Write Register Write Driver
. Byte l Q fytt2, Memory
D Write Register Write Driver Cell Array
BW3 Byte 3 Q Byte 3 128Kx9x4
D Write Register Write Driver (4,718,592)
BW4 Byte4 Q Byte4
D Write Register Write Driver
E Enable
D Register Q Q Q Q Q D D D D
m Byte 1 Byte 2 Byte 3 Byte 4 Output
Input Input Input Input Register
Enable Delay Register Register Register Register Q Q Q Q
CE2 D Register Q D D D D
Output
fl Buffer
l/Ol to |/O8,
IIO P1
I/O9 to I/O16,
l/O P2
l/O17 to |/024,
l/O25 to l/O32,
l/O P4
2002-09-25 2/20
TOSHIBA
TC55V4366FF-167,-150,-133
PIN DESCRIPTIONS
PIN NUMBER
SYMBOL
DESCRIPTION
37, 36, 35, M, 33, 32,
100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50
A0to A16
(synchronous)
Synchronous Address Inputs
Registered on the rising edge of CLK. Address
inputs must meet the specified setup and hold
times with respect to the CLK rising edge when
the chip is enabled.
93, 94, 95, 96
BW1, BW2, BW3, BW4
(synchronous)
Synchronous Byte Write Enables
These active low inputs control byte write
operations when BWE is low. W controls
POI through l/O8 and |/OP1. m controls
l/O9 through |/O16 and IIO P2. BTW controls
l/O17 through l/O24 and " P3. W controls
I/O25 through l/O32 and IIO P4.
For byte write operations, when any of these
four inputs go Low, all outputs go to high
impedance.
(synchronous)
Synchronous Byte Write Enable
This active low input controls byte write
operations.
(synchronous)
Synchronous Global Write
This active low input controls 32-bit write
operations independent of the BWE and 3W to
W inputs.
Reference Clock
All synchronous input signals are registered on
the rising edge of CLK. Synchronous signal
timings are measured from the rising edge of
CLK. Synchronous input signals must meet the
specified setup and hold times with respect to
the rising edge of CLK.
(synchronous)
Synchronous Burst Advance
This active low signal controls the internal burst
address counter after an external address has
been loaded. When Low, the internal burst
address is advanced. When High, the internal
burst address is not advanced. If a write
operation initiated by ADSP is desired, this
signal must be High to write the loaded address
on the rising edge of the first clock after the
assertion of W.
(synchronous)
Synchronous Address Status Processor
This active low signal controls the burst start by
registering a new external address. The write
enables(W,m, BW1 to W) are ignored at
the assertion of WSP and a read operation is
initiated. Subsequent operations are dependent
on the write enables at the rising edge of the
first clock after the assertion of WSP. This
signal is ignored if E is High.
2002-09-25 3/20
TOSHIBA
TC55V4366FF-167,-150,-133
PIN NUMBER
SYMBOL
DESCRIPTION
(synchronous)
Synchronous Address Status Controller
This active low signal initiates a burst read or
write, depending on the write enables(tiN,
W,W1 to W4), by registering a new
external address.
(synchronous)
Synchronous Chip Enable
This active low signal controls the chip status
(enable or disable) and the internal use of
WSP. It is sampled only when a new external
address is loaded.
(synchronous)
Synchronous Chip Enable
This active low signal controls the chip status
(enable or disable). It is sampled only when a
new external address is loaded. It can be used
for memory expansion.
(synchronous)
Synchronous Chip Enable
This active high signal controls the chip status
(enable or disable). It is sampled only when a
new external address is loaded. It can be used
for memory expansion.
(asynchronous)
Asynchronous Output Enable
This active low signal controls all 32-bit IIO
output buffers. It must be high while write
data is being driven prior to the assertion of
the byte write enables(GW, BWE, BW1 to BW4)
following a read operation.
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6,
7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
l/OI to |/O32
lnput/ Output
(synchronous)
Synchronous Data Inputs/Outputs
Byte1 is l/Ol to l/O8, Byte2 is I/O9 to I/O16,
Byte3 is |/017 to l/OM, Byte4 is |/025 to |/O32.
51,80,1,30
l/O P1 to IIO P4
lnput/ Output
(synchronous)
Synchronous Parity lnputs/Outputs
IIO P1 is a parity bit for Byte1 as l/O1 to |/O8.
l/O P2 is a parity bit for Byte2 as I/O9 to l/O16.
IIO P3 is a parity bit for Byte3 as |/017 to l/O24.
l/O P4 is a parity bit for Byte4 as l/025 to l/O32.
(asynchronous)
Mode Select
This signal selects the burst sequence. If High or
not connected, the burst sequence defaults to
Interleaved Burst. If Low, the burst sequence is
Linear Burst.
This input is pulled up internally. Do not alter
the input state while the device is operating.
2002-09-25 4/20
TOSHIBA
TC55V4366FF-167,-150,-133
PIN NUMBER
SYMBOL
DESCRIPTION
(asynchronous)
Snooze
This active high signal is used to place the
device into sleep mode (low power standby
mode). When Low or not connected, the
device remains in the active state. When high,
the device goes into a sleep state, and memory
data is retained. After this signal is deasserted,
the device wakes up when a read or write
operation is initiated by WSP or m. If 22
(sleep) mode will not be used, connect this
input to Vss.
(asynchronous)
Not Usable
This signal is used only by the manufacturer.
This signal must be low or not connected. This
input is internally pulled down.
14, 16, 39, 42, 43, 66
No Connection
These inputs are not internally connected.
15,41, 65,91
Supply
Power Supply
17, 40, 67, 90
Ground
Ground
4,11, 20, 27, 54, 61,
70, 77
Supply
Output Buffer Power Supply
5,10, 21, 26,55, 60,
Ground
Output Buffer Ground
2002-09-25 5/20
TOSHIBA TC55V4366FF-167,-150,-133
OPERATING MODE
(1) Synchronous Input Truth Table
- - - - - 4 1 ADDRESS 5 2
OPERATION CLK CE CE2 CE2 ADSP ADSC ADV WRITE ZZ USED HO, HO P CURRENT
Begin Burst L-YH L L H L x x x L External
Read Address Dout (n) IDDO1
L -Y H L L H H L x H L
Continue Burst L-y H x x x H H L H L Next Burst
Read 6 Address D0ut(n) |DDO1
L -9 H H x x L H L H L
Suspend Burst L -> H x x x H H H H L Current
Read 6 Burst Dout (n) IDDOZ
L -Y H H x x L H H H L Address
. External
Begin Burst L -9 H L L H H L x L L Address
L -9 H x x x H H H L L Current Din (p) N/A
6 Burst
L -+ H H x x L H H L L Address
Coritinue Burst L-y H x x x H H L L L Next Burst .
Write 6 Address Din (p) N/A
L -9 H H X x L H L L L
Suspend Burst L -9 H x x x H H H L L Current
Write 6 Burst Din (p) N/A
L -r H H x x L H H L L Address
Deselected L -Y H H x x x L x x L
L - H L H x L x x x L
L-YH L x L L x x x L None Hi -Z(p) loose
L -y H L H x H L x x L
L -Y H L x L H L x x L
Snooze L -9 H x x x x x x x H None Hi - z (p) |DD53
Note: 1. ZZ input, although asynchronous, is included in this table.
2. Consumption current does not include output buffer current.
3. H means logical High and L means logical Low. M means Don't Care.
4. 1rrltt?CE = L means any one or more of the byte write enable inputs (BWT, BW2, BW3,
Bird) and BWE are Low, or that W is Low. WRITE = H means W and BW-E are
High, or CTGt is High and WtE is Low and all byte write enable inputs are High.
5. (n) and (p) indicate the cycles affected by the synchronous control inputs. (n) is the
next cycle, (p) is the present cycle.
6. When CE = H, A-DSP is disabled (ADSP = X). ADSP = L to avoid redundancy with
the previous truth table entry when CE = H and ADSP = H.
2002-09-25 6/20
TOSHIBA TC55V4366FF-167,-150,-133
(2) Partial Truth Table for Write Enables (Synchronous Input)
- I/01 to l/O8, I/O9 to l/O16, I/OI? to I/O24, I/025 to I/O32,
OPERATION CLK GW BWE BW1 BW2 BW3 BW4 IIO P1 IIO P2 " P3 IIO P4
L -9 H H H x x x x Dout (n) Dout (n) Dout (n) Dout (n)
L -9 H H L H H H H Dout (n) Dout (n) Dout (n) Dout (n)
L x x x x x Din (p) Din (p) Din (p) Din (p)
H L L L L L Din (p) Din (p) Din (p) Din (p)
L H H H Din(p) Hi-Z(p) Hi-Z(p) Hi-Z(p)
H L H H Hi-Z(p) Din(p) Hi-Z(p) Hi-Z(p)
Write L -9 H
H H L H Hi-Z(p) Hi-Z(p) Din(p) Hi-Z(p)
H H H L Hi-Z(p) Hi-Z(p) Hi-Z(p) Din(p)
The other 11 combinations of BW1 to BW4 are also effective.
BW1 controls l/OI to I/08 and IIO P1. BW2 controls I/09 to |/O16and l/O P2.
BW3 controls I/O17to I/O24 and " P3. BW4 controls I/O25 to l/O32 and IIO P4.
Note .' 1. (n) and (p) indicate the cycles affected by the synchronous control inputs. (n) is the
next cycle, (p) is the present cycle.
(3) Asynchronous Truth Table
OPERATION a ZZ ”'20:;"532
Read L L Dout
H L Hi - Z
Write x L Din, Hi -2
Deselected x L Hi - Z
Snooze x H Hi - Z
2002-09-25 7/20
TOSHIBA TC55V4366FF-167,-150,-133
(4) Write Pass-through Truth Table
Previous Cycle Present Cycle Next Cycle
Operation Addr. WRITE IIO Operation Addr. WRITE E a CE2 ADSP ADSC m o5 |/O,|/OP |/O,|/OP
ADSP Initiated Am x L L H L x x L
Read Cycle
Q1 (Am)
ADSC Initiated Am H L L H H L x L
Write Read Cycle
Cycle Ak L Dn (Ak) Qn (Ak)
x H x x x H H L L
Continue
Read Cycle Qn+ ( )
x H H x x L H L L
Note: L Dn (Ak) represents input data for the nth burst address starting from address Ak.
2. Qn (Ak) represents output data from the nth burst address starting from address Ak.
3.n=1,2,3,or4
4. WRITE = L means that any one or more of the byte write enable inputs (BVI, BOT?,
"tTtTrff, Tr1TtT) and BWE are Low, or that tTG?' is Low. WRITE = H means trw- and TrGrrif
are High, or TTG?" is High and "rr1't"''t'''t''t" is Low and all byte write enable inputs are High.
(5) Interleaved Burst Sequence (MODE Input=NC or VDD)
Bit Order l A16 A13 ............. A3 A2 A1 A0
The lower 2 bits are internally generated from the external address.
1st Address 2nd Address 3rd Address 4th Address
(External) (Internal) (Internal) (Internal)
XX ...... XXOO XX ----- XX01 XX ------ XX1 0 XX ...... XX1 1
XX ...... XX01 XX ...... XX00 XX ...... XX1 1 XX ...... XX10
XX ...... XX1 0 XX ...... XX1 1 XX ...... XXOO XX ...... XX01
XX ...... XX1 1 XX ...... XX10 XX ...... XXO1 XX ...... XXOO
The burst address wraps around to its initial state.
(6) Linear Burst Sequence (MODE Input=Vss)
Bit Order : A16 A13 ............. A3 A2 A1 Ao
The lower 2 bits are internally generated from the external address.
1st Address 2nd Address 3rd Address 4th Address
(External) (Internal) (Internal) (Internal)
xx ------ xxoo xx ------ XX01 XX ------ XX10 XX ------ XX1 1
xx ...... XX01 xx ...... XX10 XX ...... XXI 1 XX ...... xxoo
XX ...... XX10 xx ------ XX1 1 XX ------ xxoo XX ...... XX01
xx ------ XXI 1 xx F..... xxoo XX ------ XX01 XX ------ XX10
The burst address wraps around to its initial state.
2002-09-25 8/20
TOSHIBA TC55V4366FF-167,-150,-133
(7) Stop-Clock Mode for Power Down
The TC55V4366FF achieves low power standby mode by stopping the clock input.
It can retains all state and data values even though the clock is not running.
To achieve the lowest possible power operation, the following signal states are required.
i) Clock is Low
ii) Control signals are inactive (for example, EST is High)
For the lowest possible power consumption during stop-clock mode, the address inputs should be
driven to MOS level (VIH Le VDD - 0.2V or VIL s 0.2 V), and the data inputs should be driven
to MOS low level (VIL s 0.2V).
. Clock restart sequence
The device can be waked up by the first rising edge of the clock signal after having been
in power down mode.
ADV i, l /
Data (out) -i-i-a Q(A1)
ADSP CLK Stop Wake up ADSP
Initiates ( Continue ) ( Initiates )
Burst Read Burst Read Burst Read
i) Stop-Clock Timing for Read Operation
2002-09-25 9/20
TOSHIBA TC55V4366FF-167,-150,-133
ADSC N l / l l
Addr l l
_.................-...- I I I
B E N i I I I
ADV l l l
Data (in) " or " Fixed I l
High-Z I l l
Data (out) I I I
KDSC CLK Stop Wake up ADSC
Initiates ( Continue ( Initiates
Burst Write Burst Writ Burst Writ
ii) Stop-Clock Timing for Write Operation
CLK If-h 'f-I 'f-, If-h 'f-"
ADSC i' L'.,? 1cil/-scis/-'i-
Data (in) -i-i-( " or 1hLIFixed
High-Z I
Data (out) Data )(i)( Date ) ',
Continue CLK Stop Wake up
Burst Read (Deselected) (Deselected)
iii) Stop-Clock Timing for Deselect Operation
2002-09-25 10/20
TOSHIBA
TC55V4366FF-167,-150,-133
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage -0.5 to 4.6 V
VDDQ Output Buffer Power Supply Voltage - 0.5 to VDD V
" Input Terminal Voltage - 0.5 * to 4.6 V
VI/o Input/Output Terminal Voltage -0.5* to VDDQ+0.5** V
PD Power Dissipation 1.2 W
Tsolder Soldering Temperature (10 s) 260 ''C
Tstrg Storage Temperature -65 to 150 ''C
Top, Operating Temperature - 10 to 85 ''C
* .' -1.5V with a pulse width of 20% "KC min
** : Vmoa+ 1.5V with a pulse width of 20% . tKC min
DC RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 3.1 3.3 3.6
VDDQ Output Buffer Power Supply Voltage 2.3 - 3.6
Input High Voltage for Address and . 1.7 - VDD+0-3
VIH Control pins(except IIO and Mode pin) V
Input High Voltage for IIO pins 1.7 - Vooq+0.3**
V.H1 Input High Voltage for MODE pin Vorr-0.3 VDD VDD+0.3
" Input Low Voltage -0.3* - 0.7
V|L1 Input Low Voltage for MODE and NU pins -th3 0.0 0.3
Note: NU pin must be low or not connected.
* : -1.0V with a pulse width of 20% ~th min
** .' Vmoa+ 1.0V with a pulse width of 20% . tKC min
You must not apply a voltage of more than 0.8V to the NU.
2002-09-25 11/20
TOSHIBA TC55V4366FF-167,-150,-133
DC CHARACTERISTICS(Ta = 0° to 70°C, VDD = 3.1V to 3.6V, VDDQ = 2.3V to 2.7V or 3.1V to 3.6V)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input Leakage Cu rrent
. v = t v - - Il
(Except MODE,ZZ, NU pins) IN 0 o DD ”A
Device Deselected or
ILO Output Leakage Current Output Deselected, - - i1 pzA
VOUT= 0 to VDD
V =V V - . V -1 - 1
MODE pin IN DD to DD 0 3
VIN = 0 to 0.3V -100 - 1
v =v t 2. v -1 - 1
ll Input Current . IN DD 0 0 00 [1A
22 pm v.N=o to 0.8V -1 - 20
VIN = 0 to 0.3V -1 - 1
NU pin v.N=o to 0.3V -1 - 1
I = -8mA 2.4 - -
vDDQ = 3.3V OH
I lou.-- - 100PA VoDa-0.2 - -
VOH Output High Voltage
IOH = - 2mA 1.9 - -
VDDQ = 2.5V
Iori= -100PA VoDQ-0.2 - - v
loL=8mA - - 0.4
VDDQ = 3.3V
v o t t L v It k:n--100szA _ - 0.2
OL u pu ow o age loL=2mA - - 0.4
VDDQ = 2.5V
IOL=100,uA - - 0.2
Device Selected, |out=0mA 167MHz - - 370
|DDO1 Operating Current All inputs--Ve/NhL 150MHz - - 355 mA
CLK 2 tKC min 133MHz - - 330
. Device Selected, |out=0mA 167MHz - - 330
IDDO2 2trting Current ADSC, ADSP, ADV 2 " 150MHz - - 315 mA
( e) All inputs=Ve/NhL, CLK 2 th min 133MHz - - 290
Device Deselected, 167MHz - - 110
IDDS1 52::de CP’rent All inputs S v.H/V.L 150MHz - - 105 mA
( running) CLK 2 th min 133MHz - - 100
Device Deselected,
IDDSZ Standby Current All inputs s VDD - 0.2V or 0.2V, _ - 3 mA
CLK frequency = OH:
hil . , ZZ--VOD-th2V,
IDDS3 SHr-Io:ze Current w I e 22 Pin IS All inputs--Ve/NhL - - 3 mA
lg CLK 2 tKC min
d . 22 E 0.2V, Chip Deselected
|DD54 Snooze Current urlng CLK s 0.2V, ADSP, ADSC--VDD-0.2V - - 3 mA
Stop-Clock Mode All inputs E 0.2V
CAPACITANCE (Ta = 25°C, f=1.0MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
C Input Capacitance Vm: = GND 5 pF
Input Capacitance for MODE, ZZ, NU pin " =GND 8 pF
CI/o Input/Output Capacitance VI/o = GND 6 pF
Note: This parameter is periodically sampled and is not 100% tested.
2002-09-25 12/20
TOSHIBA
TC55V4366FF-167,-150,-133
AC CHARACTERISTICS(Ta = 0° to 70°C, VDD = 3.1V to 3.6V, VDDQ = 2.3V to 2.7V or 3.1V to 3.6V)
TC55V4366FF-167 TC55V4366FF-150 TC55V4366FF-133
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
th CLK Cycle Time 6 - 6.6 - 7.5 -
tKH CLK High Pulse Width 2 - 2.2 - 2.5 -
tKL CLK Low Pulse Width 2 - 2.2 - 2.5 -
tKQv Access Time from CLK - 3.5 - 3.8 - 4
tKQX Output Hold Time from CLK 1.5 - 1.5 - 1.5 -
tKQLZ Output Enable Time from CLK 0 - 0 - 0 -
tKQHZ Output Disable Time from CLK 1.5 3.5 1.5 3.8 1.5 4
tGQV Access Time from a - 3.5 - 3.8 - 4
tGQLZ Output Enable Time from E 0 - 0 - 0 -
tGQHZ Output Disable Time from E - 3.5 - 3.8 - 4
tas Address Input Setup Time from CLK 1.5 - 1.5 - 1.5 -
tAH Address Input Hold Time from CLK 0.5 - 0.5 - 0.5 -
- - ns
tADSS ADSP, ADSC Input Setup Time from CLK 1.5 - 1.5 - 1.5 -
tADSH ADSP, ADSC Input Hold Time from CLK 0.5 - 0.5 - 0.5 -
tAVS ADV Input Setup Time from CLK 1.5 - 1.5 - 1.5 -
tAVH ADV Input Hold Time from CLK 0.5 - 0.5 - 0.5 -
tws GW, BWE, BW1 to BW4 Input SetupTime from CLK 1.5 - 1.5 - 1.5 -
tWH GW, BWE, BW1 to BW4 Input Hold Time from CLK 0.5 - 0.5 - 0.5 -
tces E, E, CE2 Input Setup Time from CLK 1.5 - 1.5 - 1.5 -
tCEH E, E, CE2 Input Hold Time from CLK 0.5 - 0.5 - 0.5 -
tDs Data Setup Time from CLK 1.5 - 1.5 - 1.5 -
tDH Data Hold Time from CLK 0.5 - 0.5 - 0.5 -
tzs ZZ Standby Time 5 - 5 - 5 -
tZR 22 Recovery Time 6 - 6 - 6 -
tsz Output Disable Time from 22 - 2 - 2 - 2 cycle
AC TEST CONDITIONS Fig.1
VDDQ=2.5V VDDQ=3.0V 2.5V 3.3V
Input Pulse Level 2.5V/0.0V 3.0V/0.0V
850Q/295Q
Input Pulse Rise and Fall Time 1.8ns 2.0ns l/O 20: 509 l/Opin
nput Timing Measurement 1.25V 1.5V
Reference Level RL = 500 CL = SPF 8500/2170
CL = 30pF
Output Timing Measurement VDDQ VDDQ V
Reference Level 2 2 VL = L'Q
2 (For tkara, tKQHir,
Output Load Fig. 1 Fig. 1 thLz, and tGQHZ)
2002-09-25 13/20
TOSHIBA TC55V4366FF-167,-150,-133
TIMING DIAGRAMS
READ CYCLE
I Single Read I Burst Read ,Deselected
_ - th _
.:4',-'-t:'
i... tADss #EurtADSH 1tI
ADSP _..:"'''':".::.)''"'.:..:.?,'?,',,:":.".:. "l)'iid'itl/yi/ 'ii)"'..:':.:-'"..-.:;-'-.'...-')):.."'.,
. i..' tADss4+11tAL>5H , tADss 4+1tADSH i.:
me _i:.rvr,irv:.:.r 2221511222222W‘2/22
ADv2/ 2 w,,),''..; _,._i._,:',Ctls,/,s"sdr.:i:'._', 1222221222 (_"'- 2/ s..)
i.ADV suspends bu r511.
A‘SXZ221222A222 x.i? "j'"? /i? wir- 2 2/ x,s.",":
. tws14+14+1’EWH 1
Gw//222W1WWWWWWW2V2
Ak1’1k
BI/VE // A.:.'?"'-'',..-':':";;')'.,.-:.'':'-.'',.'::. ‘22 ey'::.. xgr'i., 'ey..:.'' '.',:ixari',', 22/22
i.' tces 4+14+tCEH 1
%/////////////2/22////////
i' tCES , '14 r tCEH 1 CT misks AD-SP.:."
"'izv//:..'rttj'.i.'..,a,C //'.,rca.i'.'' 2 /yd,'.s:/ /s.'rs? 2F 'ar.. ‘2/2/ "j/i/trv/ si.",',
'.: tCES tCEH :..' W, CE2, CE2 state is sam'Ped only when a new addres'.s is loade/q1/. tCES 14+14+1tCEH i'
CE2 // /2’/ 21/ // si? // // /.// 'tr"f..:. 'F"e.t' /-
1 tCEs1w1v1’fCEH 1 i..' i," Dese(ected 111111111 t::ij2 or iii",., tCES "1w tCEI-I 1
222222 As.'.""? str" sir" As'.;'" '/i/.Ci'"(p''''t.
t5Ti- , i.' 'ist i' 1\
Din i' . H I I .' I Z I
[lg to |/O32,1 , ttsos). d H2 i i 1 1 1 Burst wr_1aps aroun1d
" P1 to " R4 1 ' d N ' 1 1 1 1 1 to its initial sta te.:"
Dout I-_i-,-.i-.i-tg S-iHiiFA2))(iN2s2y)(iii)( i Q3(A2) 22(2—
l/OI to l/O32/ i' tKQLZ1H i 1 i i 1 i'
l/O P1 to l/O P14 : 1=' s 3 s 5 ltvt, 5
'ff72f) Don t care
, Indeterminate
1. Q1(A2) represents output data from 1st burst address starting from address A2. Q2(A2)
represents output data from 2nd burst address starting from address A2.
2. ZZ is Low.
2002-09-25 14/20
TOSHIBA TC55V4366FF-167,-150,-133
WRITE CYCLE
Single Write I Burst Write .Deselected
-..ct.',-"t il E
CLK . . E E . .
i.... tADss E tADSH EtKH EE'E i,' taoss 4+E4+ tADSH. 'ipuy-ss, is ti)ocked bYE CE h'ghE . E
ADSP 5% /riRa)x1r//l'1, %Ԥ3//2/ "sit _yt..z.__''Ehilh/':_:':.:_xgr.'...r'_.zer_.i.
'i' tADSS4+E4+|1AE>SH 'i' i,' taoss |4+E4+|tADSH i.," ' .
ADSC EW "'f" "f // '.:._eiti.i. WE eirii..... 'tsir/si.'.
"iAi:-ou mujt be high_ Efor Aiisp Ewrite. i.' tAvs "Ev tAVH i.' 7E" tAVH i'
ADV/E/ 2///2"///2“/2%//2‘E%%5E2V2// // 2”
.ADV suspends bu rs;
A‘6E322Fj/22A222 2/ /si'? /_// ////XA3// /
E tws|4+E4+|tWH 'i' i' tws E i
GW// //"2.f'"f...i'le'v:r(.:R.iil.i-i..i-ilj
i .11 5 GW pEerforms wErite independent ofE BV/E andE BVI to B\_N4.
: tws4 w: tWH :
swe2/ 2225/2222 2/ 22 1//.../trr1,.r/'/t, wi:,.";
E22 24222 xr-,): /s,ei.,.r/ s'.? 2/2xE X222 xr'c-
Any:.' iof CE, CEz',
E tCEs tt' tCEH E E CE masks ADSEP. tCEs 54+ tCEH i..' CE2 Edeselects. E
E1//:E /.,._la,'i:.._jc_,"'zs,,.is:/CE/.l.'1atssA/Ds',.::. ‘EEE .
tces tCEH i.' E tWi, CEEZ, CE2 staEte is samlyed only when a neEw address':, is loadecEE. ..i
CE2 1E/ 11/ XA:::. /" 1/ "':,'" 1/ "f" 11/ AV A" .i.V'" w/ef'
i' tCEsE E4+EtCEH i' i:" '...' i" tCES‘ENE'EECEH ..:"
ce22 "::i1t;''1o..ir/i.r'vro."'.'.sv._,..'r /f(.///(. 2222222
@22222222/
I/O1DEIE/EO32E ED513101? ')'ir)rsoi)2eiir2sL, 02(E/u) D3042) vie:.'."))'"...."..:')':'.':..:..-'-':.-:'.":.
be PE‘Elotol/O $4] F4 EEGQHZ i." -:..' i.." i... i.." a
l/01tol/O32/ .
|:|/OP1to|/OF‘E4 E i
b/7,7fg'j' Don't care
Indeterminate
1. D1(A2) represents input data for 1st burst address starting from address A2. D2(A2)
represents input data for 2nd burst address starting from address A2.
2. ZZ is Low.
2002-09-25 15/20
TOSHIBA TC55V4366FF-167,-150,-133
WRITE CYCLE (BYTE WRITE TIMING)
Write Pass-through
I Byte Write I Burst Read
'iAro-s/ is bflocked by; CE high.I .
'.iv'sri:'. W/// 2/ //g
'i." ii,' tADSS |4+E4+|1ADS i:.,' E .
ADSC gW//2fi|‘V////W////V/////WWW
-ADV must be high! :for AT..' :wrlite i' tAvs vs, tAVH g
m _.jrcs,i.sr/ wj..r" 222/222 2222; ':'yzis/.'us::i.'.
.:: 15AVS+€15AVH E
AIS; 22W 222(A2x2/2/2A3x2/2/2A4x2/2/ "i/y" sj.,r vi';"";
E wsAetwH :..'
GWgK///// 2/ //t‘w2:- ///W////WWW
l i tws :>Z‘>tWH g :..' tWS ryr tWH I
awe I22 2/ /si"ri2'/"::_, r/22I/222xI/2Y/2V/2
BWI I222 Ai,)" 22222222 At,'' Ai'.':'" /v.'r'.,i? ws',.,
tws I tWH i' tws" tWH i
"fiv-e, 32/22 /si:.p" "i...r"Csi::".i. 2/22/22 "e.";" 2/ /i..e 22
i.' tCEs4->g tCEH i." E E masks AD'SgP- tcEs"."tcsH i."
CE/flx/fl/fi flfly/flx'y/l zE("fV/l
: CE, CE2, CE2 staie is sampte only I
Deseieci.ted with CE2 or CE2 tc CES tCEH I ew address IS loaded
@222 2.: x222 222; 2 "/)//vr'yrrij' tii...))''" "',':." Ai,:'""" v.,'"
.' AL'AK .
5 ICES . ICE“ 5 tces tCEH 5
cxz/ M; // ////////:‘itcEs tCEHi. : , i.' i' i.' i'
"ro-ir.::'' é////////////////2
Din1 to i.' i.' i.' i.' ti IH/H i.'
Din 8 , , , , H.016“) ,
Din(l/O P1) i' E E E // : Fd E
. . I I I I I t :' t i' :.'
Din9 to 5 ':kKt-oH; E E E 5 gi; : 21 =‘tKQV. I tKQv
Din32 , .' , , , 1 'g6t'aW), , I
Din(l/O P2 to Up P4) it OX 5 E I I 2 I t DL? I t
Doutl to I E I E I i.' i' E M. 5 5:1: 3 tie. 3 4:5: :
Dout 8 : E i 5 , , .' , 8% BW w, ‘52:? Q3(F4)
Dout(l/O P1) ; . : : : : I I a i I
Dout 9 to : : i i i i i i 2it? gga 14:5: EM. i
Dout 32 5 5 : : : : : : 2& 18i ‘12:,” 128 Q3CA4)
Dout(l/O P2 toil/O P4) : .
'ff/A, Don't care
2iggit Indeterminate
1. ZZ is Low.
2002-09-25 16/20
TOSHIBA TC55V4366FF-167,-150,-133
READ / WRITE CYCLE
. . . Output
Single Read I Single Write I Burst Read l Disabled
.i.4_."-/"hi.
':.' tADss . tADSH i1TH tKL:. . tADss 1>E¢>tADSH :..' ':,AD-ss, is blOCked by CT high;
7ir5!ri5 W flmfl/‘5‘%//W% 'f,.i,/Ehl''li:es/,.:.-...er,"'_,":.
5 i' uDssrr'.:euDsH 'i tADss|4+4+|tADsH ':.'
ADSC KV/g 4V/4V/7/WWWWW
:.AiV must be high] :for AD-SP :write. tAVS It.' tAVH i.' .
ADV/X/ // // "s:'rtAvj,'i,.jt't'1::'rxa..::ius::.::'. // // /’
"e, //%%/%AZW%%A3W// Ai'':." // // /:'r..r..y? "a:''';
i tws|4+54+|’EWH 5
GW/ //V//W//WWWWW
tws "i.," tWH i..' tws 4+tWH i..
BWE/i/ 'l'..."'"",'.,:.:'"''"'':.','.'" V/fl‘WWWWW
ssv-viv-e:i/si,.s? / /,w.:'..s? //E+WH/: "sit" /ss:.' // w/so:.,' wvi.t" si,.,'
i: tCES tCEH i.' i CE masks ADSP. tCES "ht tCEH i.'
t:ri/i.rr2li; ///>,\///\//// m//_/ /,,i'.r/ /'
i.' tCES 4+ tCEH i.' . CE; Cij2, CE are sampled only whin a new address is:' 'poaded. i.'
CE2 // /_/%§ trl/(icylr., /// // // tr WI.'..,;'" //
'.: tCES 'ri/r' tCEH '.:
CEZ/ W/flW/flW/fl/fl//
E i.' i' i.' t i.' i.' i.' i.' h i.' :..' i,' i.' js-'':,'.."
i' i..' i," i.' tos gHtDH i.' .' i : .' .' 5
Din f f f f DiI/o1tol/O32,i. g g t; '- n g g i ..' i gt
" P1 to " Pj4 . A GQHZ, 2 s 5 GQHI A
Dout :.." "i.., 'i,, ‘Q1(A:\1) 'i" _..'' _::..., A3))@(02¢A3)@(Q3 €¢A3))@(Q4 Aflfi;
[pt to I/O32,i ]
m Don't care
I/opltovoh4 i KQX i' i' tat..
1. When a write operation follows a rea_doper_atior1, 'tVg must be driven high prior to the
assertion of the byte write enables(GW, BWE, BWI to BW4) and before input data is
applied to avoid data bus contention.
2. ZZ is Low.
2002-09-25 17/20
TOSHIBA TC55V4366FF-167,-150,-133
SNOOZE CYCLE
Single Read I Snooze I Read
i... tADssH tADSH 'ttc, 'tTL':.. 5 hh i.' tADss VrEVrtADSH
ADSP _'._:itisssstt.i_.:.'" (.:%er%r.:..Njr..':.. lngWWW/W
i; 'i' tADSS (+10 '; . i..' '.; . . :'; tADSH§
WC 2 ; . ' 'N: air:..' W m/i.. tirrsi.s? si..,
ADVWW/WWWWWWWWWWWWWW
A1613 '/ii.rtir'i(1-iiiecl.i: xi.'" WWWWW WW s) WW WWWXAZW/
'i' tws [901w :..'
Gvvvii.y" WWWWW/WW s/ry W "sito" wi',/ujics'..i?v':i,
'.: tws4 N rigr r tWH '.:
BweW WWgsW'WWWWW W W W "//iiia//j///,../i1,
'''''''1''h''''(-'ii-,t/-t WW W WW W A:';:?))'),''',.' WW W WW c.',_cii'vt.i.t" W
i..' tCEsH'I tCEH i.'
cEWWg W W /z.',"'.ritis'sz.,'..i? "ir/ W si'? xt.iaj,ihsia/_..v'-ss.."'_
i.' tCEs A io . tCEH i.'
CEZW/Wx'f’ W W /.'.'.//iiirs.'..'.r WW s'-..? WW WWW W /
:..' tCEs ietcEri :..' i..' 'i." i..' i.' .
CE2 /// JV // '/'" (riirrsir /w.f""" // W/ s.,isie'sr:i'.'.'. WW”
_......-...- g : i..' i.' s a s 2
OE i 5 fi_;;‘ E “‘W/ / sf" // j:..aiiirvi.; W;
i," i... i." i..' i.." gg i' i' ..i ()3 .
Di .' a a z A ' a
[IIOHoI/lg32, (i...] g t g t2 gteQHz g
I/oP1tol/oP4.,'. . GQLZE: d i.' i'
Dout-il-i-i-. Q1éA1) 33
l/OI to IIO32, g i' tKQLZZH . ,
|:|/0P1to|/OP4:| tzriz ))
f i. i:.itetc..ax :
ZZ i' i E §;E i'
Don' t care .
:;: : icfiiiiiii
gii55) /|ndeterminate
2002-09-25 18/20
TOSHIBA TC55V4366FF-167,-150,-133
NOTE : 1. Do not apply opposite data polarity to the I/O pins when they are in the output state.
2. Output enable and output disable times are specified as follows using the output load
shown in Fig. 1.
(a) tKQLz, tKQHz
CLK _/t_/tV-hc/tt
(See Note 1) (See Note 1)
ADSP N
7ri5TR5 x1
)CE2, iiii)(
KQg 0.2V KQHZ
Dout . y,
VALID DATA OUT
(See Note 2)
(See Note 3)
I. Input states are defined in the Synchronous Input Truth Table.
2. If the device was previously deselected, when the device is selected, the
output remains in a high impedance state in the present clock cycle
regardless of UE because of the output enable delay register.
Valid data appears in the second clock cycle when tTE' is low.
3. When the device is deselected, the output goes into a high impedance
state in the present clock cycle regardless of UE.
(b) tGQLz, tGQHz, tZHz
OE, 22 y, 7 tsz
tGQLZ tGQHZ
- th2V tt v0.2V
Dout JI I
. VALID DATA OUT x is5-
o.2v '' "om/
2002-09-25 19/20
TOSHIBA
PACKAGE DIMENSIONS
Plastic LQFP (LQFP100-P-1420-0.65K)
TC55V4366FF-167,-150,-133
Unit in mm
22.0k0.2
20.0i0.1
rcls_Eg:z- E50
o cas ala
cm :1:
Eu: :1:
Eu: :1]:
ED: :1:
LIL IEI
T" Chl
Iflz, 'i'lil $1 9;}
:2: IIEU o c!
ELI: Zn] v C)
El]: ma T" Y"
CI :1:
E1]: :1:
ED: ala
Si C) gil
100% f“: 31
’k1HEHHHE i"ea1?"e"1"""l'e)-------
O 575 0.32+O'08 -
. TYP li' -0.07 ['y'irgLjjidfii
V. (ii?
Weight: 0.56g (typ)
2002-09-25 20/20
:
www.loq.com
.
