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TC55V1664J-12-TC55V1664J-15
65,536-WORD BY 16-BIT CMOS STATIC RAM
TOSHIBA TC55V1664J-12,-15
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
65,536-WORD BY 16-BIT CMOS STATIC RAM
D E S C R I PT I O N
The TC55V1664J is a 1,048,576-bit high-speed static random access memory (SRAM) organized as 65,536
words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed
and low-voltage operation, it operates from a single 3.3 V power supply. Chip enable (CE) can be used to place
the device in a low-power mode, and output enable (tTIT) provides fast memory access. Data byte control signals
(LB, UB) provide lower and upper byte access. This device is well suited to cache memory applications where
high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible.
The T055V1664J is available in plastic 44-pin SOJ packages (400 mil width) for high density surface
assembly.
FEATURES
0 Fast access time (the following are maximum values) 0 Single power supply voltage of 3.3 i" 0.3 V.
TC55V1664J-12: 12 ns TC55V1664J-12: 3.3 V i 5%
TC55V1664J-15: 15 ns TC55V1664J-15:3.3 i- 0.3 V
0 Low-power dissipation 0 Fully static operation
(the following are maximum values) 0 All inputs and outputs are LITrL compatible
Cycle Time 12 15 20 30 ns 0 Output buffer control usiig OE -
Operation (max) 190 170 150 130 mA q 1tfs2ytrifr01 11s1ng LB (101 to 108) and UB
Standby: 2 mA (all devices) 0 Packages:
SOJ44-P-400-1.27 (Weight: 1.64 g typ)
PIN ASSIGNMENT PIN NAMES
TC55V1664J A0 to A15 Address Inputs
A4 E 1 44 1A5 l/OI t1/016 Data Inputs/Outputs
A3 E 2 43 3 A6 CE Chip Enable
A2 E 3 42 II E W Write Enable Input
A1 4 41 JOE -
A0 E 5 40 Cl W _toE, Output Enable
E L 6 39 J E LB, UB Data Byte Control Inputs
l/OI E 7 g 38 I] |/O16 VDD Power (+ 3.3V)
IIOZ L 8 37 I] l/O15
1/03 L 9 w 36 Cl 1/014 GND Ground
I/O4 L 10 , 35 J l/O13 NC No Connection
Yoo L 11 M 3 GND NU Not Used (Input)
IIOS L 13 o 32 :I won
I/O6 E 14 t 31 II |/O11
l/O? E 15 30 II l/OU)
l/O8 E 16 29 II |/09
m E 17 28 J NU
A15 E 18 27 II A8
A14 E 19 26 3 A9
A13 E 20 25 Cl A10
A12 c 21 24 Cl A11
NC E 22 23 II NC
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-18 1/9
TOSHIBA TC55V1664J-12,-15
BLOCK DIAGRAM
a g li,'.', H VDD
9 w Cl
o n: O o MEMORY
a A-o ND
tE g “E CELL ARRAY G
256 x 256 x 16
l/Ol f (1,048,576)
I/O2 m I- a:
{$82 .. CE <2:
I/O5 u, < F- LL
l/O6 g 0 8 2
I/O9 SENSE AMP
l/O11 I- ff, < S f,
l/O12 2 l F- E E
(2Id EF, COLUMN 3::
I/O15 DECODER O m
COLUMN
ADDRESS BU FFER
GENERATOR
A0 A2 A12 A14
A1 All A13 A15
9| El Sol 8‘
MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.5 to 4.6 V
VIN Input Terminal Voltage - 0.5* to 4.6 V
VI/o Input/Output Terminal Voltage - 0.5* to VDD + 0.5** V
Po Power Dissipation 1.2 W
Tsclder Soldering Temperature (10s) 260 °C
Tstrg Storage Temperature - 65 to 150 ''C
Topr Operating Temperature - 10 to 85 'C
*: - 1.5V with a pulse width of 20% . tRC min (4 ns max)
**: VDD + 1.5V with a pulse width of 20% 'tRC min (4 ns max)
1997-06-18 2/9
TOSHIBA TC55V1664J-12,-15
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
- 12 3.135 3.3 3.465
VDD Power Supply Voltage V
- 15 3.0 3.3 3.6
Ihr, Input High Voltage 2.0 - VDD + 0.3** V
" Input Low Voltage - 0.3 * - 0.8 V
*: - 1.0V with a pulse width of 20%-tRc min (4 ns max)
**: VDD + 1.0V with a pulse width of 20%-tRc min (4 ns max)
DC CHARACTERISTICS(Ta = 0° to 70°c,-12: VDD = 3.3V i 5%,-15: VDD = 3.3 , 0.3V)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input Leakage Current
(Except NU Pin) " = 0V to V00 -1 - 1 prA
c-E--)hHorvt/E--1hcoro-E--um
ILO Output Leakage Current VOUT - 0V to V00 -1 - 1 prA
I Input Current VIN = 0 to 0.8V -1 - 20 A
I(NU) (NU Pin) " = 0 to 0.2V -1 - 1 pr
. IOH = - 2 mA 2.4 - -
VOH Output High Voltage I - 100 A V O 2
OH - p DD . V
IOL = 2 mA - - 0.4
VOL Output Low Voltage I 100 A O 2
OL = p - - .
tcycle = 12 ns - - 190
I o . c E = V.L, lout = 0mA tcycle = 15 ns - - 170 A
DDO perating urren Other Inputs = " or VlL tcycle = 20 ns - - 150 m
tcycle = 30 ns - - 130
|DDS1 E = 1hu, Other Inputs = VIH/VIL - - 20
I Standby Current E = VDD - 0.2V 2 mA
DDS2 Other Inputs = Yoo - 0.2 V/0.2V
CAPACITANCE (Ta = 25°C,f = 1.0 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 6 pF
CI/o Input/Output Capacitance VI/O = GND 8 pF
Note: This parameter is periodically sampled and is not 100% tested.
1997-06-18 3/9
TOSHIBA TC55V1664J-12,-15
OPERATING MODE
MODE tTi? ?TE 'flirt'' 'LI)'"" Trg- I/OI to I/O8 l/O9 to I/O16 POWER
L L Output Output IDDO
Read L L H H L High Impedance Output IDDO
L H Output High Impedance IDDO
L L Input Input IDDO
Write L x L H L High Impedance Input IDDO
L H Input High Impedance IDDO
L H H x x
Outputs Disable High Impedance High Impedance IDDO
L x x H H
Standby H x x x x High Impedance High Impedance IDDS
M : Don't care
Note: The NU pin must be left unconnected or tied to GND or a voltage level of less than 0.8 V.
You must not apply a voltage of more than 0.8V to the NU.
1997-06-18 4/9
TOSHIBA
TC55V1664J-12,-15
AC CHARACTERISTICS
(Ta = O°to 70°C (N°te1),-12: VDD = 3.3V , 5%,-15:VDD = 3.3V , 0.3V)
READ_CYCLE
TC55V1664J-12 TC55V1 6641-1 5
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
tRc Read Cycle Time 12 - 15 -
tAcc Address Access Time - 12 - 15
tco Chip Enable Access Time - 12 - 15
toe Output Enable Access Time - 6 - 8
tBA Upper Byte, Lower Byte Access Time - 6 - 8
tor, Output Data Hold Time from Address Change 3 - 3 -
tcoe Output Enable Time from Chip Enable 3 - 3 - ns
toss Output Enable Time from Output Enable 1 - 1 -
Output Enable Time from Upper Byte, Lower
tBE 1 - 1 -
tcoo Output Disable Time from Chip Enable - -
tooo Output Disable Time from Output Enable - -
Output Disable Time from Upper Byte, Lower
tBD - 7 - 8
WRITE CYCLE
TC55V1664)-1 2 TC55V1 6641-1 5
SYMBOL PARAMETER UNIT
MIN MAX MIN MAX
twc Write Cycle Time 12 - 15 -
twp Write Pulse Width 8 - 9 -
tcw Chip Enable to End of Write 10 - 12 -
t Upper Byte, Lower Byte Enable to End of 10 - 11 -
BW Write
tAw Address Valid to End of Write 10 - 11 -
tas Address Setup Time 0 - 0 - ns
tWR Write Recovery Time 0 - 0 -
tos Data Setup Time 7 - 8 -
tDH Data Hold Time 0 - 0 -
tOEw Output Enable Time from Write Enable 1 - 1 -
toow Output Disable Time from Write Enable - 7 - 8
AC TEST CONDITIONS FIG.1 3.3V
Input Pulse Level 3.0V, 0.0V
Input Pulse Rise and Fall Time 3 ns 12000
I/O 20 = 500 1/0 pin
Input Timing Measurement 1 5V
R f L I .
e erence eve c - 30 F RL = 50n CL = 5pF 870n
Output Timing Measurement 1 5V L _ p
Reference Level .
VL = 1.5V (For tcos. tOEE: tcon,
Output Load Fig. 1 tooo, tOEW and tODw)
1997-06-18 5/9
TOSHIBA TC55V1664J-12,-15
TIMING DIAGRAMS
ADDRESS
OD (See Note 6)
tooo (See Note 6)
(See 6)
tBD (See Note 6)
Note 6
Dout VALID DATA OUT
tCOE (See Note 6)
INDETERMINATE INDETERMINATE
WRITE CYCLE 1 (tTOT CONTROLLED) (See Note 5)
ADDRESS X X
tas ’ twp - tWR
WE k \x i
CE "N 2%
UB, LB \ A"
tODW (See Note 6) tOEW (See Note 6)
Dout (See Note 3)§ (See Note 4)
INDETERMINATE INDETERMINATE
I tos toc
Din X VALID DATA IN X
1997-06-18 6/9
TOSHIBA
TC55V1664J-12,-15
WRITE CYCLE 2 LEE- CONTROLLED) (See Note 5)
ADDRESS
tas twp twa
S 'RN l
te, R ,
t tODW (See Note 6)
(See Note 6)
tCOE (See Note 6)
INDETERMINATE tos tDH
VALID DATA IN
WRITE CYCLE 3 (W, E CONTROLLED) (See Note 5)
ADDRESS
twp tum
_ tcw ’
‘t _ toow
(See NOSSEB) (See Note 6)
tBE (See Note 6) W A
INDETERMINATE tos tDH
VALID DATA IN
1997-06-18 7/9
TOSHIBA TC55V1664J-12,-15
Note: (1) Operating temperature (Ta) is guaranteed for transverse air flow exceeding 400
linear feet per minute.
(2)WF remains High for the Read Cycle.
(3)If tTE goes LOW coincident with or after IT/E goes LOW, the outputs will remain
at high impedance.
(4) If UE goes HIGH coincident with or before W goes HIGH, the outputs will remain
at high impedance.
(5) If UE- is HIGH during the write cycle, the outputs will remain at high impedance.
(6) The parameters specified below are measured using the load shown in Fig. 1
(A) tCOE, tOEE, tBE, tOEW ...... Output Enable Time
(B) tCOD, tOno, tBD, tODW ...... Output Disable Time
w, E rt
(A) (B)
r _V 0.2 v
0.2 v '
DOUT -, VALID DATA OUT -
0.2 V 1 - 0.2 V
INDETERMINATE ' INDETERMINATE4
1997-06-18 8/9
TOSHIBA TC55V1664J-12,-15
PACKAGE DIMENSIONS
Plastic SOJ (SOJ44-P-400-1.27)
Units in mm
'r""""'-"""""""""'"'"'-"''-':-
11 05i0 12
9.3TYP
I-Jr-JL-dl-JI-ICICI/lr-jr-jr-Ut-JCI-tut-ici-tut-gt-ii-J
29.0MAX
28.58i0.12
Weight: 1.64 g (typ)
1997-06-18 9/9
www.ic-phoenix.com
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