TC55V1001AFTI-10 ,131,072-WORD BY 8-BIT CMOS STATIC RAMapplications where high speed, low power and battery backup arerequired. The TC55V1001AFI/AFTI/ATRI ..
TC55V1001AFTI-10 ,131,072-WORD BY 8-BIT CMOS STATIC RAMTOSH I BA TC55V1001AFl/AFTl/ATRl/ASTl/ASRI-85,-10,-85L,-1OL131 ,072-WORD BY 8-BIT STATIC RAMThe TC5 ..
TC55V1001AFTI-85L ,131,072-word by 8 bit static RAM, access time 85nsapplications where high speed, low power and battery backup arerequired. The TC55V1001AFI/AFTI/ATRI ..
TC55V1001AFTI-85L ,131,072-word by 8 bit static RAM, access time 85nsTOSH I BA TC55V1001AFl/AFTl/ATRl/ASTl/ASRI-85,-10,-85L,-1OL131 ,072-WORD BY 8-BIT STATIC RAMThe TC5 ..
TC55V1001ASRI-10 ,131,072-WORD BY 8-BIT CMOS STATIC RAMTOSH I BA TC55V1001AFl/AFTl/ATRl/ASTl/ASRI-85,-10,-85L,-1OL131 ,072-WORD BY 8-BIT STATIC RAMThe TC5 ..
TC55V1001AST-85L ,131,072-WORD BY 8-BIT CMOS STATIC RAMTOSH I BA TC55V1001AF/AFT/ATR/AST/ASR-85,-10,-85L,-1OL131 ,072-WORD BY 8-BIT STATIC RAMThe TC55V100 ..
TC9314F-017 ,SINGLE CHIP DIGITAL TUNING SYSTEM FOR CD RADIO CASSETTE
TC9314F-026 ,SINGLE CHIP DIGITAL TUNING SYSTEM FOR CD RADIO CASSETTE
TC9314F-026 ,SINGLE CHIP DIGITAL TUNING SYSTEM FOR CD RADIO CASSETTE
TC9317F ,DTS MICROCONTROLLER (DTS-21)Features built-in 1/3-duty, 1/2-bias LCD drivers and a built-in 3V booster circuit for the display. ..
TC9317F ,DTS MICROCONTROLLER (DTS-21)Features independent frequency input pins (FMIN and AMIN) and two (DOI and D02) phasecomparison out ..
TC9318FB ,SINGLE CHIP DTS MICROCONTROLLER (DTS-21)Features built-in 1/3-duty, 1/2-bias LCD drivers and a built-in 3V booster circuit for the display. ..
TC55V1001AFI-10-TC55V1001AFI-10L-TC55V1001AFI-85-TC55V1001AFI-85L-TC55V1001AFTI-10-TC55V1001ASRI-10-TC55V1001ASTI-10-TC55V1001ASTI-85-TC55V1001ASTI-85L
131,072-WORD BY 8-BIT CMOS STATIC RAM
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
131 ,072-WORD BY 8-BIT STATIC RAM
DESCRIPTION
The TC55V1001AFI/AFTI/ATRI/ASTI/ASRI is a 1,048,576-bit static random access memory (SRAM)
organized as 131,072 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this
device operates from a single 2.7 to 3.6 V power supply. Advanced circuit technology provides both high speed
and low power at an operating current of 3 mA/MHz and a minimum cycle time of 85 ns. It is automatically
i!...l...1.t..ts..d in low-power mode at 0.5 PA standby current (L-Version at VDD-- 31r....,.._Tp= 25°C) when chip enable
(CEl) is asserted high or (CE2) is asserted low. There are three control inputs. CEI and CE2 are used to select
the device and for data retention control, and output enable (Ci) provides fast memory access. This device is
well suited to various microprocessor system applications where high speed, low power and battery backup are
required. The TC55V100lAFI/AFTI/ATRI/ASTI/ASRI is available in a plastic 32-pin small-outline package
(SOP) and normal and reverse pinout plastic 32-pin thin-small-outline package (TSOP).
FEATURES
0 Low-power dissipation 0 Access Times (maximum):
Operating: 10.8 mW/MHz (typical) TC55V1001AFI/AFTI/ATRI/ASTI/ASRI
0 Single power supply voltage of 2.7 to 3.6 V _ 85, - 85L - 10, - 10L
0 Power down features using CEI and CE2. .
0 Data retention supply voltage of 2 to 3.6 V gigs “:6 :an lggm
0 Direct TTL compatibility for all inputs and outputs ccess ime ns ns
0 Wide operating temperature range of -400 to 85°C - Access Time 85ns 100ns
0 Standby current (Ta = 25°C maximum) OE Access Time 45ns 50ns
TC55V1001AFl/AFTl/ATRl/ASTl/ASRI dt Packages:
-85, -10 -85L, -10L SOP32-P-525-1.27 (AFI) (Weight: 1.04 g typ)
3.6V 3PA os A TSOPI32-P-0820-0.50(AFTI) (Weight:0.34gtyp)
. . " TSOPI32-P-0820-0.50A(ATRI) (Weight:0.34gtyp)
3.0V 1 #A 0.5 pr/k TSOP I 32-P-0.50 (ASTI) (Weight: 0.24 g typ)
TSOP I 32-P-0.50A (ASRI) (Weight: 0.24 g typ)
PIN ASSIGNMENT (TOP VIEW)
O 32 PIN SOP o 32 PIN TSOP
NC 1: 1 V 32:1 V (Normalpinout) (Reverse pinout)
A16 1: 2 31 El A13
A14 1: 3 303 CE2
A12 I: 4 293 RM 16 1
A7 I: 5 283 A13
A6 1: 6 273 A8
A5 I: 7 263 A9
A4 1: 8 253 A_11
A3 |: 9 243 OE
A2 I: 10 233 A_10
A1 I: 11 223 CE1
A0 c 12 213 I/O8
I/OI I: 13 20: l/OT
1/02 I: 14 195 I/O6
1/03 I: 15 183 IIOS 17 32
GNDI: 16 173 l/OI
PIN NAMES
AOto A16 Address Inputs PinNo. 1 2 3 4 5 6 7 8 9 IO 11 12 13 14 15 16
RM Read/Write Control Pin Name A11 A9 N A13 R/W CE2 A15 VDD NC A16 A14 A12 A7 As As A4
OE Output Enable .
a CE2 Chip Enable Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
l/Ol to l/O8 Data Input/Output Pin Name A3 A2 A1 A0 I/O1 I/O2 I/03 GND I/O4 IIOS I/06 I/O? IIO8 C? A10 o"
VDD Power
GND Ground
NC No Connection
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1998-03-17 1/13
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
BLOCK DIAGRAM
A4 -o VDD
£2 a a a --o GND
A7 'tl :1: E MEMORY CELL
shul ga, SE fit ARRAY
A13 ft' " if?, 1024x128x8
/hlt 55 tg y? (1048576)
A16 tern ttctts cm
I/OI SENSEAMP
d COLUMNADDRESS
, f/ir, s
m, t COLUMNADDRESS
l/O8 8;
dll) COLUMNADDRESS
A0 A2 A9 All
A1 A3 A10
OPERATION MODE
MODE W CE2 E MN I/OI to l/O8 POWER
Read L H L H DOUT IDDO
Write L H X L DIN IDDO
Outputs Disabled L H H H High-Z IDDO
H x x x High-Z IDDS
Standby .
X L X X High-Z IDDS
Note: x = don't care. H = logic high. L = logiclow.
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 4.6 V
" Input Voltage - 0.3* to 4.6 V
VI/o Input/Output Voltage - 0.5 to VDD + 0.5 V
PD Power Dissipation 0.8 W
Tsolder Soldering Temperature (10s) 260 ''C
Tstrg. Storage Temperature - 55 to 150 T
Topr. Operating Temperature - 40 to 85 "C
* - 3.0 V when measured at a pulse width of 50 ns ** SOP
1998-03-17 2/13
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
DC RECOMMENDED OPERATING CONDITIONS (Ta = - 40° to 85°C)
2.7 to 3.6V
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 2.7 - 3.6
" Input High Voltage 2.2 - VDD + 0.3 V
" Input Low Voltage - 0.3* - 0.6
VDH Data Retention Supply Voltage 2.0 - 3.6
* - 3.0 V when measured at a pulse width of 50 ns
DC CHARACTERISTICS (Ta = - 40° to 85°C, VDD = 2.7 to 3.6 V)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
In. Input Leakage Current VIN = 0V to VDD - - i 1.0 psA
IOH Output High Current VOH = VDD - 0.5V -0.5 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
ILO Output Leakage Current %1= VY: C7, 0:500in " or - - i 1.0 prA
7 VDD = min - - 35
CE1 = VIL and CE2 = VlH and 3V i 10% Tcycle Irs - - 10
'0001 MN = ve, IOUT = 0 mA .
Other Input = VIHNIL VDD = Tcycle mm - - 40
3.3V:t0.3V IM; - - 12
Operating Current . mA
m = 0.2V and VDD = Tcycle mm - - 30
CE2--VDD-0.2V 3V1 10% 1/15 - - 5
'DDOZ MN = VDD - 0.2 v, IOUT = 0 mA VDD = min - - 35
Other Inputs = VDD - 0.2 wo.2v 3.3V i 0.3V Tcycle 1,15 - -
bios, E = VlH or CE2 = I/w. - - 2 mA
o -85, -10 - 1
VOD = Ta = 25 C -85L, -10L - 0.5 0.7
3V , 10% -85, -10 - - 40
Ta-- -4ty'to850C -85L,-10L - - 25
o -85, -10 - 2 3
7 VDD = Ta = 25 c -85L, -10L - 0.7 0.9
IDD$2 Standby Current CE1=VDD - 0.2V 3.3v:o.3v -85,-10 - - 45
(Note) or CE2 = 0.2 V Ta = - 40° to 85°C -85L, -10L - - 30 pr/k
VDD-- 2.0 to 3.6V -85, -10 - - 1
Ta = 25°C -85L, -10L - - 0.5
VDD = 3V o o -85, -10 - - 3
Ta=-40 to40C -85L,-10L - - 2
-85, -10 - - 35
Ta-- -40°to85°C -85L,-1OL - - 20
Note: In standby mode with m 2 VDD - 0.2 V, these limits are assured for the condition CE2 i VDD - 0.2 V or CE2 s 0.2 V.
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
G: Input Capacitance " = GND 10 F
CouT Output Capacitance VOUT = GND 10 p
Note: This parameter is periodically sampled and is not 100% tested.
1998-03-17 3/13
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = - 40° to 85°C, VDD = 2.7 to 3.6 V)
READ CYCLE
TC55V1001AFl/AFTl/ATRl/ASTl/ASRI
SYMBOL PARAMETER -85, -85L -10, -10L UNIT
MIN MAX MIN MAX
tRC Read Cycle Time 85 - 100 -
tACC Address Access Time - 85 - 100
tco1 Chip Enable (m) Access Time - 85 - 100
tco2 Chip Enable (CE2) Access Time - 85 - 100
tOE Output Enable Access Time - 45 - 50
tcos Chip Enable Low to Output Active 5 - 5 - ns
tOEE Output Enable Low to Output Active 0 - 0 -
too Chip Enable High to Output High-Z - 35 - 40
tooo Output Enable High to Output High-Z - 35 - 40
tOH Output Data Hold Time 10 - 10 -
WRITE CYCLE
TC55V1tK1AFl/AFTl/ATRl/ASTl/ASRI
SYMBOL PARAMETER -85, -85L -10, -10L UNIT
MIN MAX MIN MAX
twc Write Cycle Time 85 - 100 -
twp Write Pulse Width 60 - 60 -
tcw Chip Enable to End of Write 75 - 80 -
tAs Address Setup Time 0 - 0 -
tWR Write Recovery Time 0 - 0 - ns
toow R/W Low to Output High-Z - 35 - 40
tOEw R/W High to Output Active 0 - 0 -
tDS Data Setup Time 35 - 40 -
tDH Data Hold Time 0 - 0 -
AC TEST CONDITIONS
Output load: 100 pF + one TTL gate
Input pulse level: 0.4 V, 2.4 V
Timing measurements: 1.5 V
Reference level: 1.5 V
tR, tF: 5 ns
1998-03-17 4/13
TOSHIBA
TIMING DIAGRAMS
TC55V1001AFI/AFTI/ATRI/ASTI/ASRI-85,-10,-85L,-10L
READCYcI-E(SeeNote1)
ADDRESS X X
_ tacc t0H
CE2 // tcos "N. "K,
"'% tco1
tOE too
E 'N, //
toss tooo
DOUT t VALID DATA OUT
INDETERMINATE
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESS
tum tWR
/ tcw W
fig w 7
A tODW tOEW
(See Note 2) (See Note 3)
tos tDH
/(See Note 5) VALID DATA IN (See Note 5)
/h,v,"j2',Di'ir'',',i',',, /
1998-03-17 5/13
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
WRITE CYCLE 2 LLCEI CONTROLLED) (See Note 4)
ADDRESS X
twe tum
CE2 , tcw 'W"
tcos t00w
tos tDH
De: (See Note 5) VALID DATA IN (See Note 5)
WRITE CYCLE 3 (CE2 CONTROLLED) (See N ote 4)
ADDRESS
tos tDH
DIN (See Note 5) VALID DATA IN (See Note 5)
1998-03-17 6/13
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
Note: (1) R/W remains HIGH for the read cycle.
(2) If CEI goes LOW (or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs
will remain at high impedance.
(3) If CEI goes HIGH (or CE2 goes LOW) coincident with or before R/W goes HIGH, the
outputs will remain at high impedance.
(4) If ttE is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse
polarity must not be applied.
DATA RETENTION CHARACTERISTICS (Ta = - 40° to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 3.6 V
-85, -10 - -
Ta = - 40° to 40°C
V 3 0V -85L, -10L - -
I s db c DH - . T 40ot 85°C -85,-10 - - 35 A
tan rrent a = - o
DDS2 y u -85L,-10L - - 20 /2
-85, -10 - - 45
VDH = 3.6V Ta = - 40° to 85°C
-85L, -10L - - 30
ttrm Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
CEI CONTROLLED DATA RETENTION MODE (See Note 1)
VDD l DATA RETENTION MODE
2.7 V - - - - - ----_
(See Note 2) (See Note 2)
Ihr, --- l /
- / VDD - 0.2V
CE1 tCDR tR
1998-03-17 7/13
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
CE2 CONTROLLED DATA RETENTION MODE (See Note 3)
VDD CC") DATA RETENTION MODE hi,
2.7 v ---------'..------------------------i.---------
" tCDR tR
V - - - -
IL k , 0.2 v V
Note: (1) In (El controlled data retention mode, minimum standby current mode is entered when
CE2 s 0.2 V or CE2 2 VDD - 0.2 V.
(2) When CEI is operating at the VIH level (2.2 V), the operating current is given by IDDSl
during the transition of VDD from 3.6 to 2.4 V.
(3) In CE2 controlled data retention mode, minimum standby current mode is entered when
CE2 s 0.2 V.
1998-03-17 8/13
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
PACKAGE DIMENSIONS (SOP32-P-525-1.27)
Units in mm
'ii2uscsscrvc1s7----,
10 7+0 2
14.13i0.3
(525mil)
_i1ljliierili)ljrrirlrj)
0.775wp " o.3:o.1
21.1MAX
.4 20.6iO.2 pl,
IIII L, .
2 8MAX
0,15 :%.05
Weight: 1.04 g (typ)
1998-03-17 9/13
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50)
Units in mm
"E 32 CM.
n: k x
El cu.
TT-T , co
ii-g g e;
18.4h0.2 E 1.0:0.1 0.1 i0.05
A 20.0:02 ci 1.2MAX
Weight: 0.34 g (typ)
1998-03-1 7 10/13
TOSHIBA TC55V1001AFl/AFTl/ATRI/ASTI/ASRI-85,-10,-85L,-10L
PACKAGE DIMENSIONS (TSOP I 32-P-0820-0.50A)
Units in mm
flfififififififififififlfiflfi
0.2i0.1
8.2MAX
7 9i0 1
18.4i0.2
20.0i0.2
0.1i0.05
0.2TYP
0.15 ’11)).05
0.5:h0.1
Weight: 0.34 g (typ)
1998-03-17 11/13
TOSHIBA
PACKAGE DIMENSIONS (TSOP I 32-P-0.50)
TC55V1001AFI/AFTI/ATRI/ASTI/ASRI-85,-10,-85L,-10L
Units in mm
1;? T253323 G 1
C": TIEI 6
III]: Elm]; Y,
cu: ===J. 7.
ar an A if: o C;
CI12 31') Ff g c,
E;- Ee?, f ed 00 ;
DI. K I
Lac :DD
ms: :11: -
EEC ZED
16:1:L a 17-0-
1 1181-01 E 1 0+01 ii,0-1--"05
co' 1.2MAX
1 13.4i02 ' x "
Weight: 0.24 g (typ)
0 ”5.3.055
ho--1oo
1998-03-17 12/13
TOSHIBA
TC55V1001AFI/AFTI/ATRI/ASTI/ASRI-85,-10,-85L,-10L
PACKAGE DIMENSIONS (TSOP I 32-P-0.50A)
3213! 2:131 g'
cad ' +1
cu: gl
(:11: - o‘
:11: :33 V
CH: CCC1TCI-.---'-'=
cm: 333 A
1:11: :1:
EU: :13
CH: ='ICl
:1]: -rr-t
[:1]: CITED
CI Cary I')
El]: :[13
El]: :ILI
17EECL 11:16...
1181-01 _ t
13.4t0.2
Weight: 0.24 g (typ)
8.4MAX
Units in mm
0.1i0.05
1 .2MAX
1998-03-1 7 13/13
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