TC554001FTL-85 ,524,288 WORDS x 8BIT STATIC RAMfeatures using CE C_;c:ss FII.0 Data retention supply voltage of 2.0 to 5.5 V CIE/SCC-rims: CCeSS ' ..
TC554001FTL-85V ,524, 288 words x 8 bit static RAM, access time 85nsTOSHIBA TC554001FL/FTL-7OV,-85V,-1OV524,288 WORDS M 8 BIT STATIC RAMThe TC554001FL/FTL is a 4,194,3 ..
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TC554001FL-70-TC554001FL70L-TC554001FL-70L-TC554001FL-85-TC554001FTL-70L-TC554001FTL-85
524,288 WORDS x 8BIT STATIC RAM
TOSHIBA TC554001FL/FTL-70,-85,-10
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288 WORDS M 8 BIT STATIC RAM
DESCRIPTION
The TC554001FL/FTL is a 4,194,304-bit static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates
from a single 5Vi' 10% power supply. Advanced circuit technology provides both high speed and low
power at an operating current of 10mA/MHz(typ) and minimum cycle time of 70 riIt is automatically
placed in low-power mode at (oi) PA standby current (max) when chip enable (CE) is asserted high.
There atg_two control inputs. CE is used to select the device and for data retention control, and output
enable (OE) provides fast memory access. This device is well suited to various microprocessor system
applications where hi h speed, low power and battery backup are required.The TC554001FL/FTL is
available in a stan ard plastic 32-pin small-outline paclrige(SOP) and 32-pin thin-small-outline
package(TSOP).
FEATURES
0 Low-power dissipation tt Access Time (maximum)
Operating: 55 mW/MHz (typical) TC554001FL/FTL
0 Standby current of 100 PA (maximum) -70 -85 -10
0 Single power supply voltage) 5 Vi 10 % Access Time 70 ns 85 m 100 ns
0 Power down features using CE - . 70 ns 85 m 100 ns
0 Data retention supply voltage of 2.0 to 5.5 V C_EAccess “me
o Direct TTL compatibility for all inputs and OE Access Time Mins 45ns 50 ns
outputs 0 Package:
SOP32-P-525-1.27 (FL) (Weight: 1.14 g typ)
TSOPII 32-P-400-1.27 (FTL) (Weight: 0.51 g typ)
PIN ASSIGNMENT (TOP VIEW) BLOCK DIAGRAM
o32 PIN FUFTL CE
A18 l: 1 V 32] VDD . V
A16E 2 31] A15 A28 V, V, v, --o DD
AME 3 33% 91/; jh112 :1 :5 'dti MEMORY CELL -o
A12 4 A13 file g; 88 ARRAY
A7 I: 5 28Cl A13 A14 (LL < -
A15 3 o Ul x 512 x 8
A6 I: 6 27] A8 A16 sm 3 tl E n (4194304)
A5 I: 7 26] A9 A17 3 g f),
A4 I: 8 253 w A18
A3 I: 9 24] OE l/OI
A2 I: 10 23:I 1410 SENSE AMP
A1 I: 11 22] CE 8 COLUMN ADDRESS
A0 I: 12 21] l/O8 .51:
won: 13 20] 1/07 to 3% Jo:
IIOZ l: 14 19 Cl I/os U 8: COLUMN ADDRESS
1/03I: 15 18] l/O5 l/O8 d;
GND[E 16 173 um 3 COLUMN ADDRESS
PIN NAMES
A0 to A18 Address Inputs AOAIA2A3A4A5A6A7A8
R/W Read/Write Control
E Output Enable
E Chip Enable tie
l/OI to l/O8 Data Input/Output R/W
VDD Power (+ 5V)
GND Ground CE
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-12 1/9
TOSHIBA TC554001FL/FTL-70,-85,-10
OPERATION MODE
OPERATION MODE E E R/W I/OI to I/O8 POWER
Read L L H DOUT IDDO
Write L x L DlN IDDO
Output Disabled L H H High-Z IDDO
Standby H x x High-Z IDDS
Note: M =don't care. H=logic high. L=logic low.
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 7.0 V
" Input Voltage - 0.3* to 7.0 V
Vl/O Input and Output Voltage - 0.5 to VDD + 0.5 V
Po Power Dissipation 0.6 W
Tsolder Soldering Temperature (10s) 260 °C
Tstrg. Storage Temperature - 55 to 150 "C
Topr. Operating Temperature 0 to 70 "C
* - 3.0V when measured at a pulse width of 50 ns
1997-06-12 2/9
TOSHIBA
TC554001FL/FTL-70,-85,-10
DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 4.5 5.0 5.5
" Input High Voltage 2.2 - VDD + 0.3 V
" Input Low Voltage - 0.3* - 0.8 V
VDH Data Retention Supply Voltage 2.0 - 5.5 V
* - 3.0V when measured at a pulse width of 50 ns
DC CHARACTERISTICS (Ta = ty' to 70°C, VDD = 5V i 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
u. Input Leakage Current " = 0V to I/oo - - i 1.0 [A
IOH Output High Current VOH = 2.4V - 1.0 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
C-E = V = V ty-E = V
lLo Output Leakage Current C IH or W IL or O IH - - i 1.0 pr/k
VOUT = 0V to VDD
E = VIL and MN = " min - - 80
IDDO1 IOUT = 0 mA Tcycle mA
Other Inputs = V|H/V||_ 1 pd; - 15 -
Operating Current -
CE = 0.2V and W = VDD-O-ZV min - - 70
IDDOZ IOUT = 0 mA Tcycle mA
Other Inputs = l/DD-od V/0.2V 1 pd; - 10 -
|DDS1 E = " - - 3 mA
Standby Current E = VDD_o-2V
IDDSZ o o - - 100 #A
VDD = 2.0 to 5.5V, Ta = 0 to 70 C
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
CIN Input Capacitance VIN = GND 10 pF
Cour Output Capacitance VOUT = GND 10 pF
Note: This parameter is periodically sampled and is not 100% tested.
1997-06-12 3/9
TOSHIBA TC554001FL/FTL-70,-85,-10
AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0° to 70°C, VDD = 5V i 10%)
READ CYCLE
TC554001FL/FTL
SYMBOL PARAMETER -70 -85 -10 UNIT
MIN MAX MIN MAX MIN MAX
tRC Read Cycle Time 70 - 85 - 100 -
tACC Address Access Time - 70 - 85 - 100
tco Chip Enable Access Time - 70 - 85 - 100
tog Output Enable Access Time - 35 - 45 - 50
tcos Chip Enable Low to Output Active 10 - 10 - 10 - ns
toga Output Enable Low to Output Active 5 - 5 - 5 -
too Chip Enable High to Output High-Z - 25 - 30 - 35
tODo Output Enable High to Output High-Z - 25 - 30 - 35
tom Output Data Hold Time 10 - 10 - 10 -
WRITE CYCLE
TC554001FL/FTL
SYMBOL PARAMETER -70 -85 -10 UNIT
MIN MAX MIN MAX MIN MAX
twc Write Cycle Time 70 - 85 - 100 -
twp Write Pulse Width 50 - 55 - 60 -
tcw Chip Enable to End of Write 60 - 70 - 80 -
tas Address Setup Time 0 - O - 0 -
tWR Write Recovery Time 0 - 0 - 0 - ns
toow MN Low to Output High-Z - 25 - 30 - 35
toew R/W Hige to Output Active 5 - 5 - 5 -
tos Data SetupTime 30 - 35 - 4O -
tDH Data Hold Time 0 - 0 - 0 -
AC TEST CONDITIONS
Output Load: 30 pF + one TTL gate (-70)
100 pF + one TTL gate (-85, -10)
Input Pulse Level: 0.6V, 2.4V
Timing Measurements: 1.5 V
Reference Level: 1.5 V
tr, ty: 5 ns
1997-06-12 4/9
TOSHIBA
TIMING WAVEFORMS
READ CYCLE (See Note 1)
ADDRESSES
TC554001FL/FTL-70,-85,-10
tacc tOH
tOEE tODO
OUTPUT DATA VALID
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESSES
tAS twp tum
f" Ah /
toow toEw
(See Note 2) (See Note 3)
tos tDH
(See Note 5)
DATA IN STABLE
(See Note 5)
1997-06-12 5/9
TOSHIBA TC554001FL/FTL-70,-85,-10
WRITE CYCLE 2 (CE CONTROLLED) (See Note 4)
ADDRESSES X
' ' twp tWR
R/W % /
E YF'" tii)!, /
tCOE _ toow
DOUT ,
tos tDH
D.N (See Note 5) DATA IN STABLE (See Note 5)
(1) R/W remains High for Read Cycle.
(2) If TftT goes coincident with or after R/W goes LOW, the output will remain at high impedance.
(3) If CE goes HIGH coincident with or before R/W goes HIGH, the output will remain at high
impedance.
(4) IF C-E is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse polarity
must not be applied.
1997-06-12 6/9
TOSHIBA TC554001FL/FTL-70,-85,-10
DATA RETENTION CHARACTERISTICS (Ta = 0° to 70°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 5.5 V
VDH = 3.0V - - 50
IDDsz Standby Current pA
VDH = 5.5V - - 100
thR Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
E Controlled Data Retention Mode
VDD l DATA RETENTION MODE
4.5 v --.-.-.-.-. - - - - -.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.-.t-.-.-.-.-.-.-.-.-. -
(See Note) (See Note)
" - l /
- VDD-O.2 v
CE tCDR - tR
Note: When CE is operating at the VIH level (2.2V), the standby current is given by IDDSl
during the transition of VDD from 4.5 to 2.4V.
1997-06-12 7/9
TOSHIBA TC554001FL/FTL-70,-85,-10
PACKAGE DIMENSIONS (SOP32-P-525-1.27)
iii2suucsuuvrvc1s7-----a;
10 7i0 2
14.13i0.3
ii1ljlj)ilj)lirielilili11ri,------,
O .775TYP P
h 20.6i0.2 u
2.8MAX
Weight: 1.14 g (typ)
Unit in mm
(525mil)
1997-06-12 8/9
TOSHIBA TC554001FL/FTL-70,-85,-10
PACKAGE DIMENSIONS (TSOPII 32-P-400-1.27)
Unit in mm
'2RRFlfqRFllqRlqFlFlFlplplpl
1016i01
bfEtihbjbdEEldtildld HHEI
QSSTYP
21 .35MAX
20.95i0.1
1 01—0 1
1.2MAX
0.15 ,0105
Weight: 0.51 g (typ)
1997-06-12 9/9
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