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TC554001FI-85L |TC554001FI85LTOSHIBAN/a5530avai524, 288 words x 8 bit static RAM, access time 85ns


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TC554001FI-85L
524, 288 words x 8 bit static RAM, access time 100ns
TOSHIBA TC554001FI/FTl-85L,-10L
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288 WORDS M 8 BIT STATIC RAM
DESCRIPTION
The TC554001FI/FTI is a 4,194,304-bit static random access memory (SRAM) organized as 524,288
words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates
from a single 5Vi' 10% power supply. Advanced circuit technology provides both high speed and low
power at an operating current of 10mA/MHz(typ) and minimum cycle time of 85 r1_s.It is automatically
placed in low-power mode at _140 PA standby current (max) when chip enable (CE) is asserted high.
There are_two control inputs. CE is used to select the device and for data retention control, and output
enable (OE) provides fast memory access. This device is well suited to various micro rocessor system
applications where high speed, low power and battery backup are required.And, wit a guaranteed
operating range of -40 to 85°C, the TC554001FI/FTI can be used in environments exhibiting extreme
temperature conditions. The Tc554001FI/FTI is available in a standard plastic 32-pin small-outline
package(SOP) and 32-pin thin-small-outline package(TSOP).
FEATURES
0 Lovgpower dissipation 1 0 Access Time (maximum)
perating: 55 mW/MHz (typica ) T 1 IFl FTI
0 Standby current of 8 PA (maximum) at -85L C55 00 / -10L
Ta = 25°C .
0 Single power supply voltage) 5V-k 10 % Iccess Time 85 ns 100 ns
0 Power down features using CE CE Access Time 85 ns 100 ns
0 Data retention supply voltage of 2.0 to 5.5V E Access Time 45 ns 50 ns
I Directly 'ITL compatibility for all inputs and
outputs q Paglyie2: P 525 1 27 (F1) (W . ht 1 14 t )
o . . - o - - - . elg : . g yp
g??? operating temperature range of 40 to TSOPlI32-P-400-1.27 (FTI) (Weight: 0.51 g typ)
PIN ASSIGNMENT (TOP VIEW) BLOCK DIAGRAM
o32 PIN FI/FTI CE
A18 E 1 V 32 Cl VOD 2 V
A161: 2 31 Cl A15 AA13 w m w H (3:1?)
A14E 3 30Cl A17 All 'd,' Sa: $1 -o
A121: 4 29] R/W A12 gr, :3 gg MEMORY CELL
A7 I: 5 2821 A13 £12 fit fil' 28 ARRAY
AGES 27] A8 A15 " ''il " 1024x512x8
A5 I: 7 26Cl A9 fl' o On: 0 (4194304)
A4 1: a 25:1 Ag A18 .1 x tE
A3 I: 9 24:] OE l/OI
A2 i: 10 23] A10 SENSE AMP
A1 1: 11 22Cl E s' COLUMN ADDRESS
A0 I: 12 21 Cl l/O8 t Eff x
1/01 E 13 20] 1/07 o a C)
1/02 I: 14 19:1 l/O6 o8 gg COLUMN ADDRESS
I/O3 I: 15 18 Cl l/O5 IIO8 Cl;
GNDI: 16 17] 1/04 tl COLUMN ADDRESS
PIN NAMES
A0 to A18 Address Inputs AOA1A2A3A4A5A6A7A8
MN Read/Write Control
W Output Enable
E Chip Enable a
l/OI to l/O8 Data Input/Output R/W
VDD Power (+ 5V)
GND Ground E CE
961001EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operatin ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and con itions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-12 1/9
TOSHIBA TC554001Fl/FTI-85L,-10L
OPERATION MODE
OPERATION MODE E E R/W I/OI to I/O8 POWER
Read L L H DOUT IDDO
Write L x L DlN IDDO
Output Disabled L H H High-Z IDDO
Standby H x x High-Z IDDS
Note: M = don't care. H=logic high. L=logic low.
ABSOLUTE MAXIMUM RATINGS
SYMBOL RATING VALUE UNIT
VDD Power Supply Voltage - 0.3 to 7.0 V
" Input Voltage - 0.3* to 7.0 V
Vl/O Input and Output Voltage - 0.5 to VDD + 0.5 V
Po Power Dissipation 0.6 W
Tsolder Soldering Temperature (10s) 260 °C
Tstrg. Storage Temperature - 55 to 150 "C
Topr. Operating Temperature - 40 to 85 "C
* - 3.0V when measured at a pulse width of 50 ns
1997-06-12 2/9
TOSHIBA TC554001Fl/FTI-85L,-10L
DC RECOMMENDED OPERATING CONDITIONS (Ta = - 40° to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDD Power Supply Voltage 4.5 5.0 5.5
" Input High Voltage 2.4 - VDD + 0.3 V
" Input Low Voltage - 0.3* - 0.6 V
VDH Data Retention Supply Voltage 2.0 - 5.5 V
* - 3.0V when measured at a pulse width of 50 ns
DC CHARACTERISTICS (Ta = - 40° to 85°C, VDD = 5V i 10%)
SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT
IIL Input Leakage Current VIN = 0V to VDD - - i 1.0 PA
IOH Output High Current VOH = 2.4V - 1.0 - - mA
IOL Output Low Current VOL = 0.4V 2.1 - - mA
E = V o W = V O E = V
ILO Output Leakage Current IH r IL r IH - - i 1.0 PA
VOUT = 0V to VDD
E = VIL and MN = " min - - 80
|DDO1 IOUT = 0 mA Tcycle mA
Other Inputs = VlHNIL 1 Mi - 15 -
Operating Current -
CE = 0.2V and W = VDD-O." min - - 70
IDDOZ IOUT = 0 mA Tcycle mA
Other Inputs = Vorr-0.2 V/0.2V 1,us - 10 -
IDDS‘I E = VIH - - 3 mA
Standby Current E = Voo- 0.2 V Ta = 25°C - 4 8
IDDSZ PA
VDD = 2.0 to 5.5V Ta = -4ty' to 85°C - - 140
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL PARAMETER TEST CONDITION MAX UNIT
Cm Input Capacitance " = GND 10 pF
COUT Output Capacitance VOUT = GND 10 pF
Note: This parameter is periodically sampled and is not 100% tested.
1997-06-12 3/9
TOSHIBA TC554001Fl/FTI-85L,-10L
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = - 40° to 85°C, VDD = 5V i 10%)
READ CYCLE
TC554001Fl/FTl
SYMBOL PARAMETER -85L -10L UNIT
MIN MAX MIN MAX
tRc Read Cycle Time 85 - 100 -
tAcc Address Access Time - 85 - 100
tco Chip Enable Access Time - 85 - 100
tOE Output Enable Access Time - 45 - 50
tcoE Chip Enable Low to Outputin Active 5 - 5 - ns
tOEE Output Enable Low to Output Active 0 - 0 -
too Chip Enable Hige to Output High-Z - 35 - 40
tODO Output Enable Hige to Output High-Z - 35 - 40
tOH Output Data Hold Time 10 - 10 -
WRITE CYCLE
TC554001Fl/FTl
SYMBOL PARAMETER -85L -10L UNIT
MIN MAX MIN MAX
twc Write Cycle Time 85 - 100 -
twp Write Pulse Width 55 - 60 -
tcw Chip Enable to End of Write 70 - 80 -
tAs Address Setup Time - -
tWR Write Recovery Time - - ns
toow R/W Low to Output High-Z - 35 - 40
tOEW R/W High to Output Active 0 - 0 -
tos Data SetupTime 35 - 40 -
tDH Data Hold Time 0 - 0 -
AC TEST CONDITIONS
Output Load: 100 pF + one TTL gate
Input Pulse Level: 0.4 V, 2.6V
Timing Measurements: 1.5 V
Reference Level: 1.5 V
tr, ty: 5 ns
1997-06-12 4/9
TOSHIBA
TIMING WAVEFORMS
ADDRESSES
TC554001 Fl/FTI-85L,-10L
tacc tOH
tOEE tODO
OUTPUT DATA VALID
WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4)
ADDRESSES
tAS twp tum
f" Ah /
toow toEw
(See Note 2) (See Note 3)
tos tDH
(See Note 5)
DATA IN STABLE
(See Note 5)
1997-06-12 5/9
TOSHIBA TC554001Fl/FTI-85L,-10L
WRITE CYCLE 2 Lff2Tif CONTROLLED) (See Note 4)
ADDRESSES
tDs tDH
DIN See Note 5 DATA IN STABLE (See Note 5
(1) WW remains High for Read Cycle.
(2) If CE goes coincident with or after R/W goes LOW, the output will remain at high impedance.
(3) If "tTri)"" goes HIGH coincident with or before R/W goes HIGH, the output will remain at high
impedance.
(4) IF CT is HIGH during the write cycle, the outputs will remain at high impedance.
(5) Because I/O signals may be in the output state at this time, input signals of reverse polarity
must not be applied.
1997-06-12 6/9
TOSHIBA
TC554001 Fl/FTI-85L,-10L
DATA RETENTION CHARACTERISTICS (Ta = - 40° to 85°C)
SYMBOL PARAMETER MIN TYP MAX UNIT
VDH Data Retention Supply Voltage 2.0 - 5.5 V
vDH = 3.0V - - 70 *
bose Standby Current pA
VDH = 5.5V - - 140
tCDR Chip Deselect to Data Retention Mode Time 0 - - nS
tR Recovery Time 5 - - mS
CE Controlled Data Retention Mode
*) tip/k (max) Ta = - 4ty' to 40''C
VDD DATA RETENTION MODE
4.5 v ------ - - - - N B------------------.-------- -
(See Note) (See Note)
" - l /
- vDD-o.2 v
CE tCDR tR
Note: When CE is operating at the Vm level (2.4V), the standby current is given by IDDSl
during the transition of VDD from 4.5 to 2.6V.
1997-06-12 7/9
TOSHIBA
PACKAGE DIMENSIONS (SOP32-P-525-1.27)
iii2suucsuuvrvc1s7-----a;
10 7i0 2
14.13i0.3
ii1ljlj)ilj)lirielilili11ri,------,
O .775TYP P
h 20.6ur0.2 u
2.8MAX
Weight: 1.14 g (typ)
TC554001Fl/FTI-85L,-10L
Unit in mm
(525mil)
1997-06-12 8/9
TOSHIBA TC554001Fl/FTI-85L,-10L
PACKAGE DIMENSIONS (TSOPII 32-P-400-1.27)
Unit in mm
'2RRFlfqRFllqRlqFlFlFlplplpl
1016i01
bfEtihbjbdEEldtildld HHEI
QSSTYP
21 .35MAX
20.95i0.1
1 01—0 1
1.2MAX
Weight: 0.51 g (typ)
1997-06-12 9/9

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