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TC554001AF-70V-TC554001AFT-10V-TC554001AFT-70V-TC554001AFT-85V
524,288-WORD BY 8-BIT STATIC RAM
TC554001AF/AFT/ATR-70V,-85V,-10V TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
524,288-WORD BY 8-BIT STATIC RAM
DESCRIPTION The TC554001AF/AFT/ATR is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words
by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.7 to
5.5 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of
10 mA/MHz (typ) and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 2 µA standby
current (typ) when chip enable (CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to
various microprocessor system applications where high speed, low power and battery backup are required. The
TC554001AF/AFT/ATR is available in a standard plastic 32-pin small-outline package (SOP) and normal and
reverse pinout plastic 32-pin thin-small-outline package (TSOP).
FEATURES Low-power dissipation
Operating: 55 mW/MHz (typical) Standby current of 5 µA (maximum) at Ta = 25°C Single power supply voltage of 2.7 to 5.5 V Power down features using CE. Data retention supply voltage of 2.0 to 5.5 V Direct TTL compatibility for all inputs and outputs
PIN ASSIGNMENT (TOP VIEW) PIN NAMES 32 PIN SOP & TSOP 32 PIN TSOP
VDD
A15
A17
R/W
A13
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
A18
A16
A14
A12
I/O1
I/O2
I/O3
GND
(AF/AFT)
VDD
A15
A17
R/W
A13
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
(ATR) Access Times (maximum): Package:
SOP32-P-525-1.27 (AF) (Weight: 1.14 g typ)
TSOP II32-P-400-1.27 (AFT) (Weight: 0.53 g typ)
TSOP II32-P-400-1.27A (ATR) (Weight: 0.53 g typ)
