TC51832PL-85 ,85ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAML---.
082
_,__,J
TOSHIBA tL0GTC/hEh0RY) LIBE D " “1037343 00220]: l] -T
32,768 WORD x 8 B ..
TC51832SPL-10 ,100ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAMFEATURES
. Organization: 256K bit(32,768 word x 8 bit)
. Fast Access Time and Low Power Dissipa ..
TC51832SPL-12 ,120ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAMABSOLUTE MAXIMUM RATINGS
VOUT Output Voltage
Power Supply Voltag;
TOPR Operating Temperature
..
TC51832SPL-85 ,85ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAMFEATURES
. Organization: 256K bit(32,768 word x 8 bit)
. Fast Access Time and Low Power Dissipa ..
TC51WHM516AXBN70 ,2,097,152-WORD BY 16-BIT CMOS PSEUDO STATIC RAMBLOCK DIAGRAM CEA9 A10 V DDA11 GNDA12 A13MEMORY CELL ARRAY A14A154,096 × 512 × 16 A16(33,554,432) A ..
TC528128BJ-10 ,100ns; V(cc): -1 to +7V; V(in/out); -1.0 to +7.0V; 1W; 50mA; silicon gate CMOS 131.072 words x 8 Bits multiport DRAMFEATURES KEY PARAMETERS
TC528128B
. Single power supply of 5Vi10% with a built-in
ITEM
VB ..
TC7WU04FK ,3 INVERTERTC7WUO4F/FU/FKTC7WUO4F, TC7WU04FU, TC7WUO4FKThe TC7WUO4 is a high speed C2MOS INVERTER I—ITC7WUO4F£ ..
TC7WU04FK ,3 INVERTERELECTRICAL CHARACTERISTICS (CL = 15pF, VCC = 5V, Ta = 25°C)CHARACTERISTIC SYMBOL TEST CONDITION Ta ..
TC7WU04FU ,3 INVERTERTC7WUO4F/FU/FKTC7WUO4F, TC7WU04FU, TC7WUO4FKThe TC7WUO4 is a high speed C2MOS INVERTER I—ITC7WUO4F£ ..
TC7WZ00FK ,2 Input Nand GateFeatures TC7WZ00FU High output drive: ±24 mA (min) @V = 3 V CC Super high speed operation: t ..
TC7WZ00FU ,2 Input Nand GateLogic Diagram A B Y IN AL L H & OUT Y IN BL H H H L H H H L Recommended Operating Conditions Chara ..
TC7WZ02FK ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta = 25°C) Pin Assignment (top view) Characteristics Symbol Rating Unit S ..
TC51832F-12-TC51832FL-10-TC51832FL-12-TC51832PL-10-TC51832PL-12-TC51832PL-85-TC51832SPL-10-TC51832SPL-12-TC51832SPL-85
100ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAM
TOSHIBA (LOGIC/NENORY)
32,768 NORD x 8 BIT CMOS PSEUDO STATIC RAN
:F-Ezzesq
DESCR IPT ION
The T051832 Family is a 256K bit high-speed CHOS Pseudo-Static RAN organized as 32,768
words by 8 bits, The Tc51832 Family utilizes one transistor dynamic memory cell array with
I, CMOS peripheral circuitry to achieve large capacity, h_igh speed accesses, and low power
L requirements, using a single 5V power supply. The 0E/RFSH input allows two types of
' refresh operations: Auto Refresh and Self Refresh. The T051832 Family has a static RAN-
like read/urite functionality, which allows easy interfacing to a microprocessor. The
T651832 Family is pin-compatable with the 256K bit static RAM. The TCS1832P is offered in
a standard 28 pin 0.6 inch and 0.3 inch width plastic DIP. The TC51832F is offered in a
standard 28 pin 0.450 inch width small out-line plastic flat package.
FEATURES
i . Organization: 256K bit(32,768 wordx 8 bit) .
. Fast Access Time and Low Power Dissipation
Self refresh uses an internal timer.
All. Inputs and outputs.' TTL compatible
i TC51832P Family . 256 refresh cycle/ans
r -85 -10 -12 . Pin Compatible: 256K SRAN T055257
tCEA CE Access Crime 85ns 100ns 120ns . Logic Compatible: SRAM R/w Pin
tOEA Of A Ti 35ns 40ns 50ns . 28 pin Standard Plastic PKG
CCeSS me -- P/PL t 600 mil DIP
tRc Cycle_ Time 135ns 160ns 190ns SP/SPL: 300 mil DIP
PD "-TiiGFiii:TrTiicr. Max. 303mN 248mll 220mH Thi, t 450 mil SOP
Self Refresh Current lmA/IOOuA (-L)
. Single Power Supply: SVHOZ
. Auto refresh uses an internal counter.
PIN CONNECTION
t (TOP vmw)
r M " 1 283%!) [BLOCY EEriEEil
11le 2 ll 311/111 L
M 3 A13 ,
tl' ft s)',ti'i,f,'u), ho GND
5 I A9
A4 £6 2311111 l l 7? cowm
) e, fl s'ii,'ffl,"',i')P'iiiT nmonan 5.3
A19 7 ' , v
AI , ' - n 55 Si2lt'sF, AMP a
I/Agllg l, fggiégg Ald M E>c 3031331127) - vo am: 8 _:li1,ii
11 18 I .
5°25 lf 'Jltfg . tl-tma ll 25 s
03 I 5 RC“ ADDRESS at "
GNDE 14 15 a [/04 Ar-ho BUFFER (8) l I) .'s1 l MEMORY F
PIN NAMES ii' 266 ARRAY S 3
A0 N A14 Address Inputs ugmgsn 8 1;) t t, 256x128x8 'iti
R/w Read/write Control COUNTER (8) ttt 8 o M
I Input f L a E
- -- Output Enable/ A a ""
OE/RFSH CLOCK REFRESH REFRESH m
- Refresh Input 530- WltlMhT0lt cou’mouan TIMER
CE Chip Enable Input -
I/OlmI/oa Data Inputs/Outputs OIVRFSHC
Von Power (+5V) 4 CIC)
GND Ground a,,,,-.-.]::".
TC51832P/SP/F/PL/SPL/FL-85 i
TC51832P/SP/F/PL/SPL/FL-10
q8E 1) Cl 9097396 0023012 i? UTOSE
TC51832P/SP/F/PL/SPL/FL-12 TOSHIBA (Lotirc/tiEh0RY)
T-46--23-14
[ABSOLUTE MAXIMUM RATINE
SYMBOL ITEM RATING UNITS NOTE I:
VIN Input: Voltage .-1.orv7.0 ll 1 5
VOUT Output Voltage -1.0'o 7.0 V l "
VDD Power Supply Voltage .-1.0'u 7.0 V 1 J CG
TOPR Operating Temperature 0s 70 "c 1 _ ' a
TSTG Storage Temperature -55~150 "c 1 4% a,' '
TSOLDER Soldering TegpfratureoTime 260 . 10 °C'sec 1 7.
PD Power Dissipation 600 mw l
IOUT Short Circuit Output Current 50 mA 1 L
loc REc0rMEll0E0 OPERATING CONDITIONSJ (Tu=0~ 70°C) f, ~- n
SYMBOL ITEM MIN . TYP . MAX . UNIT NOTE I',
VDD Power Supply Voltage 4.5 5.0 5.5 ll 2 is h
VIH Input High Voltage 2.4 - 6.5 V 2 4 ta.
VIL Input Low Voltage .-1.0 - 0.8 V 2 hi q m
ltc ELECTRICAL cmRAcTEpsisT1csl (1lolr--5vt10r,, Ta=0~70°C) I,',"'
SYMBOL PARAMETER PERIOD MIN . MAX ' UNITS NOTES I B? a,
Operating Current: 135ns .. 55 ‘F a
I (Average Power Supply Operating - - .
DDO garrent) 160ns 45 mA 3,4 If:
CE, Address Cycling: tRc=tRc MIN. 190ns - " F
Standby Current 1 TC51832P/SP/F - A .
I - mA _
a MSI W=GEIRFTH=VIH Tc51832PL/SPL/FL - i ' ,
' Innsz Standby Current 2 TC51832P/SP/F ... mA .3 a a
i5g--02/iiiriTr=voo-0. 2V Tc51832PL/SPL/PL - 100 PA "2
Innp Self Refresh Current: TC51832P/SP/F - 1 mA 1 a“
"tTr-Amo-tLev, i5g/iiFgi"ira0.2v TC51832PL/SPL/FL - 100 " I
Input Leakage Current: E a:
tray 0V§VIN§VDD, All other Inputs not under test=0v -10 10 " Cl
Output Leakage Current a, q
I00:) Output Disable, OVgVou'réVm) -10 10 PA s,"
Output High Level
A. Von TtNm-s-limit 2 . 4 - v
Output Low Level
VOL IOUT'4.2mA - 0.4 V a a
HBE I) C3 9097BH6 UDEEDLB H EJTOSE
TOSHIBA (LOGIC/NEHORY)
TC51832P/SP/F/PL/SPL/FL-85
TC51832P/SP/F/PL/SPL/FL-10
TC51832P/SP/F/PL/SPL/FL-12
T-46-23-14
[ELECTRICAL CHARACTERISTICS AND RECOMMENDED M OPERATING CONDITIONS]
(VDD=5v:1oz. Ta=o~70°c) (NOTES:5,6,7.8,9)
.-85 -10 ~12
SYMBOL PARAMETER MIN. MAX. MIN. MAX. MIN. MAX. UNITS NOTES
tRC Random Read or Write Cycle Time 135 - 160 - 190 - ns
tRMw Read Modify Write c§éié Time 200 - 240 - 280 - ns
tCE i-ig Pulse Width 85 10,000 100 10,000 120 10,000 ns
tp 5E Precharge Time 40 - 50 - 60 - ns
t:CIEIA 5E Access Time - 85 - 100 - 120 ns
tOEA GE'Access Time - 35 - 40 - 50 ns
tCLZ trt- to Output in Low-Z 10 - 10 - 10 - ns
tOLZ tiff to Output in Law-a 0 - o - o - ns
t Output Activririi Eng of Write
UL2 Enable 0 - 0 - 0 - n3
tCHZ Chip Disable to Output in \ugh-a 0 25 0 30 0 35 ns 10
tOHZ 55 Disable to Output In High-Z O 25 0 30 0 35 ns 10
tWHZ Write Enable to Output in Htgh-2 0 25 0 30 0 35 ns 10
tOHC 6E Hold Time Referenced to Th?" 0 - 0 - 0 - ns
tOSC "6tTset:-op Time Referenced to CE 10 - 10 - 10 - ns
tRcs Read Command Set-Up Time 0 - o - o - ns
tRCH Read Command Hold Time 0 - 0 - 0 - ns
twp Write Pulse Width 60 - 70 - 85 - ns
twcu Write Command Hold Time 60 - 70 - 85 - ns
tCWL Write Command to EE Lead Time 60 - 70 - 85 - ns
tDSW Data Set-Op Time Referenced to R/H 35 - 40 - 50 ... ns 11
tDSC Data Set-Up hii2aitereiiiTi to 5E. 35 - - 40 - 50 - na 11
tnaw Data Hold Time Referenced to R/w 0 - o - o - ns 11
toiic Data Hold Time Referenced to "dig" 0 - 0 - 0 - ns 11
tASC Address séEpr Time 0 - o - o - ns 12
t:AHC Address Hold Time 20 - 25 - 30 - ns 12
tec Auto Refresh Cycle Time 135 - 160 - 190 - ns
titFO EE to Ttgg' Delay Time 40 - 50 - 60 - n8
tFAP "RTgTi Pulse Width (Auto Refresh) 80 8,000 80 8,000 80 8,000 as 13
tFP iiWiT Precharge Time 30 - 30 - 30 - ns 13
tFCE -iiFsTi to CE'Active Delay Time 160 - 190 - 225 - ns 13
tFAS TtWig Pulse Width (Self Refresh) 8000 - 8,000 - Moo - ns 13
CFRs ?Eegglzzf::::)fr°m RFS1l 160 - 190 - 225 - ns 13
TC51 832P/SP/F/PL/SPL/FL-85
TC51832P/SP/F/PL/SPL/FL-10
TC51832P/SP/F/PL/SPL/FL-t2
'-Mt-t=l-=-=ggg=tg
"Ili? 1) D “1097293 Clrlii?ii!0htt I: DTOSE
TOSHIBA (LOCIC/MEMORVYY
T.-.itr..23..n 4i
(tf6ntinued)
SYMBOL PARAMETER '-85 -10 -12 UNITS NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
RFSH Set-Up Time
tFST (Refresh Counter Test) 10 30 10 30 10 30 ns
RFSH Hold Time
cm“. (Refresh Counter Test) 65 8,000 65 8,000 65 8,000 ns
tREF Refresh Period - 4 - 4 - 4 ms
tT Transition Time (Rise and Fall) 3 50 3 50 3 50 ns
CAPACITANCE (VDD=5V, f=1MHz, Ta=25°C)
SYMBOL _ PARAMETER MIN. MAX. UNITS
CI1 Input Capacitance (AO'VA14) - 5 pF
C12 Input Capacitance (tTil, iiTg/riirsm, R/W) ... 7 pl?
CIO Input/Output Capacitance (I/OlA.I/08) - 7 pr'
NOTE) This parameter is periodically sampled and is not 100% tested.
us}: I) © 'iiPr?iyill nuaaums a EITOSE TC51832P/SP/F/PL/SPL/FL-85
TC51832P/SP/F/PL/SPL/FL-10
TOSHIBA (LOGIC/NENORY) TC51832P/SP/F/PL/SPL/FL-1 2
T-46-23-14
NOTES:
I) Stresses greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device.
t 2) A11 voltages are referenced to GND.
3) IDDO depends on cycle rate.
4) IDDO depends on output loading. Specified values are obtained with the
output open.
f 5) An initial pause of lms with high 5? and high 6E/RFSH arereqpured attep
power-up, before proper device operation is achieved.
6) AC measurements assume tT=5ns. -
7) VIH(min.) and VIL(max.) are reference levels for measuring timing of Input /
signals. Also, transition times are measured between VIH and VIL- k
I 8) Measured with a load equivalent to 2 TTL loads and 100pF.
9) The GE/RFSH Input operates as the output ggeble input_(5E) and refresh control
F input=(RFSH) under the condition of that CE=VIL and CB=VIH, respectively.
10) tCHZ, COHZ, tua define the time at which the output achieves the open
circuit condition and is not referenced to output voltage levels.
11) In write cycles, the Input data ls latched at the earlier of R/w or 6if rising
' edge. Therefore the input data must be valid during set-up time (tpsu, tmsc)
I and hold time (tpuw, tmic).
f 12) All address inputs are latched at the falling edge of CE. Therefore all the
f address inputs must be valid during tASC and tiulc.
13) Two refresh operation ... auto refresh and self refresh are defined by the
5E/RFSH pulse width under the condition of EE=VIH.
Auto refresh:§?/RFSH pulse widthétFAP (max.)
Self t:erresh:trE/ITFgg pulse widchtFAS (min.)
The following timing parameter must be kept for proper device operation after refresh
Auto refreshthCE
Self refreshthRS
TC51832P/SP/F/PL/SPL/FL--85
TC51832P/SP/F/PL/SPL/FL-10
TC51832P/SP/F/PL/SPL/FL-1 2
LIBE J) Cl HU‘WBHB UDEEDLE T EITOSE
TOSHIBA tLotsrivmrruFrr
"""---Mlt=i=--L----------s=-
-- - 7 - 1 J, l:
TIMING CHART T464344
Att: l
READ CYCLE tp . a
Trm' v - . tea , ca
ce 61' - N, / L.., lr 'h
It Max tAm: 3" in
AW” v12: vmmss 1l,lrlllllllWllff[fl[lfflffffflIll, . a i,
tone tosc n”
tTttYrTi'frt 3:: IT. g / y I aa,
tn tncu n
n/w IUu - - T
v", T...) tom tcnz IL-.
tom k touz
1/01sV08 :3: Ir. tow, Cy DATA-OUT F---- l,,
tom. T
WRITE CYCLE
-.. tne .-,
tp A a
"trg" ll t - . km ==ezzil, . 1
u Vill. - 7 N / _‘_____ 1
tAse tAnc u
v - J. r.
“M” vi: - w ADDRESS "3jjlllllMllllllllllli lllllllll[lllllll0lh
tose A bas, 1
A - V - .
oz/ITE‘EH~ Vi: ___/ fl tmm "hc,, ,
tcm, I
n/w :1" l-f tint 2
IL tnsw tww i:
tnsc tau: 1
1/o1~I/08 3:1: IC-----------------" DATA-IN F--------
(d/ff, t Don't care l
u t, an a L " h
re " a
INEED I:
'30cr?i?q8 002201.? l DTOSE’
'TOSHIBA (L(/6it:/mi:h(yRY)
TC51 832P/SP/ F/ PL/SPL/ F L-85
TC51832P/SP/F/PL/SPL/FL-1 0
TC51832P/SP/F/PL/SPL/FL--1 2
READ MODIFY WRITE CYCLE
AO-gl 4
1/01 ~I/08
V11. -
V11. -
T-46-23-l 4 V
6? ONLY REFRESH CYCLE
'irii/iTiriiTi
Vol ~I/OB
Vit, -
Ytb---
VIII -
's., tea " L_....
ADDRESS l/l/l
tone I tosc
X. f b J
l twp ,.
mm mm} o,iL"l'". IN F--------
toLy, {% DATA-OO //// /
-h,, ta;
Ammsss' M) "1rl1llfll1llllrllh
L_.....-.,...,,
Td/ ' Don't: care
TOSHIBA (Lbéféimzmom )"
TC51832P/SP/F/PL/SPL/FL-85
TC51832P/SP/F/PL/SPL/FL--10
TC51832P/SP/F/PL/SPL/FL-12
LIBE I) CCI “1097946 t1iili?ii!018 3 EITOSE' T
T-46-23-l 4
In nun
AUTO REFRESH CYCLE
- vm - -
CE Vu. -... -....U'
turn trc
vm - tryw
"oitTrrsT1
. VIL - /
I/OI'VI/OB OPEN
d7272?i2l22j,li'
Note) AONAllo, R/W=Don't care
SELF REFRESH CYCLE
izil.. Don't care
Tir-i VIII - ff ,
vii, -
tttyo tms
tii-tpt-tit" V1” -
vu, - u
1/01~1/oa OH OPEN
vor, --
Note) AONAlé, R/w=Don't care
TOSHiBA (LOGIC/NEHORY) bills: 1) El “1097346 i3tli?iiltl1R 5 CITOSE
TC51832P/SP/F/PL/SPLIFL-85
TC61832P/SP/F/PL/SPL/FL-10
TC51832P/SP/F/PL/SPL/FL-12
T--46-23-1 4
REFRESH COUNTER TEST CYCLE (READ WRITE)
a 3:1: :/ x tteg Ns..,..-..,.,,
A0-h14 ",t(peo!jjyjooo-roooocoocjlooo,
tpm, I tosc
- v - t , t
'0Tv'rirWr m --s'z'e'zh P ST FT IT Z oil
tncs tcm, I
n/w vm - a l twp /
V11. -
tosw tmlw
tost: tout:
f" v"/lT. i DATA-IN F------
1/01~1/os L
L tcm tony. 'rv tcnz
It - _
our V8: -L-----------------Tiy DA'l'A-OU'I' F----! ///J
': Don't care
REFRESH COUNTER TEST
The Internal refresh operation of TCSl832P family can be tested by REFRESH COUNTER
TEST. This cycle performs READ/WRITE operation taking the internal counter address
as row address and fixed zero as column address.
The test procedure is as follows.
Write "0" Into all the memory cells at normal write mode.
Read "0" out and write "1" in each cell by performing REFRESH COUNTER TEST.
Repeat this operation 256 times.
Check "1" out of 256 bits at normal read mode, which was written at co.
Read "1" out and write "0" in each cell by performing REFRESH COUNTER TEST.
Repeat this operation 256 times.
Check "0" out of 256 bits at: normal read mode, which was written at © .
Perform the above C) to (li) the complement data.
@® @@ ®®
Tna----'':,
" iirFiiiij:iaj(7Lirii'ic7iiiiiio-ivin um: I) CCI “10972116 0022020 l EITOSE '
TC51832P/SP/F/PL/SPL/FL-85 -' '
TC51832P/SP/F/PL/SPL/FL-10 - 46 2? 14 i '
TC51832P/SP/F/PL/SPL/FL-1 2 T- - -
(DIP28-P-600) ta a
Unit in mm 1
re.?,,-.,,-.-,,-,,....,,-,,...,,-,,.,,,-,,-) - 'i'' ii
g mp gig“
) a [i]
t - 4i
"r''-""""""'-''-''" M --uteeass Ir,'
=-rt g t' =9
37.0:h0.2 (ti
- i',,
- - A,
1.991'Yl'. .635 N) :'ii ( a
NOTES.. Package width and length do not include mold protrusion, .. a
allowable mold' protrusion is 0.15m.
These outline drawings apply to:
TC51832P-85, TC51832PL-85
TC51832P-10, TC51832PL-10
TC51832P-12, TC51832PL-12 1 ca
A-10 l a
_o''r,
W = U 3 'h
a _ u .'l a " "ss,
n u u u h, o t, a
y, u D u d " :3
TOSHIBA (LOGIC/NEHORY) LIEaE D El ‘IEI'WEHB 0033031: 3 UTOSE
TC51832P/SP/F/PL/SPL/FL-85
TC51832P/SP/F/PL/SPLIFL-"
OUTLINE DRAWINGS (DIP28-P-300)
TC51832P/SP/F/PL/SPL/FL-12
Unit in mm
28 15 - ----. J,
C'hr-tr-Tr''-tf-Tr-tr"-tetr-Netf-trmr"'''t
g. h a:?
ts +I°
L.., L4 L4 1..u LJ L4 L4 L4 L4 L4 L4 L4 L4 cal 'lf'
t 14 $1
34.9:h0.2 f/
...z o
l 0.5d:0.t
0.9 4 'TYP. 2.54 1.4' Au
Note: Package width and length do not: include mold protrusion,
allowable mold protrusion is 0.15mm.
These outline drawings apply to:
TC51832SP-85, 'N51832SPL-85
TC51832SP-10, TC518328PL-10
TC51832SP-12, TC51832SPL-12
/iri;-idiiridokrc/mi:noirir) I431: I) III auqvaua 0022022 5 CITosa
Tc51832P/SP/F/PL/SPL/FL-85
TC51832P/SP/F/PL/SPL/FL-10 T_46_23_1 4
TC51832P/SP/F/PL/SPLIFL-12
(SOP28-P-k50)
Unit in mm
I 8.5i 0.2
flf'lrl0f1f1l1flfll1llf'lflfl
8.821: 0.2
1 l.8:i:0.3
LOTYP,
$uu?uuuuuuuuuy|___
ll, 0.43120.)
Note: Package width and length do not include mold protrusion,
allowable mold protrusion is 0.15mm.
These outline drawings apply to:
T051832F-85, TC51832FL-85
Tc51832P-10, TC51832FL-10
T051832F-12, TC51832FL-12
u a a u -X, war u N E
u a nus r a
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www.ic-phoenix.com
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