TC514410AZ-80 ,80 ns, 4-bit generation dynamic RAMABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING NOTES
input Voltage Vm
Output Voltage Vout
Power ..
TC514800AJLL-70 , 524288 WORD X 8 BIT DYNAMIC RAM
TC51832F-12 ,120ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAMFEATURES
. Organization: 256K bit(32,768 word x 8 bit)
. Fast Access Time and Low Power Dissipa ..
TC51832FL-10 ,100ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAML---.
082
_,__,J
TOSHIBA tL0GTC/hEh0RY) LIBE D " “1037343 00220]: l] -T
32,768 WORD x 8 B ..
TC51832FL-12 ,120ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAMABSOLUTE MAXIMUM RATINGS
VOUT Output Voltage
Power Supply Voltag;
TOPR Operating Temperature
..
TC51832PL-10 ,100ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAML---.
082
_,__,J
TOSHIBA tL0GTC/hEh0RY) LIBE D " “1037343 00220]: l] -T
32,768 WORD x 8 B ..
TC7WG14FC ,L-MOS LVP seriesabsolute maximum ratings. OUT1A 3Y 2A GNDNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 ..
TC7WG14FU ,L-MOS LVP seriesAbsolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating UnitSupply voltage V −0.5 to 4. ..
TC7WG17FK ,L-MOS LVP seriesabsolute maximum ratings. OUT Start of commercial production2006-02Note 3: V < GND OUT1 2014-03-01 ..
TC7WG17FU ,L-MOS LVP seriesAbsolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating UnitSupply voltage V −0.5 to 4.6 ..
TC7WG32FC ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTNote 4: Mounted on an FR4 board. Start of commercia ..
TC7WG32FK ,L-MOS LVP seriesabsolute maximum ratings. OUTStart of commercial productionNote 3: V < GND OUT2006-031 2014-03-01 T ..
TC514410AZ-80
100 ns, 4-bit generation dynamic RAM
1,048,576 WORD x 4 BIT DYNAMIC RAM
DESCRIPTION
PRELIMINARY
The TC514410AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 1,048,576 words by 4
bits. The TCSl44IOAP/AJ/ASJ/AZ utilizes TOSHIBA'S CMOS Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and to the system user.
Multiplexed address inputs permit the TC514410AP/AJ/ASJ/AZ to be packaged in a standard 20 pin
plastic DIP, 26/20 pin plastic SOJ(300/350mi1) and 20 pin plastic ZIP. The package size provides high
system bit densities and is compatible with widely available automated testing and insertion
equipment. System oriented features include single power supply of 5V:|:10% tolerance, direct
interfacing capability with high performace logic families such as Schottky TTL.
FEATURES
. 1,048,576 word by 4 bit organization
. Fast access time and cycle time
PIN CONNECTION (TOP VIEW)
Plastic DIP Flame SOI Plastic ZIP
wmoHI zolvss
WIIIOIH
WZJIOIIZ 19IW4/IOI WMO202
ASIS 16.5; M05
AOIS 150A8 Mt
Attl7 MIA7 gum
ANJ8 13IA6 Allll
A3t19 IIIAS ASHI
Vcc'W HIM Vcc'll
TCSM410AP/AJ/A51/ AZ - 70/ - 80/ - IO
IRAC m Actess Time 70ns 80ns 100ns
Un Column Address Access Time 35ns 40ns lions
tou: EAT Access Time 20ns 20ns 25ns
tn: Cycle Time 130ns 150m 180M
tpt Fast Page Mode Cycle Time Mns 50ns 60m
f.Ll)LeN2h/_li.ifi
A0-A9 Address Inputs
ATG Row Address Strobe
CAT Column Address Strobe
WWW? Write Per 8it/ReadN/rite Input
tft Output Enable
w1llOI~Wdll04 Write Select/Date Input/Output
Vcc Power( . 5V)
Vss Ground
. Single ower suaply of 5V:t10%
with a uilt-in BB generator
. Low Power
550mW MAX. Operatin
(TC514410AP/AJIAS /AZ--70)
468mW MAX. Operatin
(TC51 1itliA3heloht'?V - 80)
413mW MAX, Operatin
(TC514410AP/AJ/A /AZ-10)
5.5mW MAX. Standby
. Output unlatched at cycle end allows
two-dimensional chip selection
. Read-Modif -Write, GAS before RM
refresh, RA only refresh, Hidden
refresh, Write Mi Bit, Fast Page
Mode and Test ode ca ability
q Allinputsand outputs L Compatible
1024 refresh cycles/16ms
Package
T0514410AP ' MP20-P-300C
TCSI4410AJ :SOJ26-P-350
T0514410ASJ :SOJ26-P-300A
TC514410AZ l ZIPZ-P~400A
iLl.,t22ilAtLR2W1.
WIIIOI W21102 WBIIOJ WMOI
Vet Vs:
DATA IN
I U FFERS
DATA our
BUFFERS
no.1 CLOCK
GYM GEN umn
C M COLUMN
Aoo- fsihiih1 m} 92:00er
Ato- a ma ol
A2 o- REFRESH 'i'g'dtl''.
A3 o- CONYROLLER
Mo. .1024“
A50» (nsrnssu tr4
A6Oe 0 /!'" 5 MEMORY
2:0. .. s C'-,', W
A l t 4
A90. surggg l, t,' i " :41“
m0 , NO.t CLOCK SUBSTMYE BIAS
GENERAYOR GENERATOR
TC51 441 tJAP/AJ/ASO/AZ-ro, TC51 4410AP/A0/ASJ/Az-80
TC51 441 tYAP/AJ/ASU/Az-l o
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
input Voltage " .-1-7 V 1
Output Voltage Vour - _ V 1
Power Supply Voltage Vcc - 1~7 V 1
Operating Temperature Tom 0~70 'C 1
Storage Temperature Tsro - 55-150 'C 1
Soldering Temperature . Time Tsouso 260 . 10 T . sec 1
Power Dissipation Po 700 mW t
Short Circuit Output Current tour 50 mA 1
RECOMMENDED DC OPERATING CONDlTlONS(Ta=0-70''c)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES
Vcc Supply Voltage 4.5 5.0 5.5 V 2
V." Input High Voltage 2.4 - 6.5 V 2
" Input Low Voltage - 1.0 - 0.8 V 2
TC51 441 oAP/AJ/ASJ/Az-70, TC51 441 oAP/AJ/ASJ/Az--8o
TC51 441 tYAP/AJ/AN/AZ-l O
DC ELECTRICAL CHARACTERISTICS (Vcc = 5V i 10%, Ta = 0--7ty'c)
SYMBOL PARAMETER MIN. MAX. UNITS NOTES
OPERATING CURRENT TcsuautiuowAstjAz.rts - 100 3 4
ICU Average Power Supply Operating Current TCs1Mt0APfA#ASJttu-80 - 85 mA
(m. EET, Address Cycling: tac=tnc MINJ TCSIulaAémuAsqu-Io - 7S s
STANDBY CURRENT
Icct Power Supply Standby Current - 2 mA
(m=OTS=vm)
m ONLY REFRESH CURRENT TtalqM0AMutASyAb70 - 100
lccz Average Power Supply Current, m Only Mode TCs1Mt0ANAttA$ltAb80 - 85 mA 3, 5
(m Cycling. em, Wt'. tnc- tec MW.) TCMMi0AWAgfASlfAb10 - "
FAST PAGE MODE CURRENT TCMMt0AWAllAStl/tr0 - " 3 4
Average Power Supply Current, Fast Page Mode Tcsmwum/Aslmz-ao - 65 mA
lcca (m=VILa ar. Address Cycling: tpc=trt MIN.) TCSt0t0tuVgulASgtA2.t0 - ss s
STANDBY CURRENT
lccs Power Supply Standby Current - 1 mA
(R23 = US: Vcc - 0.2V)
m BEFORE m REFRESH CURRENT TcsmwAPwmsqu-Io - too
tccs Average Power Supply Current, CAT Before m TCsua10guVNtA$MAb80 - 85 mA 3, s
Mode (W. ES Cycling: tgcxtgc MIN.) TCs1M10AWAJtASJtAbto - "
INPUT LEAKAGE CURRENT
I. (L) Input Leakage Current, any input - 10 1O pA
(0VSVmeS6.5V, All Other Pins not under Test=0V)
t OUTPUT LEAKAGE CURRENT 10 10
t) tc) (Door is disabled, 0VSVours5.SV) PA
OUTPUT LEVEL
VOH " l 2.4 - V
Output H Level Voltage (lour= -SmA)
OUTPUT LEVEL
Vac " " - 0.4 V
Output L Level Voltage (krur=4.2mA)
A-51 1
TC51 441 oAP/AJ/ASJaz---70, TC51441 oAP/AJ/AS0/Az--80
TC51 441 oAP/A0/ASJ/Az--1 o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc=SV-t 10%, Ta=0~70°c) (Notes 6, 7, 8)
TC514410AP/ TC514410AP/ TC514410AP/
SYMBOL PARAMETER AJIASJIAZ-7O AltASl/Ab80 AJIASJIAZ-W UNIT NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
tec Random Read or Write Cycle Time 130 - 150 - 180 - n:
tmw Readmilod'ifyN/rite Cycle Time 185 - 205 - 245 - ns
tpt: Fast Page Made Cycle Time 45 - 50 - 60 - n:
tpww t?y'ee'''/,e,eMo" Read-Modify-Write 100 - 105 - 125 a ns
teat Access Time from m - 7O - 80 - 100 ns '),"
ttyu: Access Time from m - 20 - 20 - 25 ns RM
tan Access Time from Column Address - " - 40 - 50 ns 9.15
km Access Time from m Precharge - 40 - 45 - 55 ns 9
tcu eas to output in Low-Z 0 - 0 - 0 - ns 9
ttrr Output Buffer Turn-olf Delay 0 20 o '20 o 20 ns It)
h Transition Time (Rise and Fall) 3 SO 3 50 3 50 n5 8
to, W Precharge Time 50 A.. 60 - 70 - ns
toss m Pulse Width 70 10,000 80 10,000 100 10,000 ns
tusp m Pulse Width (Fan Page Mode) 70 200,000 80 200,000 100 200,000 ns
mm m Hold Time 20 - 20 - " - ns
mucv 55: ZZISeTtiwrrledeF;om m Precharge 40 - 45 - 55 - m
((5,, m Hold Time 70 - 80 .- 100 - ns
toss CE Pulse Width 20 10,000 20 10,000 25 10,000 ns
titCD m to m Delay Time 20 so 20 60 25 75 ns 14
IMO W to Column Address Deiay'Time 15 35 IS 40 20 50 ns 15
tcsw G5 to m Precharge Time 5 - s - 10 - ns
tor US Precharge Time 10 - 10 - 10 - m
y tasa Row Address Set-op Time 0 - 0 - 0 - ns
{Mu Row Address Hold Time 10 - 10 - IS - m
tasc Column Address Set-Up Time 0 - 0 - 0 - ns
ICAH Column Address Hold Time 15 ... 15 - 20 - ns
Hm. Column Address to m Lead Time 35 - 40 - 50 - ns
lacs Read Command Set-Up Time 0 - 0 - 0 - ns
tsro, Read Command Hold Time 0 - 0 - 0 - ns 11
TC51 441 oAP/AJ/AS0/Az-70, TC51 441 0AP/AJ/ASJ/Az-80
TC51 4410AP/AJ/ASd/Az-1 o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Continued)
TC514410API TC514410AP/ TC514410AW
SYMBOL PARAMETER AJ/ASIIAZ-TO AJIASJIAZ-BO AJ/ASJIAZ-IO UNITS NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
tmm Read Command Hold Time referenced 0 - 0 - 0 - ns II
two, Write Command Hold Time _ 15 - 15 - 20 - ns
twp Write Command Pulse Width 15 - IS - 20 - ns
1ng Write Command to m‘ Lead Time 20 - 20 - 25 - ns
tch Write Command to CPS Lead Time 20 - 20 - 25 - ns
ttos Data Set-Up Time t) - 0 - O - ns 12
tor, Data Hold Time 15 - 1S - 20 - ns 12
mg; Refresh Period - 16 - 16 - 16 ms
twct Write Command Set-UP Time 0 - 0 - i) - ns 13
ch0 CAT to Wt Delay Time so - so -. 60 - m 13
(Rwo m to WT Delay Time 100 - Ito - I35 - ns 13
tAwo Column Address to W Delay Time 65 - 7O - 85 - n: 13
'tcpwo CK; Precharge ta WR-ITE Delay Time " - " - 90 - ns 13
m Set-Up Time
tcpt (m before W Cycle) 5 - S - 5 - m
CAT Hold Time
tco (GS before AM Cycle) 15 - IS - 20 - M
lapc m to m Precharge Time 0 - O - 0 - ns
CAT Precharge Time
tcpr (m before m Counter Test Cycle) 40 - ao - st) - n5
tnon m Hold Time referenced to'UE 10 - I 10 I - 20 - ns
tom 6: Access Time - " - 20 - 25 ns
teen TE to Data Delay 20 - 20 .. " 4 ns
totz Output buffer turn off Delay Time 0 20 0 " 0 20 ns
from trg
tom US Command Hold Time 20 - 20 - " - ns
twas Write Per Bit Set-Up Time 0 - 0 - 0 - ns
Ivor, Write Per Bit Hold Time 10 - 10 - IO - ns
twos Write Per Bit Selection Set-Up Time (l - 0 - 0 - ns
lwon Write Per Bit Selection Hold Time 10 - 10 - 1O - ns
TC51441 tYAP/AJ/ASO/AZ-N, TC51 441 oAP/A0/ASd/Az--80
TC51 441 tYAP/AJ/ASO/AZ-l 0
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Continued)
TCS l 44 I OAPI
AJIASJIAZ-70
TC514410API
JUlASJlAb80
TCS I 44 1 GA?!
AJ/ASJ/AZ-l 0
SYMBOL PARAMETER UNIT NOTES
MIN. MAX. M)N. MAX. MIN. MAX.
twrs Write Command Set-up Time 10 - 1O - 10 - ns
tw-m Write Command Hold Width 10 - 10 - 10 - ns
twnp WE to m Precharge Time 10 - 10 - 10 - n:
Mm WT to RTE Hold Time 10 - 10 - 1O - ns
TC51 441 oAP/AJ/ASd/Az--70, TC51 441 oAP/A0/ASJ/AZ-80
TC51 441 oAP/A0/ASJ/Az--1 0
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE
TEST MODE (Vcc = 5V t 10%, Ta = 0~70°C) (Notes ii, 7, 8)
TCS14410API TC5 144 1 OAP/ TC514410APl
SYMBOL PARAMETER AJIASJIAZJO AHASJ/AZ-80 AJ/ASJIAZ-10 UNIT NOTES
MIN. MAX, MIN. MAX. MIN. MAX.
tec Random Read or Write Cycle Time 135 - 155 'c. 185 - ns
tmw Read-Modify-Write Cycle Time 160 - 180 - 215 - ns
tpc Fast Page Mode Cycle Time 50 - SS - " - ns
tvmw 23:19P:?;9M°de Read-Modify-Write 75 - 80 - . . 95 - m
taac Access Time from m - " - 85 - 105 ns 9'11:
tcat Access Time from m - 25 , - " - 30 ns 9,14
tan Access Time from Column Address - no - " - 55 ns 9,15
tora Access Time from m Precharge - " - so - 60 ns 9
uas RX; Pulse Width 75 10,000 85 10,000 105 10,000 ns
teast, E755 Pulse Width (Fast Page Mode) 75 200,000 85 200,000 105 200,000 m
tug“ m Hold Time 7 25 - " - 30 - ns
tcw C753 Hold Time " - 85 - 105 - n5
1mm: CAT Precharge to liM Hold Time 45 - 50 - 60 - ns
tcat G5 Pulse Width 25 10,000 25 10.000 30 10,000 ns
tttnt Column Address to m Lead Time 40 - " - ss - as
ttwo CET to WE Delay Time 55 - " - 65 - ns 13
tawo ES to WE Delay Time t05 - Its - 140 - ns 13
tawo Column Address to WE Delay Time 70 - " - 90 - ns 13
tcpwo G5 Precharge to WRTTE Delay Time 80 - 80 - 9S - ns 13
ton tR Access iime - 25 - 25 - 30 M
too, IR Command Hold Time 25 - 25 - 30 - ns
. CAPACITANCE (Vcc = 5V , 10%, f=1MHz, Ta = 0--70''c)
SYMBOL PARAMETER MIN. MAX. UNIT
Cn Input Capacitance (AO-NO - 5 pF
Ca Input Capacitance (m, m, WEIWE, ug) - 7 pF
co Input/Output Capacitance MOI-PIM) - 7 pF
T051441 oAP/Ad/ASJ/Az--70, TC51 441 oAP/AJ/ASJ/Az--8o
TC51 441 tYAP/AJ/ASO/AZ-l 0
NOTES:
I. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
2. All voltages are referenced to Vss.
3. [am Icca. Icc4, Ices depend on cycle rate.
4. ICCI. ICC4 depend on output loading. Specified values are obtained with the output open.
5. Column address can be changed once or less while man, and CAS=V[H.
6. An initial pause of 200ps is required after pqwerfup followed by 8 m only refresh before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 m
before m refresh cycles instead of 8 m refresh cycles are required.
T, AC measurements assume tT=5ns.
8. Vm (min.) and vn, (max.) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VII,
9. Measured with a load equivalent to 2 TN, loads and 100pP.
10. torrtmax.) and defines the time at which the output achieves the dpen circuit condition and is not
referenced to output voltage levels.
ll, Either tncu or tmm must be tsatisfied for a read cycle.
12. These parameters are referenced to t5ES leading edge in early write cycles and to WRITE leading
edge in Read-Write cycles.
13. twcs, tnwn, town, Mum and tcpwn are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If twcsit twcs(min.), the cycle is an early
write cycle and the data out pin will remain open cireuitthigh impedance) throughout the entire
cycle; If tRmrittRwDtmin0, tcwn?2 tcwn(min.) ' tAwoit tAwoimin.) and tcpwnz tCPwn(min.)
(Fast Page Mode), the cycle is a Read-Write cycle and the data out will contain data read from the
selected cell: If neither of the above sets of conditions is saiisried, the' condition of the data out (at
access time) is indeterminate.
14. Operation within the tncp(max.)1imit insures that true (max.) can be met.
taco (max) is specified as a reference point only: If tRCD is greater than the speeiiied tRcMmax.)
y limit, then access time is controlled by tCAC.
15. Operation within the tRAD(max.)limit insures that tmc (max) can be met.
tmmmnx.) is specified as a reference point only: If tub is greater than the speeifled tRAMmax.)
limit, then access time is controlled by tAA.
TC51 441 tJAP/AJ/ASO/AZ-N, TC51441 oAP/AJ/ASd/AZ-80
TC51 441 0AP/AJ/ASJ/Az--1 O
READ CYCLE
CO LUMN
v... ---
w1noz~
W4/I04 " -
(B. t "H" or "U'
Note: MN="H" or "L"
DATA- OUT
WRITE CYCLE (EARLY WRITE)
" -..-..
A0 --A9
m _ COLUMN
WI/lol-- VIN
- MASK
wanoa " - DATA - IN DATA. W
Note: DOUT=OPEN Big: "H" or 'L'
TC51 441 oAP/AJ/ASJ/AZ-70, TC51 441 oAP/Ad/ASJ/Az-80
TC51 441 oAP/AJ/ASu/AZ-1 0
WRITE CYCLE (02- CONTROLLED WRITE)
WB‘IW'E
WI/lots VIH
w4n04 "
taut tmu,
"C.",'.'.,". ROW COLUMN
Cr.. DATA- IN
DOUT=OPEN I: "H" or 'L'
READ - MODIFY - WRITE CYCLE
WUIOV-
W4/104
COLUMN
DATA-l N
DATA - OUT
TC51 441 oAP/Ad/ASJ/Az--70, TC51441 oAP/AJ/ASJ/AZ-80
TC51 441 thip/AJ/ASO/Az-l o
FAST PAGE MODE READ CYCLE
m “H -
A0--A9 vi: -
- Ihr, -
WI/lol-- Von -
wanoa Von. -
Note: lhN--"H''or"L" 'tpt I "H" or "L''
FAST PAGE MODE WRITE CYCLE
Ihr, -
A0--A9 V:
mm st'
WI/lol-- Vm - MASK
WdllOd VIL - TA.
. El "H" or (
Note: DOUT=0PEN
TC51 441 oAP/AJ/ASJ/AZ-N, TC51 441 tJAP/AJ/AN/AZ-tro
T051441 0AP/AJ/ASJ/AZ-1 o
PAST PAGE MODE READ-MODIFY-WRITE CYCLE
w me I - OH
W4/104 VOL
M AS K
- DATA-IN
m ONLY REFRESH CYCLE
..r"'"'-'-""''"""'-"-"S
W, 'l tttas I
Vit. - y ls . .. .
too l torc
Cif:_/ \_/
:1: :K W/
liar. "H" or "L"
: WRITE, UE="rt" or "L"
TC51441 oAP/AJ/ASJ/AZ--70, TC51 441 oAP/AJ/ASJ/Az--80
TC51 441 OAP/AJ/ASJ/Az--1 t)
CA3 BEFORE RAE REFRESH CYCLE
Urs tttp
VI” - a MS I a
" --- ~k
m "t :fxf‘lk ---tsv-----1, ////////////////////
twap twilH ,
m-ss-cts,,...:.-'-,,,:), I ','ji'ifijiii, ',)jjj,ijiij', ',,'riifj,ri(ti',,,
wm 1- OH N
0 OPEN
wa/Ioa Voc----. /
Note: thm Br, A0-A9= "H'' or "c"
Eil.. "H" or "L"
TC51 441 oAP/AJ/ASJ/AZ-70, TC51 441 tJAP/AJ/ASO/Az-tXI
TC51 441 oAP/A0/ASd/Az-1 o
HIDDEN REFRESH CYCLE (READ)
teat (RP ter,
" ---et C-""'"""""''
" - 's, / 'Nc-c-Cllr:-------,?
.‘CRP a ‘nco V tam tom I tou,
" - I sho, j/e"-"--'---
" - tstat, ')s,
‘IAH tout
‘Asnl "’1
't -:,..-..-iiiiii'ikilistiiy.tc-. //////////////////////////////////
|‘ncs I
311‘ -,;5j,tfiji; 's'ii'S''h? ts/t 'i'i''i'tiiiiiiiiiii bfjf,(fif,
" -. _'tcat: J/" A,si,,ii;'i',
I m: :33 ton [q-ate-.
'trr-----'----------'), DATA-OUT :;___
TC51 441 oAP/AJ/ASJ/Az---70, TC51 441 tJAP/Au/ASO/Az-tm
TC51441 tIAP/AJ/ASO/AZ-l 0
HIDDEN REEFRESH CYCLE(WRITE)
m 'trT,,,,"'h "' f " "s-c-rc-ci-C-tCl----" tRa I c?, Nu,
m c: ...-..:-:.rjfi'r'r t: ’L\\ y'
0-A9 1(': @Lw"
irmTT 1i,'',yrf:iiiiis'j'j,'4ii, 'jjffiih, twp - //// ////////gi/ff/ai5b,,
= 1CL1iiiiiiiiiiiiiiiiiiliiiiiEiiiiiiaiEi5iiiitiiiiiiiiiii'i4
tos Ann I
lol,, :r cr. X DATA-IN jess
El "H'' at L"
TC51 441 oAP/AJ/ASJ/Az--70, TC51 441 oAP/AJ/ASJ/AZ-80
TC51441 thip/AJ/ASO/Az-l o
UAS BEFORE RAE REFRESH COUNTER TEST CYCLE
"irh'T ::::"“‘*\ tnas t s/'=t'z'='t,
AAAAA 't W4?
a Z: I/o" /J ws''''','":',",:"''';'';')'-''
$353334 :3: C. OPEN twcs "i; u, VALID :wa _
'C-UTC",))-.,-,,,),,;;,,,,,;,),'"'-' "sais;:';:;';;;';')'),. “W 1W
a C','y11iiiigiiiiiigigiiiiiiliiitiiiiiiiliiiiiliiiiiii5
READ-MODIFY.
VVVVVVVVV
TC51 441 oAP/AJ/ASJ/Az--70, TC51 441 oAP/AJ/ASJ/AZ-80
TC51 4410AP/AJ/ASJ/Az--1 0
WE, TEAS BEFORE m REFRESH CYCLE
m:::: x tttAS f--- \_
m :i: :_/ "i'-'-'' tom ,////////////////%
i77lW7T 't ‘W/m WW/fl/ 'fijiif,fi;,
Note: Dm. UE, A0~A9-"H' or "L"
(ar/ff., , "H'' or "L''
TC51 441 OAP/AJ/ASJ/Az--70, TC51441 oAP/AJ/ASJ/Az-80
TC51 441 thip/Ad/ASU/AZ-l o
APPLICATION INFORMATION
ADDRESSING
The 20 address bits required to decode 1 of the 1,048,576 cell locations within the
TCSl410AP/AJ/ASJ/AZ are multiplexed onto the 10 address inputs and latched into the on-chip address
latches by externally applying two negative going TTL-level clocks.
The first clock, the Row Address Shchum). latches the 10 row'address bits into the chip. The
second clock, the Column Address Strobe (CKS), subsequently latches the 10 column address bits into
the chip. Each of these signals, m, and CES, triggers a sequence of events which are controlled by
different delayed internal clocks.
The two clock chains are linked together logically in such a way that the address multiplexing
operation is done outside of the critical path timing sequence for read data access. The later events in
the Wig clock sequence are inhibited until the occurrence of a delayed signal derived from the TM
clock chain. The "gated tmp feature allows the m clock to be externally activated as soon as the
Row Address Hold Time specification (tRAH) has been satisfied and the address inputs have been
changed from Row address ta Column address information.
DATA INPUTS
A write cycle is performed by bringing(W/)WE low during the R'KS/CIS operation. The falling
edge of UKS or (WFDWE strobes data on (Wi) IOi into the on-ehip data latch. To make use of the
write-per-bit capability Wgt/immust be low as m falls. In this case data bits to which the write
operation is applied can be specified by keeping Wi (/IOi) high with set-up and hold times referenced to
the m negative transition. For those data bits of Wi (/IOi) that axe kept low as m tells the write
operation is inhibited on the chip if WEU'WE) is high as m falls, the write-per-bit capability does not
work and the write operation is performed for all four data bits.
DATA OUTPUTS
The three-state output buffers provide direct 'ITL compatibility with a fan-out of two standard TTL
loads. Data-out is the same polarity as datst-in. The outputs are in the high-impedance state until TM
is brought low. In a read cycle the outputs go active after the access time interval time and tOBA are
satisfied.
The outputs become valied after the access time has elapsed and remains valied while UM and UE
are low. m or CE going high returns it to a high impedance state. In an early-write cycle, the
outputs are always in the high-impedance state. In a delayed-write or read-modify-write cycle, the
outputs will follow the sequence for the read cycle.
The UE controls the impedance of the output buffers. In the logic high position the buffers will
remain in a high impedance state.
When the UE input is brought to a logical low level, the output buffer are enabled. Both m and
M can control the output. Thus in a read operation, either OE or m returning high forces the
outputs into the high impedance state,
TC51 441 tYAP/AJ/ASO/AZ-ro, TC51 4410AP/AJ/ASJ/Az--80
TC51 441 tJAP/AJ/AN/AZ-l O
WI my1-vouttM- OPEN ---t VALID DATA-OUT )
RTS ONLY REFRESH
Refresh of the dynamic cell matrix is accomplished by performing a memory cycle at each of the 512
row address (A0-A9)within each 16 millisecond, time interval.
Although any normal memory cycle will perform the refresh operation, this function is most easily
accomplished with "m-only" cycles.
54‘s BEFORE TOG" REFRESH
CES before HS refreshing available on the TC514410AP/AJIASJ/AZ offers an alternate refresh
method. If CM is held on law for the speeiiied period(tcsa)before ES goes to low, on chip refresh
control clock generators and the refresh address counter are enabled, and an internal refresh operation
takes place. After the refresh operation is performed, the refresh address counter is automatically
incremented in preparation for the next m before m refresh operation.
PAGE MODE
The "Page-Mode" feature of the TC514410AP/AJ/ASJ/AT allows for successive memory operations at
multiple column locations of the same row address with increased speed without an increase in power.
This is done by strobing the row address into the chip and maintaining the as signal at a logic i)
throughout all successive memory cycles in which the row address is cqmmon. This "Page-Mode" of
operation will not dissipate the power associated with the negative going edge of RAS. Also, the time
required for strobing in a new address is eliminated, thereby decreasing the access and cycle times.
HIDDEN REFRESH
An optional feature of the TCSl4410AP/AJ/ASJIAZ is that refresh cycles may be performed while
maintaining valid data at the output pin. This is referred to as Hidden Refresh. Hidden Refresh is
performed by holding CM at Vit, and taking m high and after a specified precharge period (tap),
executing a Chg before RM refresh cycle. (see Figure below)
MEMORY CYCLE REFRESH CYCLE REFRESH CYCLE
m "ss-f-_,,,-,.,-..:''"'-"'";,-.,.-..-.]''""'-'"'"'
m -'-'-""'"l T-'-'""-'"'-"""'-"
This feature allows a refresh cycle to be "Hidden" among data cycles without affecting the data
availability.
TC51 441 oAP/AJ/ASJ/Az-70, TC51 441 oAP/AJ/ASJ/Az-80
TC51 441 oAP/AJ/ASJ/Az--1 O
EA_S BEFORE A7G REFRESH COUNTER TEST
The internal refresh operation of TC514410AP/AJ/AtWAZ can be tested by CKS BEFORE m
REFRESH COUNTER TEST, This cycle performs READ/WRITE operation taking the internal counter
address as row address and the input addresras column address.
The test is performed after a minimum of 8 CXS before m cycles as initialization cycles. The test
procedure is as follows.
C) Write "O" into all the memory cells at normal write mode.
© Select one certain column address and read "O" out and write "I" in each cell by performing CTS
BEFORE Kits REFRESH COUNTER TEST (READ-WRITE CYCLE). Repeat this operation 512
times.
© Check "I" out of‘512 bits at normal read mode, which was written at o,
G) Using the same column as o, read "I" out and write "o" in each cell performing tsig BEFORE
rtifg REFRESH COUNTER TEST. Repeat this operation 512 times.
© Check "o" out of 512 bits at normal read mode, which was written at a).
© Perform the above C) to co to the complement data.
TEST MODE
The TC514410AP/AJ/ASJ/AZ is the RAM organized 1,048,576 words by 4 bits, it is internally
organized 524,288 words by 8 bits. In "Test Mode", data are written Into 8 sectors in parallel and
retrieved the same way. A00 is not used. If, upon reading, two bits on one 110 pin are equal (all "1"s
or "0''s), the I/O pin indicates a "I". If they were not equal, the I/O pin would indicate a "o". Fig. 1
shows the block diagram of TC514410J/Z. In "Test Mode", the 1MX4 DRAM can be tested as if it were
a 512KX4 DRAM.
"WE, Wig Before Wig Refresh Cycle" puts the device into "Test Mode". And 'CAS Before m
Refresh Cycle" or “m Only Refresh Cycle" puts it back into "Normal Mode". In the Test Mode, "WE,
TAS Before m Refresh Cycle" performs the refresh operation with the internal refresh address
counter. The "Test Mode" function reduces test times (1/2 in case ortl test pattern).
TC51 441 oAP/AJ/AS0/Az-70, TC51 441 tJAP/AJ/ASU/AZ-tm
TC51 441 OAP/AJ/ASJ/Az-1 O
BLOCK DIAGRAM INTHE TEST MODE
_ Aoc Vcc
A w--------" Normal
oc A o--]
----iuF- ' I Drs-------------;
Normal _ 512Kb|ock - '4 Test
pot C Co . Aoc A POI
Test 8
512K block - 5 DY-dt')
B I 'ts----]
-------o iNormal
--------o
Atoc V C
----o Normal
Aoc C -o--l
--osdy---- '
Normal 512K block - s--) Do Test
1/02 --"'so, - C no:
Test Aoc D
N 512K block - l Dy-------------;')
D r 'xr----]
---o iNormal
Am: V C
---------o !Normal
Aoc E "o--]
Normal -----iuh--- t
. 512K block - o-) CDxy- oTest
I/03 "ss, -...._ E 1/03
Test Aoc F
512K block - ', CDs-------------;')
F ' "ry-l
----o T Normal
------o
Aoc VCC
' A -----o Normal
oc G rxr---l
--chs.o-n l l 2t:Y---o.
Normal 512K block - >4 Test
1/04 --eu ---- G
C A V04
Test Jeb.- H
512K block - ',rCDy----------Re
H fl 'xr----]
-----o iNormal
-----<)
Fig. 1
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