TC514410ASJ-60 ,60 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization
I Fast access time and cycle time
. Single
..
TC514410AZ-80 ,80 ns, 4-bit generation dynamic RAMABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING NOTES
input Voltage Vm
Output Voltage Vout
Power ..
TC514800AJLL-70 , 524288 WORD X 8 BIT DYNAMIC RAM
TC51832F-12 ,120ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAMFEATURES
. Organization: 256K bit(32,768 word x 8 bit)
. Fast Access Time and Low Power Dissipa ..
TC51832FL-10 ,100ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAML---.
082
_,__,J
TOSHIBA tL0GTC/hEh0RY) LIBE D " “1037343 00220]: l] -T
32,768 WORD x 8 B ..
TC51832FL-12 ,120ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAMABSOLUTE MAXIMUM RATINGS
VOUT Output Voltage
Power Supply Voltag;
TOPR Operating Temperature
..
TC7WG126FK ,L-MOS LVP seriesabsolute maximum ratings. OUTStart of commercial productionNote 3: V < GND OUT2006-021 2014-03-01 T ..
TC7WG14FC ,L-MOS LVP seriesabsolute maximum ratings. OUT1A 3Y 2A GNDNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 ..
TC7WG14FU ,L-MOS LVP seriesAbsolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating UnitSupply voltage V −0.5 to 4. ..
TC7WG17FK ,L-MOS LVP seriesabsolute maximum ratings. OUT Start of commercial production2006-02Note 3: V < GND OUT1 2014-03-01 ..
TC7WG17FU ,L-MOS LVP seriesAbsolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating UnitSupply voltage V −0.5 to 4.6 ..
TC7WG32FC ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTNote 4: Mounted on an FR4 board. Start of commercia ..
TC514410ASJ-60
60 ns, 4-bit generation dynamic RAM
1,048,576 WORD x 4 BIT DYNAMIC RAM
DESCRIPTION
This is advanced information and speeifica-
tions are subject to change without notice.
The TCSI4410AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 1,048,576 words by 4
bits. The TC514410AP/AJ/ASJ/AZ utilizes TOSHiBA's CMOS Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and to the system user.
Multiplexed address inputs permit the TC514410AP/AJ/ASJ/AZ to be packaged in a standard 20 pin
plastic DIP, 26/20 pin plastic SOJ(300/350mi1) and 20 pin plastic ZIP. The package size provides high
system bit densities and is compatible with widely available automated testing and insertion
equipment. System oriented features include single power supply of 5Vi 10% tolerance. direct
interfacing capability with high performace logic families such as Schottky TTL.
FEATURES
. 1,048,576 word by 4 bit organization
I Fast access time and cycle time
TC514410APIAJ/ASJIAZ - 60
Inc 7173 Access Time 60ns
taa Column AddressAccess Time 30ns
tca: 55 Access Time 20ns
tm: Cycle Time 110ns
tpt Fast Page Mode Cycle Time 45ns
PIN NAMES
A0--A9 Address Inputs
R73 Row Address Strobe
C73 Column Address Strobe
WENTE Write Per Bit/Read/Write Input
Ut Output Enable
W1/lOl~W4/I04 Write Select/Date Input/Output
Vcc Power ( + SV)
Vss Ground
PIN CONNECTION (TOP VIEW)
Plastic DIP
WI/IOI I 1
Plastic Sth Plastic ZIP
I yillvss tsr?
Single ower supply of 51H: 10%
with a uilt-in VBB generator
Low Power
660mW MAX, Operatin
J'lc"ihT/h)fieJh''df/rAz - 60)
5.5mW MAX. Standby
Output unlatched at cycle end allows
two-dimensional chip selection
Read-Modif "Write, CA5 before RAS
refresh, RA -on1y refresh, Hidden.
refresh, Write per Bit, Fast Page
Mode and Test Mode ca ability
Allinputs and outputs L Compatible
1024 refresh eyeles/16ms
Package
TC514410AP : DIP20-P-300C
T0514410AJ : SOJ26-P-350
T0514410ASJ 2 SOJ26-P-300A
TCSI4410AZ '. ZIP20-P-400A
-fL2ti.LCpl/VGf2..t),./..l.
WIJIOI WMO? WMO3 WNIO4
O O C) O
DATA IN
DATA OUT
BUFFERS
BU'FERS
no.2 CLOCK
25 qulOl -
" Iw3/Ioa WMO3
A90 ta0tE A9 22flOt
A(hlli ISIAB
AOU9 In
tlil WM A1010 ”IQ;
2 8 13IA6 AZIH 150At;
AN19 nus Anl12 15UAs
VchIO HIA4 V(cl13 140A4
AS ??liiii,
ATr1Abriti1
WW GENERATOR
c COLUMN
At) 0. ',ig,W, ID ozcoosa
Al aumn ?10) J Cy
A2 o- REFRESH "v'thth4'.
A3 o- CONTROLLER
A4 .JnM-
AS cr- R6FRE1§H tt '
A6 c W3 " 1 MEMORY
A3: ROW 8 m.“ ARRAY
A A a 1024 4
A9 0. tu,'#BltWfo, y, i l""
NO.1 CLOCK . .
'MCs--- mm 'Gllltdil1"
TC514410AP/AJ/ASJ/AZ-60
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage Vm - 1~7 V 1
Output Voltage Vour - 1~7 V 1
Power Supply Voltage Vcc - 1~7 V 1
Operating Temperature Topit 0~70 "C 1
Storage Temperature TSTG - 55-150 'C 1
Soldering Temperature-Time Tsocoert 260.10 °C-sec 1
Power Dissipation . PD 700 mW 1
Short Circuit Output Current 'our 50 mA I
RECOMMENDED DC OPERATING CONDITIONS (Ta = 0--70''c)
SYMBOL PARAMETER Moi. TYP. MAX. UNIT NOTES
Vcc Supply Voltage 4.5 5.0 5.5 V 2
" Input High Voltage 2.4 _"" 65 V 2
" Input Low Voltage - 1.0 - 08 V 2
TC51441 OAP/AJ/ASJ IAZ-60
DC ELECTRICAL CHARACTERISTICS (Vcc = 5V t10%, Ta = 0--70"c)
SYMBOL PARAMETER MIN. MAX. UNITS NOTES
OPERATING CURRENT 3, 4
ICC] Average Power Supply Operating Current TC5iM10AP/AMASJ/Ab60 - 120 mA
(m, 53, Address Cycling: ter-tac MIN.) 5
STANDBY CURRENT
Iccz Power Supply Standby Current - 2 mA
(RAS =CAG = Ihr0
R-AT ONLY REFRESH CURRENT
lcca Average Power Supply Current, CUTS" Only Mode TC5tMj0Ap/At/ASJtAbtr0 - 120 mA 3, 5
(m Cycling, T7G--vw tstc--tac MIN.)
FAST PAGE MODE CURRENT
Average Power Supply Current, Fast Page Mode TCSiMtt7AptAItASJV60 - 70 mA
'(ca (W=V.L, E73, Address Cycling: tpc=tpc MIN.) 5
STANDBY CURRENT
lccs Power Supply Standby Current - 1 mA
(‘RTS = ttTG = Vcc - 0.2V)
c-NS'" BEFORE m REFRESH CURRENT
'cce Average Power Supply Current, Ch-s Before EAT TCs1o10Ap0u/ASltAF60 - 120 mA 3, 5
Modeti0G, CAT Cycling: tRc--.tec MIN.)
INPUT LEAKAGE CURRENT
h C) Input Leakage Current, any input - 10 10 pA
(OVEVWS. 6.5V, All Other Pins not under Test=OV)
l OUTPUT LEAKAGE CURRENT 10 10 A
o W) (Dow is disabled, ovsvoms 5.5V) - p
OUTPUT LEVEL
V 2.4 - V
OH Output "H'' Level Voltage0our= -5mA)
OUTPUT LEVEL
Output "L" Level Voltage(lour=4.2mA)
TC51441 OAP/AJ /ASJ IAZ-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Va: SV , 10%, Ta = 0--70oc) (Notes 6, 7, 8)
TC514410APIAJ/ASJ/AZ-60
SYMBOL PARAMETER UNtT NOTES
MIN, MAX.
titC Random Read or Write Cycle Time 110 - ns
tmw Read-Modify-Write Cycle Time 165 - ns
tpt Fast Page Mode Cycle Time 45 - ns
Ipmw 2::iepi'ignieM0de Read-Modify-Write 100 - ns
tnAc Access Time from TOG - 60 ns '),"
tCAc Access Time from C73 - 20 ns 9,14
taa Access Time from Column Address - 30 ns 9,15
[CPA Access Time from th3 Precharge - 40 ns 9
(CLZ tTG to output in Low-Z 0 - ns 9
torr Output Buffer Turn-off Delay 0 20 ns 10
tr Transition Time(Rise and Fall) 3 50 ns 8
tap m Precharge Time 40 - ns
IRAS TOG Pulse Width 60 10,000 ns
IRA” m Pulse Width(Fast Page Mode) 60 200,000 ns
tasu m Hold Time 20 - ns
113 Hold Time From tas Precharge
tRHCP (Fast Page Mode) 40 - ns
ICSH CNf; Hold Time 60 - ns
tou W Pulse Width 20 10,000 ns'
taco W5 to tTM Delay Time 20 40 ns 14
limo m to Column Address Delay Time 15 30 ns 15
too m to R753 Precharge Time 5 - ns
tcp m Precharge Time 10 - ns
tase Row Address Set-Up Time 0 - ns
tRAH Row Address Hold Time 10 - ns
tasc Column Address Set-Up Time 0 - ns
ICAH Column Address Hold Time 15 - ns
tam. Column Address to TOG Lead Time 30 - ns
tgcs Read Command Set-Up Time 0 - ns
tgc... Read Command Hold Time 0 - ns 11
TC51 441 OAP/AJ /ASJ /AZ-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Continued)
TC514410APIAJIASJIAZ-60
SYMBOL PARAMETER UNITS NOTES
MIN. MAX.
t Read Command Hold Time referenced 0 ns 11
MH to m
twm Write Command Hold Time 10 1 ns
twp Write Command Pulse Width 10 - ns
IRWL Write Command to TAT Lead Time 20 - ns
ICWL Write Command to m Lead Time 20 - ns
to; Data Set-Up Time 0 - ns 12
‘on Data Hold Time 15 - ns 12
m2; Refresh Period - 16 ms
twcs Write Command Set-UP Time 0 - ns 13
RM) m to m Delay Time 50 - ns 13
tawp 'TAT to INT Delay Time 90 - ns 13 z
tnwo Column Address to WE Delay Time 60 - ns I3
tcpwo CE Precharge to WRITE Delay Time 70 - ns 13
CAT Set-Up Time
tcse 5 - ns
(HS before R73 Cycle)
673 Hold Time
tcro -._ -_ IS - ns
(CAS before RAS Cycle) .
[Rpc RUE to m Precharge Time 0 - ns
i5G Precharge Time
tcet - 30 - ns
(ITN! before m Counter Test Cycle)
lac“ R715 Hold Time referenced to Ut 10 - ns
ton 675 Access Time - 20 ns
toto TR m Data Delay 20 - ns
t Output buffer turn off Delay Time 0 20
on from TE
tow a Command Hold Time 20 - ns
twin Write Per Bit Set-Up Time 0 - ns
\wau Write Per Bit Hold Time 10 - ns
twos Write Per Bit Selection Set-Up Time 0 - ns
ton Write Per Bit Selection Hold Time 10 - ns
TC514410AP/AJ/ASJ/AZ-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Continued)
TC5 1 44 I OAP/AJIASJ/AZ-GO
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
twrs Write Command Set-up Time 10 - ns
twm Write Command Hold Width 10 - ns
twe W? to m Precharge Time 10 - ns
twg” WT to m Hold Time It) - ns
TC51441 OAP/AJ/ASJ /AZ-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE
TEST MODE Mx = 5V i10%, Ta = 0~70°C) (Notes 6, 7, 8)
TC514410APIAJ/ASJ/AZ-50
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
tac Random Read or Write Cycle Time 115 - ns
tpc Fast Page Mode Cycle Time 50 ... ns
teat Access Time from EN; - 65 ns 'd'
ICAC Access Time from -diiT - " ns 9,14
1AA Access Time from Column Address - 35 ns 9,15
mm Access Time from m Precharge - 45 ns 9
teas MS Pulse Width 65 10,000 ns
IRAsp CAT Pulse Width(Fast Page Mode) 65 200,000 ns
1am Ers" Hold Time 25 - ns
tcsu CTG Hold Time 65 - ns
tRHcp t7G Precharge to RTS Hold Time 45 - ns
tcas CAT Pulse Width 25 10,000 ns
tear Column Address to R-AG Lead Time 35 - ns
CAPACITANCE (Vcc = 5V i10%, f =1MHZ, Ta p."..- 0--70''c)
SYMBOL PARAMETER MIN. MAX. UNIT
th, Input CapacitancetA0~A9) - 5 pF
CR Input capacitancetrOG, m, mm, Ut) - 7 pF
Co Input/Output Capacitance(W1/I01~W4/l04) - 7 pF
TC51441 OAP/AJ/ASJ IAZ-60
NOTES:
9’5"???“
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
All voltages are referenced to Vss.
Itm, Icca. Icc4, Iccs depend on cycle rate.
Iccl. Icc4 depend on output loading. Specified values are obtained with the output open.
Column address can be changed once or less while mam and CKS=vm.
An initial pause of 200ps is required after power-up followed by 8 RTE only refresh before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 ms
before EAS refresh cycles instead of 8 m refresh cycles are required.
AC measurements assume tT=5ns.
1% (min,) and V11, (max.) are reference levels for measuring timing of input signals. Also,
transition times are measured between Vm and Irs.
Measured with a load equivalent to 2 TIT, loads and 100pl?.
topp(max.)nnd defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
Either tncn or tmm must be satisfied for a read cycle.
These parameters are referenced to t5M leading edge in early write cycles and to WRITE leading
edge in Read~Write cycles.
twcs, tnwn, town, tAWD and tCPWD are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If twcsiitewcs(min.), the cycle is an early
write cycle and the data out pin will remain open circuit (high impedanee)thrroughout the entire
cycle; If titwocatRwo(min'.), towng tcwD(min,), thwniittAwD(tnin.) and tcPwDri?-etcPwo(min0
(Fast Page Mode), the cycle is a Read-Write cycle and the data out will contain data read from the
selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out(at
access time) is indeterminate.
Operation within the tRCD (max.)limit insures that tRAC (max) can be met.
titcD(rnax.)is specified as a reference point only: If taco is greater than the specified tncMmax.)
limit, then access time is controlled by tCAc-
Operation within the tRAD (max.) limit insures that tRAC (max.) can be met.
tRAD (max.) is specified as a reference point only: If tum) is greater than the specified tlmmmax.)
limit, then access time is controlled by tAA.
TC514410AP/AJ/ASJ/AZ-60
READ CYCLE
WIIIOI~
WdllOll
COLUMN
DATA - OUT
INN---"ll" or "L'' gig
WRITE CYCLE (EARLY WRITE)
WUIOI~
W4/l04
COLUMN
- MASK
Vw, __ // DATA-IN DATA-IN
l)OUTraOPliN ET. "H" or "L"
TC514410AP/AJ/ASJ/AZ-60
WRITE CYCLE (GIT: CONTROLLED WRITE)
A0-A9 IH COLUMN
WE/WE tH
W1/101~ Vm
W4/IO4 " DATA-IN
Note: DOUT=OPEN gh : "H" or "L"
READ - MODIFY - WRITE CYCLE
Ti7ig tH
a: (l"
A0-A9 IH COLUMN
tit? tH
('i" DATA-IN
WI/lol-- IL
TC51 441 OAP/AJ IASJ IAZ-60
FAST PAGE MODE READ CYCLE
ri7G "
A0-A9 VT
wa/wE VT
_ - VIH
w1/101 - Von
wanoa VOL
Note: Dmr="li"m"'l/' Eg.. "H'' or "L"
FAST PAGE MODE WRITE CYCLE
Dour N
R73 VIH
A0-A9 "
W 1 HO 1 _ VIH
wano4 VIL
gg.. "H" or "L''
Note: Ihour= OPEN
TC51 441 OAP/AJ IASJ IAZ-GO
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
V RASP
Ti7G IH
A0-A9 IH
-A. - v
wans IH
tlie- IH
wmoz~ OH
wanoa VOL WOH tc
Vm MASK
VIL DATA-IN
E% ONLY REFRESH CYCLE
VIH - 5
m " --- tm N, tm r/l,,,,,
m sl/C.'"...'..:.....-,,?' tAStt mar, "cy"
AtH-A9 C'y--'1iiiiiiiiiiiiiig new 1tgiiiititEitEEEiiiEElti)
Note: WRITE, UE=“II" or "L"
TC51441 OAP/AJ /ASJ/AZ-60
wa BEFORE KES REFRESH CYCLE
4 tttrr -te.-.,
- . teat }
" - 4 a
" -......_Y/ N,
V 1tau, _ tCHR 7
MR? twrm
ih7ri/WE 31‘ C(//iifiiiggE ';iCi'iiji'iiij"ji'jii'j,
wmo1~ VOW“ N OPEN
INM04 I/cw - /
Note: Deo 6f. AO-M.-.. "H" or "L''
ET. "H'' or "L''
TC514410AP/AJ/ASJ/AZ-60
HIDDEN REFRESH CYCLE (READ)
Ihr, ..-..-. ,
7/: tttp \4:4?H\_
m :1: .-r..,..yl)c''-' tm\\§ ti1sH.., "tcry---?-''---'--------
sir/i-urs/Cyl-iii)','?;'; , (" pe iiias/ W
CAC t FF
3:; ' «mg
Vor, - -F"
W J101 --l--- DATA- OUT
W4/l04 VOL - k
gg; ." "H" or "L"
T051441 OAP/AJ/ASJ IAZ-BO
HIDDEN REEFRESH CYCLE WRITE
Ttwi' :1: --L-""'""'"-"'1, .2: su-tis,.,.---)' 'ic....,
ttTG :1: -c,,../" -r.t:t:i:s:i-, "tsf r J/
AAAAA ::: wMW ////////////%<
WlyihTE" :1: cagigigiiiiir"s'' - iiizzzzis,i,ii,
t5E- 5::7//////////////////////////////////////////////////////////%
C,1v10d, :1: " >6 DAT], 'iassiisiiiiiiiiiiiii,i,iiii,iiiiai.iiiiiiii.siiiiiiiaiiiis
Eil.."" H" or "L"
T051 441 OAP/AJ/ASJ IAZ-60
CA3 BEFORE RES REFRESH COUNTER TEST CYCLE
READCYCL
_--.',"-)'-.']-"."---,";]-)"-""--, "sr'-'-''--'-; tRas fix
lv":]''-']."),',''';':'',":''';;))'','')''" "tiiii'ii'ii'i'i"iti'i's'iiii'' 'ttiii
"Cr..] "ict-os-e- / to,r"ziositi
C.'] twcs "Ist,,, 'i', toEt H?—
iwvErr--ji,i,,,ii,jiis?)r'"'''z'-- 'irirtsiitiiiiiisiif fost ,- /////l//{////////////
XI:%////////////////////////////////////////////////////Z
TC514410AP/AJ/ASJ/AZ-60
WE. GAS BEFORE RAE REFRESH CYCLE
-. In?
- VIH - a S a
m N, N
" - -N
V ' csa tcun ,éj
IH - -
ER? gjf,iji,
Vic -e.- T //L
lava twrH
m ft' CyEiiiiE'iEiih gt'ii;, f;iiiifi''iii'j,i'jji'i, ')fff,
wmm~ I/OH----' OPEN
wanoa Voc -
Note: 0m. TR, AO-Ar-. "H" or "L"
Eg.. "H" or "L"
TC51 441 OAP/AJ IASJ /AZ-60
APPLICATION INFORMATION
ADDRESSING
The 20 address bits required to decode 1 of the 1,048,576 cell locations within the
Tc51410AP/AJ/ASJ/AZ are multiplexed onto the 10 address inputs and latched into the on-chip address
latches by externally applying two negative going 'ITL-level clocks.
The first clock, the Row Address Strobe@%, latches the 10 row address bits into the chip. The
second clock, the Column Address Strobetm), subsequently latches the 10 column address bits into
the chip. Each of these signals, RES, and CM, triggers a sequence of events which are controlled by
different delayed internal clocks.
The two' clock chains are linked together logically in such a way that the address multiplexing
operation is done outside of the critical path timing sequence for read data access. The later events in
the Chg clock sequence are inhibited until the occurrence of a delayed signal derived from the EM
clock chain. The "gated CKS" feature allows the CKS clock to be externally activated as soon as the
Row Address Hold Time specifieation(trtAn) has been satisfied and the address inputs have been
changed from Row address to Column address informatidn.
DATA INPUTS
A write cycle is performed by bringing(WMWE low during the RAS/UM operation. The falling
edge of UKS or iWIf/)WlT Strobes data on (Wi)10i into the on-chip data latch. To make use of the
write-per-bit capability WWWE)must be low as -I7S falls. In this case data bits to which the write
operation is applied can be speeirled by keeping Wi(/10i) high with set-up and hold times referenced to
the m negative transition. For those data bits of Wi (/IOi) that are kept low as rag tells the write
operation is inhibited on the chip if WOW) is high as tTM falls, the write-per-bit capability does not
work and the write operation is performed for all four data bits.
DATA OUTPUTS
The three-state output buffers provide direct 'ITL compatibility with a fan-out of two standard TIT,
loads. Data-out is the same polarity as data-in. The outputs are in the high-impedance state until Ch-s-
is brpught low. In a read cycle the outputs go active after the access time interval tnAc and tOEA are
satisfied.
The outputs become valied after the access time has elapsed and remains valied while TWSI and W
are low. (ES or E going high returns it to a high impedance stare. In an early-write cycle, the
outputs are always in the high-impedance state. In a delayed-write or read-modify-write cycle, the
outputs will follow the sequence for the read cycle.
The UE controls the impedance of the output buffers. In the logic high position the buffers will
remain in a high impedance state.
When the CE input is brought to a logical low level, the output buffer are enabled. Both (KS and
15E can control the output. Thus in a read operation, either at" or tWif returning high forces the
outputs into the high impedance state.
TC51 441 OAP/AJ IASJ/AZ-60
"il/Ts ONLY REFRESH
Refresh of the dynamic cell matrix is accomplished by performing a memory cycle at each of the 512
row address(A0--A9) within each 16 millisecond time interval.
Although any normal memory cycle will perform the refresh operation, this function is most easily
accomplished with "RM-only" cycles.
E‘A-s BEFORE FITS REFRESH
Uh-s before -IITG refreshing available on the TC514410AP/AJ/ASJ/AZ offers an alternate refresh
method. If CATS is held on low for the specified period(tcsn)before m goes to low, on chip refresh
control clock generators and the refresh address counter are enabled, and an internal refresh operation
takes place. After the refresh operation is performed, the refresh address counter is automatically
incremented in preparation for the next Ch-s before -ItttS refresh operation.
PAGE MODE
The "Page-Mode" feature of the TC514410AP/AJ/ASJ/M allows for successive memory operations at
multiple column locations of the same row address with increased speed without an increase in power.
This is done by strobing the row address into the chip and maintaining the m signal at a logic 0
throughout all successive memory cycles in which the row address is common. This "Page-Mode" of
operation will not dissipate the power associated with the negative going edge of' RAS. Also, the time
required for strobing in a new address is eliminated, thereby decreasing the access and cycle times.
HIDDEN REFRESH
An optional feature of the TC514410AP/AJ/AN/AZ is that refresh cycles may be performed while
maintaining valid data at the output pid. This is referred to as Hidden Refresh. Hidden Refresh is
performed by holding tTEll at Vu, and taking rag high and after a specified precharge period (tap),
executing a Cie before m refresh cycle. (see Figure below)
MEMORY CYCLE REFRESH CYCLE REFRESH-CYCLE
'f -L_,.,.,_,/"''-"L.._._.,/'"-"l /
- """"'"'-N, f'""""''''-"""""''"'"'''"""'"""
w11101~w4/104_‘ OPEN ----l VALID DATA-OUT )-
This feature allows a refresh cycle to be "Hidden" among data cycles without affecting the data
availability.
TC51 441 OAP/AJ/ASJ IAZ-60
T7G BEFORE TOG REFRESH COUNTER TEST
The internal refresh _operation of TC514410AP/AJ/ASJ/AZ can be tested by tW? BEFORE ITEg
REFRESH COUNTER TEST. This cycle performs READ/WRITE operation taking the internal counter
address as row address and the input address as column address.
The test is performed after a minimum of 8 UK before TtTig cycles as initialization cycles. The test
procedure is as follows.
co Write "O" into all the memory cells at normal write mode.
© Select one certain column address and read "o" out and write "I" in each cell by performing tTM
BEFORE m REFRESH COUNTER TEST (READ-WRITE CYCLE). Repeat this operation 512
times.
© Check "I'' out of 512 bits at normal read mode, which was written at CO,
© Using the same column as co, read "I" out and write "O" in each cell performing tsig BEFORE
m REFRESH COUNTER TEST. Repeat this operation 512 times.
© Check "O" out of 512 bits at normal read mode, which was written at co.
© Perform the above CD to © to the complement date.
TEST MODE
The TC614410AP/AJ/ASJ/AZ is the RAM organized 1,048,576 words by 4 bits, it is internally
organized 524,288 words by 8 bits. In "Test Mode", data are written into 8 sectors in parallel and
retrieved the same way. A00 is not used. If, upon reading, two bits on one I/O pin are equal (all "1"s
or "0"s), the I/O pin indicates a "I''. If they were not equal, the I/O pin would indicate a "O". Fig. 1
shows the block diagram of TC514410J/Z. In "Test Mode", the 1MX4 DRAM can be tested as if it were
a 512KX4 DRAM.
"WE, m Before -rm5 Refresh Cycle" puts the device into "Test Mode", And “TS Before m
Refresh Cycle" or “m Only Refresh Cycle" puts it back into "Normal Mode". In the Test Mode, “WE,
CM Before m Refresh Cycle" performs the refresh operation with the internal refresh address
counter. The "Test Mode" function reduces test times (1/2 in case of N test pattern).
T051 441 OAP/AJ /ASJ/AZ-60
BLOCK DIAGRAM INTHE TEST MODE
-----------Q
A -------o Normal
oc A ' "
Normal "N-u? s I 2K block - l C2:x :Test
vol o of A A 1t01
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c--------------,
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A ------Q ly Normal
oc C ear-----]
Normal _ 512K block - o-) Test
l/02 -osc, -TCT c i/02
Test 01cc D
512K block - ', Ey-----------):
D r \°_l
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c----------"
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A ------© y Normal
oc E o----]
---o-u7-
Normal . 512K block - 4 I D:'----------',:";
nos ”No; 7(2'"i" E 1/03
Test c F
(Ch-C)
512K block - 3 C:----------;':
F I "so-----!
-------o iNormaI
. _ ot.oc
A --------0 Normal
0C G ecs-1
----->-uh- ' I yr---------;
Normal . 512K block - 4 Test
I/04 --oso -AT,T G "04
Test Og__ H
s12KbIock - l CD)---------)'?.
H ' "xr-H
------o iNormal
Fig. 1
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