TC514402AZ-60 ,60 ns, 4-bit generation dynamic RAMfeatures include single power supply of 5Vi10% tolerance,
the TC514402AP/AJ/ASJ/AT to be package ..
TC514402AZ-70 ,70 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576
word by 4 bit organization
. Fast access time and cycle time
TC51440 ..
TC514402AZ-80 ,80 ns, 4-bit generation dynamic RAMBLOCK DIAGRAM
WMO1 WMO2 WMOJ WUIOI
O O 0 C)
COLUMN
DECODEI
SENSE AMP.
IIO GATE
MEMORY
..
TC514410ASJ-60 ,60 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization
I Fast access time and cycle time
. Single
..
TC514410AZ-80 ,80 ns, 4-bit generation dynamic RAMABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING NOTES
input Voltage Vm
Output Voltage Vout
Power ..
TC514800AJLL-70 , 524288 WORD X 8 BIT DYNAMIC RAM
TC7WG125FK ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTStart of commercial production 2006-021 2014-03-01 ..
TC7WG126FC , CMOS Digital Integrated Circuit Silicon Monolithic Dual Bus Buffer with 3-STATE Output
TC7WG126FK ,L-MOS LVP seriesabsolute maximum ratings. OUTStart of commercial productionNote 3: V < GND OUT2006-021 2014-03-01 T ..
TC7WG14FC ,L-MOS LVP seriesabsolute maximum ratings. OUT1A 3Y 2A GNDNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 ..
TC7WG14FU ,L-MOS LVP seriesAbsolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating UnitSupply voltage V −0.5 to 4. ..
TC7WG17FK ,L-MOS LVP seriesabsolute maximum ratings. OUT Start of commercial production2006-02Note 3: V < GND OUT1 2014-03-01 ..
TC514402AZ-60
60 ns, 4-bit generation dynamic RAM
$048,576 WORL? x 4 BIT DYNAMK RAM *
L)..ef.iffufdI.lf2iy
This is advanced information and specifica-
tions are subject to change without notice.
The TC514402AP/AJ/ASJ/AT is the new generation dynamic RAM organized 1,048,576 words by 4
him. The TC514402AP/AJ/ASJ/AZ utilizes TOSHIBA's CMOS Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and to the system user.
Multiplexed address inputs permit the TC514402AP/AJ/ASJ/AZ to be packaged in a standard 20 pin
plastic DIP, 26/20 pin plastic SOJ (300/350mil)and 20 pin plastic ZIP, The package size provides high
system bit densities and is compatible with widely available automated testing and insertion
equipment. System oriented features include single power supply of 5V:t10% tolerance, direct
interfacing capability with high performace logic families such as Schottky ITL.
EE_ALU R. ES
0 1,048,576 word by 4 bit organization
0 Fast access time and cycle time
TC5l4402AP/AJ/ASj/ AZ - 60
tang F56 Access Time 60ns
taa Caiumn AddressAccess Time 30ns
10m ts Access Time 20m
IRC Cycle Time 110ns
ts: Static Column Mode 35
che Time tsns
Elm NAMES
A0--A9 Address Inputs TR Output Enable
'OT-s Row Address Strobe IlO1~I104 Data mput/Output
(3 Chip Select Vcc Power ( ' 5V)
WW/r-E- iliead/Write Input Vss Ground
PIN CONNECTION (TOP VIEW)
Plastic DIP Plastxc so:
_._._._.‘g ugh“..-
Plan": ZIP
Vcc __-_
. Single ower supply of 5ViIO%
with a uilt-in V138 generator
o Low Power
660mW MAX. Operating
(TC514402AP/AJ/AS IAZ-BO)
5.5mW MAX. Standby
0 Output unlatched at cycle end allows
two-dimensional chip selection
I Read-Modif -Write. CS before RES
refresh, RA -oni ' refresh, Hidden
refresh, Static C‘Iolumn Mode and
Test Mode ca ability
Allinputs an ourputsTN, Compatible
1024 refresh cyeles/16ms
Package
TC514402AP :DIP20-P-300C
TC514402AJ ..S0J26-P-350
TC514402ASJ :SOJ26-P-300A
TC514402AZ :ZIP20-P-400A
BLOCK DIAGRAM
|/01 A32 V03 U04
C) o O Ct
DATA IN DATA OUT
BUFFERS J BUFFERS
no.2 CLOCK
er o--- GENERATOR I
k-------
c UM COLUMN
A00» 1fb)(thl1 as) oscooen
Al 0+ BUFF R 101
SENSE AMP,
A? CF- co1Wl8cG PO GATE
A4 w- Hh'-
A50. ':'d"l%
A60> C 1'3,“ , MEMORY
A7 o- Row ty I ARRAY
“80’ A? R , fro." 1024x1024
A90, BU F R 'A' l xl
O NONI CLOCK
W GENERATOR
SUBSTRATE BIAS
GENERATOR
TC51 4402AP/AJ IASJ IAZ-BO
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage Vm - _ V 1
Output Voltage Vour - 1~7 V 1
Power Supply Voltage vcr - _ v 1
Operating Temperature TopR 0-70 "C 1
Storage Temperature Tsm - SS~ 1 50 T 1
Soldering Temperature .Time Tsomza 260. 10 'C . set 1
Power Dissipation P0 700 mW 1
Short Circuit Output Current “om 50 mA 1
RECOMMENDED DC OPERATING CONDlTlONS(Ta=0-70"c)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES
Vct Supply Voltage l 4.5 5.0 5.5 V 2
" Input High Voltage 2.4 - 6.5 V 2
" Input Low Voltage - 1.0 - 0.8 V 2
TC51 4402AP/AJ /ASJ /AZ-60
DC ELECTRICAL CHARACTERISTICS (Vcc = 5V , 10%, Ta = 0--7ty'c)
SYMBOL
PARAMETER
MIN. UNITS
OPERATING CURRENT
Average Power Supply Operating Current
FTS, ts, Address Cycling: titC=tRC MIN.)
TC51Mtl2AWAJ/AWAb60 - 120 mA
STANDBY CURRENT
Power Supply Standby Current
(m = a = VIH)
WE ONLY REFRESH CURRENT
Average Power Supply Current, 'TIG Only Mode
tk-AT Cycling, tT=Vw. tru:=te MIN.)
TCS 1 M02Af'tAJ/ASJ/Ar60 - 120 mA
STATIC COLUMN MODE CURRENT
Average Power Supply Current, STATIC COLUMN
Mode (ri7iT=eT--uc, Address Cycling: tsc=tsc MIN.)
TC51 4402AP/AJ/ASJIAZ-60 - 95 mA
STANDBY CURRENT
Power Supply Standby Current
(RTS = 6 = Vcc - 0.2V)
E; BEFORE TNT REFRESH CURRENT
Average Power Supply Current, tTr Before "iT/iT
Made00G, ts Cycling: tnc=lRC MIN.)
TCS1MO2AP/AJIASJ/AZ-60 - 120 mA 3, 5
INPUT LEAKAGE CURRENT
Input Leakage Current. any input
(OWS, V.NS GVSV, All Other Pins Not Under Test', 0V)
-10 10
io (L)
OUTPUT LEAKAGE CURRENT
(DOUT IS disabled, 0VSVourS 5.5V)
-10 10
OUTPUT LEVEL
Output "H" Level Voltagerm = - SmA)
2.4 - V
OUTPUT LEVEL
Output "L" Level Voltage(IOUT=4.2mA)
TC51 4402AP/AJ /AS0/AZ-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc=5Vi10%, Ta=0--70oc)(Notes 6, 7, 8)
TC514402APIAJIASJIAZ-60
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
tRc Random Read or Write Cycle Time 110 ... ns
tmw Read-Modify-Write Cycle Time 165 - n5
tsc Static Column Mode Cycle Time 35 - ns
tsmw 21.311: folumn Mode Read-Modify-Write 90 - ns
ycle Time
tmc Access Time from WATS - 60 ns 'ii,'
tCAC Access Time from C? - 20 ns 9,14
tAA Access Time from Column Address - 30 ns 9,15
bury Access Time from Cast Write - S5 ns 9.16
10.2 S to output in Lowa - t) - ns 9
ton Output Buffer Turn-off Delay 0 20 ns 10
‘AOH Output Data Hold Time from Column 5 - ns
Addres
tow Output Data Enable Time from MIT - 20 ns
t7 Transition Time(Rise and Fall) 3 50 ns 8
tap TAS" Precharge Time 40 - ns
tRAS m Pulse Width 60 10,000 n5
tRASC vs Pulse Width(Static Column Mode) 60 200,000 ns
tag” i3 to m Hold Time 20 - ns
tcsu m to i3 Hold Time 60 - ns
tcs 3 Pulse Width 20 10.000 ns
tcsc CT Pulse Width(Static Column Mode) 20 200,000 ns
taco TtTG to E? Delay Time 20 40 ns 14
1mm TOG to Column Address Delay Time 15 30 ns 15
tco E to WATS Precharge Time 5 - ns
tty, 3 Precharge Time 10 - n5
' tAsa Row Address Set-Up Time 0 - ns
tam; Row Address Hold Time 10 - ns
tasc Column Address Set-Up Time 0 - ns
tom Column Address Hold Time 15 - ns
tAit COIET Address Hold Time referenced 70 - ns
to RAS (READ CYCLE)
1am Column Address to FWS' Lead Time 30 - ns
tAH cole', Address Hold Time referenced 5 - , ns 17
to RAS Rise [
TC51 4402AP/AJ IASJ IAZ-60
TCSt4402AWAl/Au/Ab60
SYMBOL PARAMETER UNITS NOTES
MIN. MAX.
L st Write to Col mn Address Dela
tcvous , t u y 20 25 ns 16
Last Write to Column Address Hold
tAHLw . 55 - ns
Read Command Set-up fime referenced
tecs - O - ns
Read Command Hold Time referenced
IRCH 0 - ns 11
Read Command Hold Time referenced
1mm --- 0 - ns 11
to RAS
Write Command Hold Time
two, (Output Data Disable) 10 - ns 13
tum Write Command Pulse Width 10 - ns
tw, Write Command Inactive Time 10 - ns
1mm Write Command to TOG Lead Time 20 - ns
tCWL Write Command to tS Lead Time 20 - ns
tos Oata-In Set-Up Time 0 - ns 12
tor, Data-In Hold Time 15 - ns 12
(REF Refresh Period - 16 ms
t Write Command Set-UP Time t) ns 13
wo (Output Data Disable)
t? to W_R_ITE Delay Time I
t - n 13
CWD (READ-MODIFY-WRITE CYCLE) 50 '
IigTs- to WRITE Delay Time
t 90 - ns 13
RWD (READ-MODIFY-WRITE Cycle)
tAwo Column Address to WRITE Delay Time 60 - ns 13
lcsn Cs Set-Up Time(f§ before RE) 5 - ns
104R (3 Hold Timefi before m) 15 - ns
IRPC AVG to E: Precharge Time 0 - ns
C? Precharge Timed? before EAT
tcpr 30 - ns
Counter Test Cycle)
tROH R76 Hold Time referenced to tre 10 - ns
ttwa tit' Access Time - 20 n5
1.050 ITE- to Data Delay 20 - ns
Output Buffer turn off Delay Time
1051 -- 0 20 ns 10
from OE
tom 5? Command Hold Time 20 - ns
TC51 4402AP/AJ IASJ /AZ-60
TC5 M402APIAJ/ASJ/AZ-60
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
twrs Write Command Set-Up Time 10 - ns
twr" . Write Command Hold Time 10 - ns
tvow WRTTE to m Pretharge Time IO - n3
twnn WRITE to RAS Hold Time 10 - ns
TC51 4402AP/AJ IASJ/AZ-BO
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE
TEST b/_1QLLiiiVcc=51/t10%, Ta=0~70°c)(Notes 6, 7, 8)
TC514402AP/Al/ASJtAb60
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
Inc Random Read or Write Cycle Time 115 - ns
tsc Static Column Mode Cycle Time 40 - ns
tRAc Access Time from tS - 65 ns 91':
tcnc Access Time from ts ... 25 ns 9,14
taa Access Time from Column Address - 35 ns 9,15
mm FAT Pulse Width 65 10,000 as
(MS: T/G Pulse Width(5tatic Column Mode) 65 200,000 ns
lag" TOG Hold Time 25 - ns
tcw cs Hold Time 65 - ns
tcs 3 Pulse Width 25 10,000 ns
tcsc ES Pulse Width (Static Column Mode) 25 200,000 ns
tstat Column Address to EhT Lead Time 35 - ns
CAPACITANCE (Vcc = 5V , 10%, f =1MHZ, Ta = 0--70''c)
SYMBOL PARAMETER MIN. MAX. UNIT
Cu Input Capatitance(A0-A9) - S pF
Ca Input CapacitanceirtTG, TS, WRITE, CT) - 7 pF
Co Input/Output Capacitance(l/O1~l/04) - 7 pF
TC51 4402AP/AJ/ASJ/AZ-60
NOTES:
9F"???
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
All voltages are referenced to Vss.
I001, 1003. ICC4, ICCS depend on cycle rate.
1001. ICC4 depend on output loading. Specified values ate obtained with the output open.
Column address can be changed once or less while m: Vu,.
An initial pause of 200ps is required after power-up followed by 8 TM only refresh cycles before
proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 Cg
before RAE. refresh cycles instead of 8 It7g refresh cycles are required.
AC measurements assume tT=5ns.
Vm (min.) and Vii, (max.) are reference levels for measuring timing of input signals.
Measured with a load equivalent to 2 TTL loads and IQOpF.
toFF(max.) and toEztmax.)define the time at which the output achieves the open circuit condition
and arealot referenced to output voltage levels.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to ES leading edge in early write cycles and to WRITE leading
edge in Read-Modify-Write cycles.
twcs, tRWD, town and tAWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If tWcsLetWcs(rnin.), the cycle is an early write cycle
and the data out pin will remain open circuit(high impedance) through the entire cycle; If
tawogtnwp (min.), tcwpgtcwn (min.) and tAngtAWD (min.) the cycle is a Read-Modify-Write
cycle and the data out will contain data read from the selected cell: If neither of the above sets of
conditions is satisfied, the condition of the data out (at access time) is indeterminate.
Operation within the titcro(max.)1imit insures that time (max.) can be met.
tRCD(max.)is specified as a reference point only: If men is greater than the specified tncn(max.)
limit, then access time is controlled by tCAC.
Operation within the tRAD (max.) limit insures that tnAc(max.)can be met.
tRAD (max.) is speeimsd as a reference point only: If tRAD is greater than the specified tRAD(max.)
limit, then access time is controlled by tAA.
Operation within the tLWAD(max.)limit insures that tALw (max.) can 'be met.
tLWADhnax.) is specified as a reference point only: If tRAD is greater than the specified tLWAD
(max.) limit, then access time is controlled by tAA.
tAH is the condition to latch column address ewhen RAE has rised up.
TC51 4402AP/AJ IASJ /AZ-60
READ CYCLE
COLUMN
toez F
l/Ol~|/04 OH -....l-l.-..l.-_ DATA - OUT
WRITE CYCLE (EARLY WRITE)
-- " -
VIL ---
Ihr, ---
1ASR 14?fo tasc ICAH
A0--A9 " Il'- /////,
COLUMN
----- VIH ---- t
'e-um-d L-to,,-,
. v, - - -
”014/04 IH ------------? DATA-IN E OPEN
VIL - - -
ET. "H" or "L"
TC51 4402AP/AJ IASJ/AZ-60
WRITE CYCLE(UE CONTROLLED WRITE)
A0~A9 COLUM N
uo1~v04 IH DATA _ IN
READ - MODIFY - WRITE CYCLE
v - f'
VO1~I/04 tlt9Ft DATA-IN "/// //
_:'iCfs,s'Ci: : "H'' or "L"
TC51 4402AP/AJ IASJ IAZ-BO
STATIC COLUMN MODE READ CYCLE
Ath-A9
I/ol-l/Oil 0”
Ea,. "H'' ctr "L''
TC51 4402AP/AJ IASJ /AZ-60
STATIC COLUMN MODE WRITE CYCLE iEARLY WRITE)
I/O 1~ll04
STATIC COLUMN MODE WRITE CYCLE (EARLY WRITE)
m Ihr,
A0 A9 Vo,
tT VIH
Wrt-it-E
t5t- Vo
POI VO4 VIH
TC51 4402AP/AJ IASJ /AZ-60
STATIC COLUMN MODE READ - MODIFY - WRITE CYCLE
A0~A9 IH com
tSRMW tcan
" I _ 1/04
Er. "H" or (
TC51 4402AP/AJ/ASJ/AZ-60
STATIC COLUMN MODE READ/WRITE MIXED CYCLE
A0--A9
--__ VIH
tos ton tAOH
l/OI-l/ol
Dm1 Dour2 N DINN
(WRITE) (READ) (READ) (WRITE)
El "H" or "L"
TC51 4402AP/AJ IASJ /AZ-60
RM ONLY REFRESH CYCLE
Note: WRiTi-I, (rr',="u" or "L"
ka.. "H'' or "L"
TC51 4402AP/AJ /ASJ IAZ-GO
GS BEFORE RKS REFRESH CYCLE
wrtrtt 'v/YL'',''''''" 5
w-"-"'""'"''""""-"""]
w----.-,)
TC51 4402AP/AJ IASJ /AZ-60
HIDDEN REFRESH CYCLE (READ)
a 315:] 'te, V 6-]!
(F.A9 3;»; %r>@<9W//////////////////////////
twap twan
ws-UT-C,,'.".:',,:),)';'', i- I "iiisir a W
a ZITW ”WW
".l.l,o, I: -r-------------c-.---iiir 'oA,A-ou, 'l-y------.
‘ : 2. or"t.''
TC51 4402AP/AJ IASJ IAZ-60
HIDDEN REEFRESH CYCLE WRITE
= _ 4 ttttt ' tap
taAs _.
VIH - s
m N / N is,
" - -~____r- -
7 = titcty =-, tRSH 7 tom , - tou,
AtRAD 'tt:s
, vat H
'iii :;cow3l£<%// /////////%<
atzr-WWWW
R.', :1: IC, >6 "oA,.""','",',""" (.gttiiiiiiEiiiiiEiittttitiEiitiitiiiiil
'g4ti : "H'' or T''
TC51 4402AP/AJ IASJ /AZ-60
CS BEFORE RAS REFRESH COUNTER TEST CYCLE
__.__J t
VIH -- V ‘RAS /'z's='is,
h“; " - -h t
tcte " = 5
" I tcs
ASC 41%
0 9 COLUMN AD SS
" -'re I
READCYCLE W [ WM ‘ RCS f"
- v 0 " y
W IIIIIII tg
V i'jii'iijiii'lij, tom
trt Ffftt k 2, to 4tjfi?',
l lcu to 1
OPEN DATA- OUT Cy-
o L - k
twnp twrm ---- ttwt
WRITE CYCLE A tcm
WATrt" :1: --'i','gt; "'ii'ii'"iii'i'i'ii'ii)irc' A two, I I
ut- :2?:/
l tos tim
- M------------
l/OI- vm----- OPEN i IN is
. I/oa IG. - tch
E D-MODI - twar, t W
RITE CYCLE tcwo tam
w H WRH tacs
Ihr, -'t?'iit l .1 10 " twe 7
W? " Iiiiiiiit7 liiiitiiiiiijiei" 'st'CadiiiiiiiiiiiiiiiiiiiiiiiiE
V/A : "H" or "L"
TC51 4402AP/AJ IASJ IAZ-60
WRITE. CS BEFORE RAE REFRESH CYCLE
trp ‘CSE
VIH -- ,k'-"h
" -....-_v/' si.',
A, tap
_..."""-'"-,
l/Ot - I/O4
VOL ----...-2
Note: CE. Atr-A9= "H" or "L''
Eiil.. "H" or "L"
TC51 4402AP/AJ/ASJ/AZ-70, TC51 44o2AP/AJ/ASJ/AZ-80
TC51 4402AP/AJ/ASJ/AZ-1 o
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage " -1-7 V I
Output Voltage Vour -1--7 V 1
Power Supply Voltage Vcc -1~7 V 1
Operating Temperature Tope o-ro 'C 1
Storage Temperature Tsms - 55~150 'C 1
Soldering Temperature . Time Tsowzn 260 . 10 'C . set 1
Power Oissip"ation _ Po 700 mW t
Short Circuit Output Current tour so mA I
RECOMMENDED DC OPERATING CONDITIONS (Ta=0~70°c)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES
Vcc Supply Voltage 4.5 5.0 5.5 V 2
V.” tnput High Voltage 2.4 - 6.5 V 2
VI. Input Low Voltage - 1.0 - 0.8 V 2
TC51 4402AP/AJ /ASJ/AZ-60
BLOCK DIAGRAM IN THE TEST MODE
---------©
Ao -------Q Normal
c A "r-H
---iu7-- l Ci--------;
Normal . 512K block - o--) Test
IIO1 TC. A
Test tK i)
S12K block - I CDs---------?'?.
B r 'o---]
___.__o niNormal
----------o
-----------©
A -------0 IN ormal
CC C s " I
Normal 0‘9 512K block ' - r--) DO :Tesl
v02 “Ox - c
df Aoc D
o-o-- 512K block - 3 CD-------------;')
D 1 "st:r---1
-------o INormaI
A --------0 IN ormal
OC E xy----)
---QA----- ' I Xr-----------;
Normal . 512K block - o--) Test
1/03 -e'ut, --..-- E
Test 49:02; F
512K block - l CDs--------)]
F ' 'ts----]
------Q INormal
A ------Q IN ormal
cc G l (0-I
Normal tN-U? 512K block - r-4 Do cTest
1/04 -"'sc, - G
Test Jec, H
512K block - 5 [Ds-------------))
H ' 'xr----]
w-----------) Normal
_------------"
Fig. 1
___/i":--
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