TC514402AZ-80 ,80 ns, 4-bit generation dynamic RAMBLOCK DIAGRAM
WMO1 WMO2 WMOJ WUIOI
O O 0 C)
COLUMN
DECODEI
SENSE AMP.
IIO GATE
MEMORY
..
TC514410ASJ-60 ,60 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization
I Fast access time and cycle time
. Single
..
TC514410AZ-80 ,80 ns, 4-bit generation dynamic RAMABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING NOTES
input Voltage Vm
Output Voltage Vout
Power ..
TC514800AJLL-70 , 524288 WORD X 8 BIT DYNAMIC RAM
TC51832F-12 ,120ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAMFEATURES
. Organization: 256K bit(32,768 word x 8 bit)
. Fast Access Time and Low Power Dissipa ..
TC51832FL-10 ,100ns; V(in/out/dd): -1 to +7V; 600mW; 50mA; 32,768 word x 8-bit CMOS pseudo static RAML---.
082
_,__,J
TOSHIBA tL0GTC/hEh0RY) LIBE D " “1037343 00220]: l] -T
32,768 WORD x 8 B ..
TC7WG126FC , CMOS Digital Integrated Circuit Silicon Monolithic Dual Bus Buffer with 3-STATE Output
TC7WG126FK ,L-MOS LVP seriesabsolute maximum ratings. OUTStart of commercial productionNote 3: V < GND OUT2006-021 2014-03-01 T ..
TC7WG14FC ,L-MOS LVP seriesabsolute maximum ratings. OUT1A 3Y 2A GNDNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 ..
TC7WG14FU ,L-MOS LVP seriesAbsolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating UnitSupply voltage V −0.5 to 4. ..
TC7WG17FK ,L-MOS LVP seriesabsolute maximum ratings. OUT Start of commercial production2006-02Note 3: V < GND OUT1 2014-03-01 ..
TC7WG17FU ,L-MOS LVP seriesAbsolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating UnitSupply voltage V −0.5 to 4.6 ..
TC514402ASJ-80-TC514402AZ-70-TC514402AZ-80
100 ns, 4-bit generation dynamic RAM
1048,576 WORD x 4 BIT DYNAMIC RAM PRELIMINARY
DESCRIPTION
The TCSI4402AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 1,048,576 words by 4
bits, The TC514402AP/AJ/ASJ/AZ utilizes TOSHIBA'S CMOS Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins,"both internally and to the system user.
Multiplexed address inputs permit the TC514402AP/AJ/ASJ/AZ to be packaged in a standard 20 pin
plastic DIP, 26/20 pin plastic SOJ(300/350mi1) and 20 pin plastic ZIP. The package size provides high
system bit densities and is compatible with widely available automated testing and insertion
equipment. System oriented features include single power supply of 5V:l: 10% tolerance, direct
interfacing capability with high performace logic families such as Schottky 'ITL.
FEATURES
0 1,048,576 word by 4 bit organization 0 Single os.er.sup.ply of 5Vd:10%
0 Fast access time and cycle time Li,t,ht uilt-in VBB generator
I ow ower
TC51d402AP/A0ASllA2-70/-80/- It) 550mW MAX. Operatin
taac m Access Time 70:15 BOns 100ns f,',Ri14d)ji,Ag,eh. /AZ--70)
t C I Add A Ti 468mW MAX. peratin
AA 'dl umn T' CCeSS 'm" 35ns 40ns Sons 'f?rlvsf4ttAugl'f//1%ur..,
ttac CS Access Time 20ns 20m 25nt 413mW MAX. Operatin
te Cycle Time 130ns 150ns 180ns 'lr?lJslv41tl'liA'i'vi1%W/Az-.io,
tsc Static Column Mode 5.5mW MAX. Standby
Cycle Time Mns 45ns 55ns q Output unlatched at cycle end allows
two-dimensional chip selection
. Read-Modif -Write, cg before mrg
PIN NAMES refresh, -on1 refresh, Hidden
refresh, Static olumn Mode and
A0-A9 Address Inputs Ut Output Enable 1t1 Mode ca ability TIT, C b1
- . inputs an outputs ompati e
T,' Row Address Strobe 1/01 I/O4 Data Input/Output . 1024 refresh cyeles/16ms
Chip Select Vcc Power(+5v) . Package
WRITE ReadNVritelnput vss Ground TC514402AP : DrP20-P-300C
T0514402AJ :SOJ26-P-350
TC514402ASJ ..SGr26-P-300A
PIN CONNECTION(TOP VIEW) TC514402AZ ..ap20-P-400A
BLOCK DIAGRAM
Plastic DIP Plank SOI Plastic Ill' W130! wgoz 'W" wane:
51,123 Ci' IS Vcc Vs}
It03 .:: A uoa DATA m ttATA our
vss?st' rs" POI sunm uurms
I z: WR tt
3:45 A. wm: , .
Cet Ctif A No} CLOCK
A0 At..' 'ii': f, UK! ' GENERATOR
" D.'., :::
:-: u A COLUMN
Vtt .5. Eu l AOO-> 233%??? oscoou
:.: as u au F n to
" At cr- sznss AMP
At, A6 A2 mmu uo GATE q
A7 M..' hh" M .30. tenuous:
... M HI'-
" " tt
2:3: t {3%} Me ' MEMORY
ABC» ROW 8 1024 ARMY
AD??? v ' 1026tt Ion
A90. , " R l ol w ' x4
m no.1 CLOCK suasrur: ms
Cr--- ceutvwon censuron
TC51 4402AP/AJ/ASJ/AZ-N, TC51 4402AP/AJ/ASJ/AZ-8o
TC51 44o2AP/A0/ASJ/Az--1 0
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
input Voltage " - lee? V 1
Output Voltage VOUT - 1~7 V 1
Power Supply Voltage Vcc - _ V 1
Operating Temperature Tova 0~70 'C 1
Storage Temperature Tsm - SS-ISO 'C I
Soldering Temperature .Time TSOLDER 260. 10 'C . sec 1
Power trissip'ation Po 700 mW 1
Short Circuit Output Current lour so mA 1
RECOMMENDED DC OPERATING CONDITIONS(Ta=O~70°c)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES
Vcc Supply Voltage 4.5 5.0 5.5 V 2
Ihr, Input High Voltage 2.4 - 6.5 V 2
" Input Low Voltage -1.0 - 0.8 V 2
TC51 4402AP/AJ/ASJ/AZ-70, TC51 4402AP/AJ/ASJ/AZ-80
TC51 4402AP/AJ/ASJ/AZ-1 o
DC ELECTRICAL CHARACTERISTICS Mx = 5V i 10%, Ta = 0--7ty'c)
SYMBOL PARAMETER MIN. MAX. UNITS NOTES
OPERATING CURRENT TCStM02AtVAlfAsJtAb70 - 100 3 4
Ian Average Power Supply Operating Current TCS1M02AptiuttkSmu.80 - 85 mA
W5. TT, Address Cycling: tttc-lu: MIN.) 'cs1otr2A"utAtvAb1tl - 75 5
STANDSY CURRENT
Icce Power Supply Standby Current - 2 mA
(m " B = VIH)
m ONLY REFRESH CURRENT _ TC5Md02APttutASJtAb70 -' 100
kya Average Power Supply Current, m Only Mode TCSIMOZAPIAJIASJIAZ-OO - 85 mA 3, 5
(m Cycling, eGvw. tAcartac MIN.) TCStM0NkPfAJtASMAb10 - 75
STATIC COLUMN MODE CURRENT T0t6a02APtAgfASMAb70 - 85 3. 4
Average Power Supply Current. STATIC COLUMN TC5uM2AMutASlJAb80 - " mA
ko Mode (RTS=C§=V,L. Address Cycling: tsta ts: MIN.) TCS‘MOZAPIAJIASJIAl-lo - 70 S
STANDBY CURRENT
Iccs Power Supply Standby Current - 1 mA
(m:E=V¢c-O.2V) ,
3 BEFORE m REFRESH cuaasm TCs1M02AWAJtAutAr70 - 100
lccs Average Power Supply Current, C5 Before RAT TCs1M0tAfrtAJtASJtAzAr0 - 85 mA 3, 5
Mode (W. B Cvdingi tstctststt: MIN.) TCs1M00AFlAJlA$ltAb10 - 75
INPUT LEAKAGE CURRENT
I. C) Input Leakage Current. any input - 10 10 PA
(OVSVmS 6.5V, All Other Pins Not Under Test=OV)
OUTPUT LEAKAGE CURRENT
I - 10 1
t2 tu (Dow is disabled, ovsvomsssw 0 "A
OUTPUT LEVEL
Von . . 2.4 _- v
Output H Level Voltage ttour " - SrnAl
OUTPUT LEVEL
V - 0.4 V
OL Output "L" Level Voltage tiour= 4.2mA)
TC514402AP/AJ/ASJ/Az-70, TC51 44o2AP/AJ/ASJ/Az--80
TC51 4402AP/AJ/ASJ/AZ-1 O
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc=5V-t 10%, Ta=ir-7ty'c)(Notes 6, 7, 8)
TC5 MAOZAPI TC514402AP/ TCS I “02AM
SYMBOL P ARAMETER AJIASJ/AZ-70 AJ/ASJIAZ-BO AJ/ASJIAZ-w UNIT NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
tag Random Read or Write Cycle Time 130 - ISO .. 180 - m
tmw ReadNodHpWrite Cycle Time 185 - 205 - 245 - n5
tsc Static Column Mode Cyclo Time 40 - 45 - " - ns
lsww 'e/e' gizmn Mode Read-Modify-Write 100 - 110 - 135 - ns
tstac Access Time from m - " - 80 - 100 ns 'i':
tou: Access Time from CS - 20 - 20 - " ns 9,14
tan Access Time from Column Address - 35 - 40 - so ns 9,15
tatw Access Time from Last Write - 65 - " - 95 ns 9.16
tcct B to output in Low-Z 0 - 0 - - ns 9
torr Output Buffer Turn-olf Delay 0 20 0 20 20 ns 10
uor, Output Data Hold Time from Column 5 - 5 - 5 - ns
Addres
tow Output Data Enable Time from WRITE - 20 - 20 - 30 m
tr Transition Timetttise and Fall) 3 SO 3 so 3 so ns 8
tap m Precharge Time so - 60 - 70 - ns
tttas m Pulse Width 70 10,000 80 10.000 100 10,000 n:
husc m Pulse WidthtStatic Column Mode) 70 200,000 80 200.000 100 200,000 ns
tnsn E to liM Hold Time " - 20 - " - ns
lcsu m to 3 Hold Time 70 - 80 - 100 - ns
tcs t? Pulse Width 20 10.000 " 10.000 " 10,000 ns
tcsc (5 Pulse WidthtStatit Column Mode) 20 200,000 " 200,000 25 200,000 In
taco m to (3 Delay Time 20 so 20 60 25 75 ns 14
trust, m to Column Address Delay Time IS 35 15 40 20 so ns 15
law eg to m Precharqe Time 5 - S - 10 - n:
tty' B Precharge Time 10 - 10 - 10 - ns
tasa Row Address Set-Up Time 0 - 0 - 0 - m
(sum Row Address Hold Time 10 - 10 - 15 - ns
tasc Column Address Set-Up Time 0 - 0 - 0 - n:
tcau Column Address Hold Time 15 - 15 - 20 - m
tart Column Address Hold Time referenced as - " - Its - ns
to R35 (READ CYCLE)
lam. Column Address to m Lead Time 35 - 40 - so - ns
hm fjgggidrus Hold Time referenced 5 - S - 10 - ns 17
TC514402AP/AJ/ASJ/AZ-70, TC51 44o2AP/AJ/ASJ/AZ--8o
TC51 4402AP/AJ/ASJ/AZ-1 o
TCSMdOIAPI TCS14402API TCSMAOZAP/
SYMBOL P ARAMETER A1/ASJ/A2-70 AJ/ASJ/AZ-BO AJ/ASJIAZ-IO UNITS NOTES
MIN. MAX, MIN. MAX. MIN. MAX.
“WAD f Write to Column Address De ay 20 30 20 35 25 45 m 16
LastWritetoCol Add Hold
“HUN ‘as n e o o umn ress o 65 - 75 g 95 - ns
R d Co nd Set- Time ref r n: d
lacs ea mma up I e e e 0 - 0 - t) - ns
Read Command Hold Time referenced
t 0 - 0 ... 0 - ns 11
RCH to 3
t Read Command Hold Time referenced O 0 0 11
- - - ns
RRF4 to TOST
Write Command Hold Time
t IS - 15 - 20 - ns 13
WC" (Output Data Disable)
twp Write Command Pulse Width 15 - IS - 20 - ns
tw, Write Command Inactive Time 10 - IO - 10 - ns
1mm Write Command to m bead Time 20 - 20 - 25 - ns
tch Write Command to ey Lead Time 20 - 20 - . " - ns
tos Data-ln Set-Up Time 0 - O - O - ns 12
tor, Data-ln Hold Time IS - 15 - 20 - m 12
tttts Refresh Period - 16 - 16 - 16 ms
twcs Write Command Set-UP Time 0 - t) - 0 - m 13
(Output Data Disable)
t3 to WRITE Delay Time
- s - - 13
tcwo (READ-MODIFY-WRITE CYCLE) so " 60 m
m to WRI'IE Delay Time
t 100 - ll - 135 - 1
ttwt) (READ-MODIFY-WRITE Cycle) 0 m 3
Uwo Column Address to WHITE Delay Time 65 - 70 - 85 - n: 13
tcpt 8 Sthp TimeKE before 1015) s - S - S - ns
tcmt CT Hold Time(C§ before m 15 - 15 - 20 - ns
1ng m to G Precharge Time 0 - t) - t) - ns
tcrm cs Precharge TirnetCT before m 40 - 40 - 50 - ns
Counter Test Cycle)
ttttVi m Hold Time referenced to U! 10 - 10 - 20 - ns
toga Tit Access Time - 20 - 20 - 25 ns
tow US to Data Delay 20 - 20 - 25 - ns
Qutput Buffer turn off Delay Time
Ion from 6.: 0 20 0 20 0 20 ns It)
too, 65 Command Hold Time 20 - 20 - 25 - n5
TC5144o2AP/AJ/ASJ/AZ-70, TC51 4402AP/A0/ASJ/Az-80
TC51 4402AP/AJ/ASJ/AZ-1 o
TC514402AP/ TC514402AP/ TC514402AP/
SYMBOL P ARAMETER AJIASJ/AZ-70 AJ/ASJ/AZ-BO AJ/ASI/AZ-IO UNIT NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
twrs Write Command Set-Up Time 10 - 10 - 10 - m
two, Write Command Hold Time 10 - 10 - 10 - n3
twap irv%Tt to m Precharge Time It) - 10 - 10 - n:
twnH WRITE to RAS Hold Time 10 - IO - 10 - ns
TC51 4402AP/AJ/ASJ/Az--70, TC51 4402AP/AJ/ASJ/Az--80
TC51 4402AP/AJ/ASJ/AZ--1 o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE
TEST MODE (Vcc=5Vt 10%, Ta=0--70'c) (Notes 6, 7, 8)
TCSMAOZAPI TC514402AP/ TC514402AP/
SYMBOL PARAMETER AJ/ASJ/AZ-70 AJ/ASJIAZ-BO AlfA$J/Ab10 UNIT NOTES
MIN. MAX. MIN, MAX. MIN. MAX.
lac Random Read or Write Cycle Time 135 - 155 -'' 185 - ns
tmw Read-Modify-Write Cycle Time 190 - 210 - 250 - m
tsc Static Column Mode Cycle Time 45 - so - 60 - ns
lsmw _ 'el' 122::mn Mode Read-Modify-Write 105 - HS - 14() - ns
tug Access Time from C3 - " - 85 - 105 ns 'i?
tou: Access Time from CT - " - 25 - 30 ns 9,14
tan Access Time from Column Address - 40 - 45 - 50 ns 9,15
tacw Access Time from Last Write - 70 - 80 - 100 ns 9,16
IRA; m Pulse Width " 10,000 85 10,000 105 10,000 ns
tusc m Pulse Width(Statit Column Mode) 75 200,000 85 200,000 105 200,000 ns
tag” 'RTS Hold Time 25 - 25 - ' 30 - ns
tcsr, E5 Hold Time 75 - as - 105 - ns
tcs 8 Pulse Width 25 10,000 " 10,000 30 10,000 ns
tcsc cs Pulse Width (Static Column Mode) 25 200,000 25 200,000 30 200,000 ns
tRAL Column Address to m Lead Time 40 - 45 - 55 - m
tCWD CS to WRITE Delay Time 60 - 60 - 70 - ns 13
titwo m to WWW Dalay Time 105 - 115 - 140 - ns 13
tawo Column Address tom Delay Time 70 - " - 90 - ns 13
ttwa UP Access Time - 25 - 25 - 30 m
togo CE to Data Delay 25 - 25 - 30 - ns
tom Ut Command Hold Time 25 - 25 - 30 - ns
CAPACITANCE (Vcc = 5V A10%, f=1MHZ, Ta = 0--70''c)
SYMBOL PARAMETER MIN. MAX. UNIT
ct, Input CapacitancetA0-A9) - s PF
Ca Input CapatitanretliM, CT. Wm, UE) - 7 pF
Co Input/Output Capacitance(ll01-V04) - 7 pF
TC51 4402AP/AJ/ASJ/AZ-70, TC51 4402AP/AJ/ASJ/AZ-80
TC51 4402AP/A0/ASJ/Az--1 o
N OTES:
@999.”
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
All voltages are referenced to Vss.
ICC]. Icca, Icca, Iccs depend on cycle rate.
ICCI. ICC4 depend on output loading. Specified values are ouained"with the output open.
Column address can be changed once or less while m=vm and CS=V[H.
An initial pause of 200ps is required after power-up followed by 8 m only tefresh cycles before
proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CS
before RES refresh cycles instead of 8 HAS refresh cycles are required.
AC measurements assume tr=5ns.
VIH (min.) and V1L(max.)are reference levels for measuring timing of input signals.
Measured with a load equivalent to 2 TTI, loads and 100pF.
topp (max.) and toEztmax.)define the time at which the output achieves the open circuit condition
and are not referenced to output voltage levels.
Either met! or tam; must be satisfied for a read cycle.
These parameters are referenced to CS leading edge in early write cycles and to WRITE leading
edge in Read-Modify-Write cycles.
twcs, tnwn, tcwo and tAWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If twcsz twcs (min.), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) through the entire cycle; If
tiuvoiiitmwo(min.), tcwD2ttcwD(min.) and tAwrrittAwDimin.) the cycle is a Read-Modify-Write
cycle and the data out will contain data read from the selected cell: If neither of the above sets of
conditions is sausmed, the condition of the data out(at access time) is indeterminate.
Operation within the tncn(max.)limit insures that tmc (max.) can be met.
tncp(max.)is specified as a reference point only: If tRCD is greater than the specified taco(max.)
limit, then access time is controlled by tCAC.
Operation within the tRAD(max.)limit insures that tMc(max.) can be met.
tnAD(max.) is speeimed as a reference point only: If tram is greater than the specified tmn(max.)
limit, then access time is controlled by tAA.
Operation within the tL\VAD(max.) limit insures that tALw(max.)can be met.
thADUnax.) is specified as a reference point only: If tRAD is greater than the specified tLWAD
(max,) limit, then access time is controlled by tAA.
tAH is the condition to latch column address ewhen US has rised up.
TC51 4402AP/AJ/ASJ/Az--70, TC51 4402AP/AJ/ASJ/AZ-8o
TC51 4402AP/AJ/ASJ/AZ-1 o
READ CYCLE
A(P-A9
COLUM N
<< << << $5 $5 55
'92 FE Ff v-r. r3; r;
|/O1~l/04 DATA - OUT
WRITE CYCLE QEARLY WRITE!
S5 $5 $5 55 <_< $5
r-x F: F: 4-: I F:
II II || II II II
COLUMN
'ijCti2i,iffjtf
tos tost
--------? DATA. IN E OPEN
trot-WM
C''gt": .. "H" or "L"
TC514402AP/AJ/ASJ/Az-70, TC51 4402AP/AJ/ASJ/AZ-80
TC51 44o2AP/AJ/ASJ/Az--1 o
WRITE CYCLE (GE CONTROLLED WRITE)
es tcs
MP-NY v COLUMN
l/O1~ll04 V DATA . IN
READ - MODIFY - WRITE CYCLE
A0-A9 V COLUMN
Ihr, tOEA
IIO1~IIO4 V DATA. IN
'itat : "H" or "c"
Eg.. "H'' or 'L'
TC51 4402AP/AJ/ASJ/AZ-70, TC51 4402AP/AJ/ASJ/AZ-80
TC51 4402AP/AJ/ASJ/AZ-1 tl
STATIC COLUMN MODE READ CYCLE
uou~uoa OH
OL"-"-"
Dou, 2
(g'ff) : "H' or "L''
TC51 4402AP/AJ/ASJ/AZ-70, TC51 4402AP/AJ/ASJ/AZ-80
TC51 4402AP/AJ/ASJ/Az-1 o
STATIC COLUMN MODE WRITE CYCLE {EARLY WRITE!
A0--A9
IIO1~1IOd
STATIC COLUMN MODE WRITE CYCLE {EARLY WRITE}
" tusc
l/Ol IIO4 Vm
TC51 4402AP/AJ/ASJ/AZ--70, TC51 4402AP/AJ/ASJ/AZ-80
TC51 4402AP/AJ/ASJ/AZ-1 O
STATIC COLUMN MODE READ - MODIFY - WRITE CYCLE
A0-A9 COL. l
" limo
tsttstw tttue
l/OI~UO4
Eg.. "H" or "L"
TC51 4402AP/AJ/ASJ/Az--70, TC51 4402AP/AJ/ASJ/AZ-80
TC51 44o2AP/AJ/ASJ/Az--1 o
STATIC COLUMN MODE READ/WRITE MIXED CYCLE
A0--A9 '"
tos tan tAou
Won --
1/01 ~1/04 om:
Dourl 0m"
OL-" N
(WRITE) (READ) (READ) (WRITE)
'Lett : "H" or 'L'
TC5144o2AP/AJ/ASJ/Az-70, TC51 4402AP/AJ/ASJ/AZ-8o
TC51 4402AP/AJ/ASJ/Az---1 o
HAS ONLY REFRESH CYCLE
___....___3 _‘__..____,
m v... 'ss, tm l /
" - K '. L_,
A0-A9 ITS t',f,if,j ROW t'ifiEtitiEEEE/iijiiiiE4,f, -
ga.. "H" or 'L'
Note: WRITE. UE=“H" or "L"
TC51 4402AP/AJ/ASJ/AZ-70, TC51 44o2AP/AJ/ASJ/AZ--80
TC51 4402AP/AJ/ASJ/AZ-1 O
CS BEFORE RAE REFRESH CYCLE
._._‘R_P__.. .-t.y'...-,
" -...- a a
" - “k
t l tcsx
a::::fxl J/ff/it/f/j;),, // //%
l twnv
ivnrc,,yci'Fg'i' Q.,
V -""""'"'-""-"""N,
1~uoa OH
VOL ----.-..-l
'g9," t'' . . .
Note: 1E,A0-Agra"H"or"L'' //A H or L
TC51 4402AP/AJ/ASJ/Az--70, TC51 4402AP/AJ/ASJ/AZ--80
TC51 4402AP/AJ/ASJ/AZ-1 0
HIDDEN REFRESH CYCLE READ
toss tie tap
V." s....-."-'"-"", e"""''-""' in
m V \ / N-------'-------- \
IL - -x_________._r- -
lots, lace tam. tom J too
i3 vo, - law r,
V". - tttao -k
mm ‘AH
AME, 't 1r,f,fiifijj' (wrég " COLUMN -s- (iltiiziiiiiiiisii'iaititiiiiiziiiiziii
r cs 'st l, 1.4m
ismc'v4-rrii'ii'itiitii'ii?'' taa I/
tsd,',:'.:-,),',),?)''',;''!;", ',,sst,iiiiiss,iii, J'" tttOH 2'c'"'')i'.ti:" /pt2:isij,
' ttac r
l inc ‘cu tote
V - I " a
l - OH
tOI "r------'---------'), DATA-OUT F-------
1/04 VOL - “K f
Eg.. "H" or (
TC51 4402AP/AJ/ASJ/Az--70, TC51 4402AP/AJ/ASJ/AZ-80
TC51 4402AP/AJ/ASJ/AZ-1 O
HIDDEN REFRESH CYCLElWR1TE0
'." oo CR
VIH - " a ie""""'''""--""""
" ____/ -" RAD w
--A9 :1: Cii,i';ffi,)iCrriiXi)]
C: -I'j',jt'';etj)'''fsviiii,jts,
w: tec
in: L 1m , J’L.
'is, r-st,,--------,-----------, \
teo lnsu t ' t p
twcs tw
tut: -tpy.
7: "H" of L"
TC51 4402AP/AJ/AN/Az--70, TC5144o2AP/AJ/ASJ/Az--80
TC51 4402AP/AJ/ASJ/AZ-1 o
CS BEFORE ILM REFRESH COUNTER TEST YCLE
Ihre _.,-----)
Ihr, -- -
ZS Wt---
A0-A9 :::“%/////////////:L COLUMNADDMSS
READ CYCLE two, two, AA
vtti0TT ZII‘W‘ '1t2fffsffy"' f tttore '%f
a :1:W//////M// j)tibto" st //f/ ts,tsis''
H-----
F In: a d;
vols. Von - f
1/04 OPEN DATA - our
VOL - t r:
twto twRH
WRITE CYCLE
(Viim? II? "Cf/ff/j/tl 'tb'ii''i'ii;i'iiife)/rc' twc" wtiiiiiiiii'is''i'ii, l/fiW/Z/i
a 3132/
L...."._.
'ssl l
- "q----.----
LC,',,:,':,,-.- OPEN I BMW: M
WRITECYCVL': A IH l, A F53 m i a'"",
-WRiTT " -...'ifrfi'iy "tiiiitEiift' 'SC, iii/iiiatiiiiiiiiiiFi,
I taa -
“1::me tosa /
'")1ctt','tr..r. Ctt (ss
: "H'' or "L" ooooo
TC51 4402AP/AJ/ASJ/Az-70, TC514402AP/AJ/ASJ/Az-80
TC51 4402AP/AJ/ASJ/Az--1 O
WRITE, cg BEFORE HIS REFRESH CYCLE
" - a teas /)" a
m " - 's, 'is,
trn, 2c-.ssu tote
VIH - -.r"'""'"'"h
t; " -._..V/ " /,,o4''''" /,stft,
tms twm
WWTT (rr'jjitiggtjitiii,,ty,,s ///
Vort--c
l/Ol ~I/04 R
V0]. - C" OPEN
Note: UH, A0--A9= "H'' or "L"
(gg : "H" or 'L'
TC51 4402AP/AJ/ASJ/AZ--70, TC514402AP/AJ/ASJ/Az-80
TC51 4402AP/AJ/ASJ/Az--1 o
TEST MODE
The TC514402AP/AJ/ASJ/AZ is the RAM organized 1,048,576 words by 4 bits, it is internally
organized 524,288 words by 8 bits. In "Test Mode", data are written into 8 sectors in parallel and
retrieved the same way. ADC is not used. If, upon reading, two bits on one 110 pin are equal (all "I"s
or "0"s) , the I/O pin indicates a "1". If they were not equal, the I/O pin would indicate a "O". Fig. 1
shows the block diagram of TC514402AP/AJ/ASJ/AZ. In "Test Mode", the 1MX4 DRAM can be tested
as if it were a 512KX4 DRAM.
“WRITE, CS Before m Refresh Cycle" puts the device into "Test Mode". And “US Before m
Refresh C cle "or "mm Only Refresh Cycle" put it back into "Normal Mode". In the Test Mode,
" E, Before m Refresh Cycle" performs the refresh operation with the internal refresh
address counter. The "Test Mode" function reduces test times(1/2 in cace of N test pattern).
TC51 44o2AP/AJ/ASJ/AZ-70, TC51 4402AP/AJ/ASJ/AZ--80
TC51 4402AP/AJ/ASJ/AZ-1 O
BLOCK DIAGRAM IN THE TEST MODE
Aoc V C
A w----------' Normal
oc A =,xs--H
Normal h
T-""" 512K block - s-r) Do Test
V01 ost, -icr A
Test DC tt
Ch-ur- 512Kblotk - -', Cy---------))
a ' 'o----]
-----Q . iNormaI
Aoc V C
-------Q Normal
A04: c xr---]
Normal _ 512K block - s-l Test
t/02 -'so, c
Test Am: D
512K block - ', LDr--------o2Ct
D 1 'xr-l
------o iNormal
--------o
_____vo: V c
----o Normal
Aoc E xr---)
----iu)---w , I yr--------;
Normal . S12K block - s--) Test
v03 --'Ne, --- E
Test AOC F
512K block - l [Dr--------;'')
F ' 'o---]
-----Q iNormal
---------o
voc V C
--------0 Normal
Aoc G xr-l
---iuir-- l I yr----------;
Normal . 512K block - r--) Test
1/04 ---os G
Test Aoc H
Ab-u? 512K block _ 3 Dy----------)?
H -T 'ts--]
-----© TNormal
---------of L
Fig. 1
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