TC514400Z-10 ,100 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization . Low Power
. Fast access time and cycle time 578 ..
TC514400Z-80 ,80 ns, 4-bit generation dynamic RAMELECTRICAL CHARACTERISTICS (Vcc=5VilOZ, Ta-Om70°C)
SYMBOL PARAMETER 'lf-riff)?,??''?,'??,]
Aver ..
TC514400ZL-80 ,80 ns, 4-bit generation dynamic RAMELECTRICAL CHARACTERISTICS (VCC=5V110%, Ta=0~70°C)
5mm. PARAMETER
Operating Current
ICCl Avera ..
TC514402ASJ-80 ,80 ns, 4-bit generation dynamic RAM1048,576 WORD x 4 BIT DYNAMIC RAM
DESCRIPTION
The TC514402AP/AJ/ASJ/AZ is the new generation ..
TC514402AZ-60 ,60 ns, 4-bit generation dynamic RAMfeatures include single power supply of 5Vi10% tolerance,
the TC514402AP/AJ/ASJ/AT to be package ..
TC514402AZ-70 ,70 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576
word by 4 bit organization
. Fast access time and cycle time
TC51440 ..
TC7WG04FK ,L-MOS LVP seriesabsolute maximum ratings Note 2: High or Low State. Do not exceed I Start of commercial productionO ..
TC7WG08FC ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 mm × 25.4 m ..
TC7WG125FK ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTStart of commercial production 2006-021 2014-03-01 ..
TC7WG126FC , CMOS Digital Integrated Circuit Silicon Monolithic Dual Bus Buffer with 3-STATE Output
TC7WG126FK ,L-MOS LVP seriesabsolute maximum ratings. OUTStart of commercial productionNote 3: V < GND OUT2006-021 2014-03-01 T ..
TC7WG14FC ,L-MOS LVP seriesabsolute maximum ratings. OUT1A 3Y 2A GNDNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 ..
TC514400Z-10-TC514400Z-80
100 ns, 4-bit generation dynamic RAM
m CT o; ""r,"_i:","F i Fii {“555151:
1,048,576 WORD X 4 MT DYNAMIC RAM * This is advanced information and specifications
DESCRIPTION are subject to change without notice.
The TCSlthOJ/Z Is the new generation dynamic RAN organized 1,048,576 words by 4
bits. The TC51p00J/2 utilizes TOSHIBA‘s CMOS Silicon gate process technology as well
as advanced circuit techniques to provide wide operating margins, both internally and
to the system user. Multiplexed address inputs permit the TC5Li400J/2 to be packaged
in a standard 26/20 pin plastic SOJ and 20 pin plastic ZIP. The package size pro-
vides high system bit densities and is compatible with widely available automated
testing and insertion equipment. System oriented features include single power Supply
of 5irtlty,t tolerance, direct interfacing capability with high performance logic families
such as Schottky TTL.
FEATURES
. 1,048,576 word by 4 hit organization . Low Power
. Fast access time and cycle time 578mil MAX. Operating (TC514400J/2-80)
TC5144001/2-8Q/Fld AQSmW MAX. Operating (TC514400J/Z-10)
t - 5.5aV MAX. Standby
RAC I/tfue/tice',"' 80ns lOOns . Outputs unlatched at cycle end allows two-
tAA Access Time 40ns 50ns dimensional chip selection
tCAC tThT; Access Time 20ns 25ns . Re_a.1-rfotury-urite, m before It%rrefresh,
CRC Cycle Time 150ns 180ns RAS-only refresh, Hidden refresh and
Fast Page Mode Fast Page Mode capability
tpc Cycle Time 50ns 60ns . All inputs and outputs TTL compatible
0 1024 refresh eyc1es/16ms
. Package Plastic SOJ: TCSlMOOJ
Plastic ZIP: TC5144002
. Single power supply of 5Vt10r, with a
built-in VBB generator
PIN CONNECTION (TOP VIEW) BLOCK DIAGRAM
Plastic SOJ Plastic ZIP 1/01 Vote Vos Vos
t5E 'ff') t-qd
" 2 Trs-
Q ", bi
1:3: iyi,' [24: Vos Vcc Vss A *
1/02 33 'd9i;''l-1i, i DATA IN DATA our --oh7e"
m 'jil ,5 ITE BUFFERB Bnmaa "
A0 133 g) A9 'rtTrg" f l J T
A2 ran, 'rbi), A1 I
Vcc lh] 5:13: M - No. 2 CLOCK
A5 ii: 9:6: M CAB0-- GENERATOR
" as; A6 , "I
AT 1 -.
" 'al,A8 o COLUMN COLUMN
PIN NAMES fi',',': IO 'liT"rug'dato Io.) DBCODM
amass m.
A0 m A9 Address Inputs 22°" REFRESH Vo (um:
RAS Row Address Strobe " ""f'"''" - ION
CAS Column Address Strobe Mo-- REFRESH - 'rt""
WRITE Read/Write Input A6o-- g coum'mmm) ,
62" Output Enable ATO-- ROW . ,3: I MEMORY
Mo-s ADDRESS 10 ) g g ION ARRAY
IéOlmI/OA gata I?P:;;OUtpu A9,3... o BUFFiiRSOD) . g i 1024x1024)“
CC ower' +
v G d Kiig No. 1 CLOCK f
SS roun Q GENERATOR
BUBSTRATB ans
GENERATOR
TC51 440thl/Z-8o
TC51 440tu2--1 o
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTE
Input Voltage VIN -1n.7 V 1
Output Voltage VOUT -1m 7 v 1
Power Supply Voltage Vcc -1m 7 v 1
Operating Temperature TOPR " 70 "c 1
Storage Temperature TSTG -55~150 ''C 1
Soldering Temperature . Time TSOLDER 260 . 10 °C-sec 1
Power Dissipation PD 600 mil 1
Short Circuit Output Current IOUT 50 m 1
REC0NNEN0E0 DC OPERATING CONDITIONS (Ta'0m70°C)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTE
Vcc Supply Voltage 4.5 5.0 5.5 ll 2
VIH Input High Voltage 2.4 - 6.5 ll 2
ilri. Input Low Voltage -l.0 - 0.8 V 2
DC ELECTRICAL CHARACTERISTICS (VCC=5VilOZ, Ta-ON70°C)
SYMBOL PARAMETER MIN. MAX.UNITS NOTES
OPERATING CURRENT T05144OOJ/Z-80 - 105
ICCl Average Power Supply Operating Current mA 3,4,5
(KITS, m, Address Cycling: tRc=tRC MIN.) Tt3s1ig0og/z-10 - 90
STANDBY CURRENT
ICCZ Power Supply Standby Current - 2 mA
(W=CK§-Vm)
US ONLY REFRESH CURRENT TcsluoOJ/z-eo - 105
ICCB Average Power Supply Current, m Only Node mA 3,5
(m Cycling, Trg-vim tchtRc MIN.) Tt9s1te0oVz-10 - 90
FAST PAGE MODE CURRENT A
ICCA Average Power Supply Current, Fast Page Node muuoo‘T/z-% - .70 mA 3,4,5
(muvu, EG, Address Cycling: tPc'tpc MIN.) 'rCs1sto0Vz-10 - 60
STANDBY CURRENT
ICCS Power Supply Standby Current - 1 mA
. (m-m=VCC-O . 2V)
m BEFORE m REFRESH CURRENT -
ICC6 Average Power Supply Current, Tgig Before T0514400J/z-ao 105 mA 3
tTift Mode (KAT, CET Cycling: tRC'tRC MIN.) Tto51itoiz-1o - .90
INPUT LEAKAGE CURRENT
II(L) Input Leakage Current, any Input -10 10 uA
(ova VIN: 6.3V, All Other Pins Not Under Test-OV)
OUTPUT LEAKAGE CURRENT
100-) (Dow ls disabled, ogg Vourf- 5.5V) -10 10 "
OUTPUT LEVEL
VOH Output "ll" Level Voltage (IOUT=-5mA) 2.4 - ll
OU'IPUT LEVEL
VOL Output "L" Level Voltage (IOUT=4.2mA) - Od l?
TC51 440tu2-8o
TC51 440tulZ--1 0
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc=5VtIOZ, Ta-tport))) (Notes 6, 7, 8)
TC51h4003/z TC5144OOJ/Z
SYMBOL PARAMETER -80 -10 UNIT NOTES
MIN. MAX. MIN. MAX.
tRC Random Read or Write Cycle Time 150 - 180 - ns
tRMW Read-Modify-teste Cycle Time 205 - 245 - n8
tPC Fast Page Mode Cycle Time 50 - 60 - n8
tPRMW Fast Page Mode Read-Modify-Write Cycle 105 - 125 ... n8
tRAC Access Time from ITG - 80 - 100 us 01015
tCAC Access Time from m: - 20 - 25 ns 9,14
tAA Access Time from Column Address w 40 - 50 ns 9,15
tCPA Access Time from TiG Precharge - Ci - 55 n8 9
cc1.z ttTG to Output in Low-Z o - 0 - ns 9
torr Output Buffer Turn-off Delay 0 20 0 20 ns 10
tT Transition Time (Rise and Fall) 3 50 3 50 ns 8
tRP Tirs" Precharge Time 60 - 70 - ns
tRAS "ii7iT; Pulse Width 80 10,000 100 10,000 as
tRASP Ers- Pulse Width (Fast Page Mode) 80 200,000 100 200,000 us
tRsu "iws- Hold Time 20 - 25 - as
tcsu its Hold Time 80 - 100 - ns
tRucp E_§ Precharge to Ers" Hold Time 45 - 55 - n3
tczas t7g Pulse Width 20 10,000 25 10,000 as
tch Tt"gig to ttWg Delay Time 20 60 25 75 us 24
tRAD TiTtTeo Column Address Delay Time 15 40 20 50 ns 15
tcite 'ttsto 11TG Precharge Time 5 - 10 - 08
tcp tTitTPreeharge Time 10 - 10 - us
tASR Row Address Set-op Time 0 - 0 - ns
tRAH Row Address Hold Time 10 - 15 - n8
tASC Column Address Set-Up Time 0 - 0 - ns
tCAH Column Address Bold Time 15 - 20 - n3
tAR Column Address Hold Time referenced to 60 - 75 - tttt
tRAI, Column Address to Mg Lead Time 40 - 50 - ne
tRCS Read Command Set-op Time o - 0 - n3
tRCH Read Command Hold Time 0 - 0 - ns 11
TC51 4400Jlz-80
TC51 44oNlz--1 O
ELECTRICAL CHARACTERISTICS AND RECOMMENDED M OPERATING CONDITIONS (Continued)
rcsumooa/ Icsuaow/
SYMBOL PARAMETER 2-80 2-10 UNITS NOTES
MIN. MAX. MIN. MAX.
tRRI-I Read Command Hold Time referenced to Eig 0 - 0 - us 11
two}; Write Command Bold Time 15 - 20 - n8
twcg Write Command Hold Time referenced to m 60 - " - ns
tWP Write Command Pulse Width 15 - 20 - ns
tRia, Write Command to fOTg Lead Time 20 - 25 - n8
tcur, Write Command to m Lead Time 20 - 25 - ns
tps Data See-op Time 0 - 0 - ns 12
tDH Data Bold Time 15 - 20 - ns 12
tDHR Data Bold Time referenced to m 60 - 75 - us
CREF Refresh Period - 16 - 16 ms
twcs Write Command Set-Up Time 0 - o - ns 13
tCWD m to TriMIr Delay Time 50 - 60 - us 13
tan RTS' to tTtT'tft" Delay Time 110 - 135 - ns 13
t1AM) Column Address to WE Delay Time 70 - 85 - ns 13
CCPYD tifesPl/itlu'd' ThErig Delay Time 75 - 90 - ns 13
tCSR tTA-g Set-op Time (m before 1TCs Cycle) 5 - 5 - :13
tom tTirg Hold Time (EA-S' before m Cycle) 15 - 20 - Ittt
tRPC ITirg to CTS' Precharge Time 0 - 0 - n3
tCPT t?l?rsPt':t'eh'isfr1g,'u,,,e, Test Cycle) h0 - 50 - ns
ttttm m Hold Time referenced to O? 10 - 20 - n3
tom Off Access Time - 20 - 25 n3
tom) " to Data Delay 20 - 25 - "
tom Output Buffer Turn Off Delay Time from trg 0 20 0 20 us 10
t.orm W Command Hold Time 20 - 25 - 118
turs Write Command Set-Up TimetTest Mode Its) 10 - 10 - n8
tWTH Write Command Hold Time (Test Mode In) 10 - 10 - us
---- o tirs- Pr r Time
tHRH 'Ferl-i-fthe",'"'-,-))?'],','?,',")' m - m - us
TC51 440NlZ-80
TC51 440NlZ-1 o
ELECTRICAL CHARACTERISTICS AND REC0NNEN0E0 M OPERATING CONDITIONS IN THE TEST MODE
TC514400J/Z. TC514400J/Z
SYMBOL PARAMETER -80 -10 UNIT NOTES
MIN. MAX. ' MIN. MAX.
tRC Random Read or Write Cycle Time 155 - 185 - n8
tPC Fast Page Mode Cycle Time 55 - 365 - ns
tRAC Access Time from RAS - 85 - 105 ns 9,14,15
tCAC Access Time from CAS - 25 - 30 ns 9,14
CAA Access Time from Column Address - 45 - 55 n3 9,15
“CPA Access Time from erG Precharge - 50 - 60 n8 9
tRAS Tics Pulse Width 85 10,000 105 10,000 tttt
tmsp "CA'ii" Pulse HidthtFast Page Mode) 85 200,000 105 200,000 ns
tRSH ifs Hold Time 25 - . 30 - ns
ccsg cTs Hold Time 85 - 105 - ns
tRHCP i5ifg" Precharge to -iiit1t" Hold Time 50 - 60 - n8
tCAS (:1? Pulse Width 25 10,000 30 10,000 ns
tRAI, Column Address co TigTs Lead Time 45 - 55 - ns
CAPACITANCE (Vocusvnoz, mum, Ta"0-70''C)
SYMB 0L PARAMETER MIN . MAX . UNIT
C11 Input Capacitance tAti-As) - 5 pp
012 Input Capacitance (fthTs, Ers, WiTTE, 5i) - 7 p?
Co Output Capacitance (I/Ol~I/04) - 7 p?
TC51 440tu2-80
TC51 440N)Z-1 o
NOTES'.
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. A11 voltages are referenced to 1rss.
3. 1001a ICC3, ICCA: Iccti depend on cycle rate.
4. 16019 ICC4 depend on output loading. Specified values are obtained with the
output open.
5. Column address can be changed once or less while FKE-VIL and EK§-VIH.
6. An initial pause of 200ps is required after power-up followed by 8 fiM only
refresh cycles before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CKE before RAS refresh cycles instead
of 8 liEt1" only refresh cycles are required.
7. AC measurements assume tT-Sns.
8. VIH(m1n.) and VIL(max.) are reference levels for measuring timing of Input
signals. Also, transition times are measured between VIH and VIL'
9. Measured with a load equivalent to 2 TTL loads and 100PF.
10. tOFF(max.) and tOEz(max.) define the time at which the output achieves the open
circuit condition and are not referenced Lo output voltage levels.
11. Either tRCH or tRRH must be satisfied for a read cycle.
12. These parameters are referenced to CKE leading edge in early write cycles and
to VRITE leading edge in read-modify-write cycles.
13. twcs, tang. tCND, CARD and ttmm are not restrictive operating parameters. They
are included in the data sheet as electrical characteristics only. If tvcstevcs
(min.) the cycle is an early write cycle and data out pin will remain open circuit
V (high Impedance) through the entire cycle; If tiumittmm (m1n.), tcwnncwn (aim),
twp: tAND (aim) and ten“); tCPWD (111111.) (Fast Page Bode), the cycle " a read-
modify-write cycle and data out will contain data read from the selected cell:
tf neither of the above sets of conditions is satisfied, the condition of the
data out (at access time) is indeterminate.
14. Operation within the t CD(max.) limit insures that t c(max.) can be met.
tRCD(max.) " ii'di"h2i as a reference point only: tt tch is greater than the
specified tch(max.) limit, then access time is controlled by eau:.
15. Operation within the tRAD(max.) limit insures that tRAc(max.) can be met.
tRAD(max.) is specified as a reference point only' If tRAD is greater than
the specified tRAD(max.) limit, then access time is controlled by egg.
TC51 440N/Z-80
TC51 440Nlz--1 0
READ CYCLE
AO-A 9
1/0 1~I/o4
VIL---
VALID DATA- OUT
iffiit "tP or "LII
WRITE CYCLE (EARLY WRITE)
Vor-tpot
IrIt,--
VIII -
1rrT,'---
1rIL--
VII, -
VALI D DATA-T N OPEN
TC51 440tulz-80
TC51 440N)z-1 0
WRITE CYCLE (GE CONTROLLED WRITE)
IrTL---
A099 m
VIL --
IrTH--.
Yu,---
1/01~1/o4 v VALID DATA-IN
al: "H" or "L"
READ-NOD IFY-WRITE CYCLE
Irtg--
VI}! -
I/ 1/ vL/OH --
1 . VI/OL -
TC51 44othlM-80
TC51 4400Jlz-1 o
FAST PAGE MODE READ CYCLE
truer t
1rrL-.-
1rlir-.
1r1L--
AOr-A 9
voil--
1/01~I/04
stifd VALID TA-OUT
TA-tWTI - . "H" or "L"
FAST PAGE MODE WRITE CYCLE
13MB? tity
IriH---
VIL---
AO-M VIL---
IrIH-.
VIE...
1/01~I,/04.
. VIL--
TC51 44Gu/Z-80
TC51 440NM-1 0
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
VIL --
VIE _..
AtH-A9
1/501 VI/OH_
I/m vi/OL-
-: "H" 91' "L"
TC51 44oN/Z-80
RAS ONLY REFRESH CYCLE
VI _-.-"-'"-"'"""""""""''"""' -
“g H ”ms /
VIL-..
tcar tam
TWg IriH.-
VIL.-, /
tAsR tttag
vrL-- ADDRESS
Note: TifirtT, tTiF''tl" or "L" ffd t "it" or "L"
CAS BEFORE RAS REFRESH CYCLE
-- VIH- - tmg
RAS / t N N
i--- RFC
- vm___ teen tam
CAS \ ff%%%jfffjfffLri/
(,,''i',rl._.._v/ /
"tut m
. WRITE ,"d,ullll.llll.ll] 1Qlllllllllllllilllf[llllllllllllllllllllllMh
1/01~I/04. o L OPEN
VOL - ___/
Note: Of, A0~A9-"H" or "1." Iff, t "g" or "L"
TC51 440thW-80
TC51 440Na-1 O
HIDDEN REFRESH CYCLE (READ)
tRc tRC
true tras ttttt
v --..-"-'"T
m 13 I tAR l Em ,
VII,........ -
tCRP tmm tnsa ‘ca?
tcna 'T""'""""--"-'--""'-
ITV IH t ily. 2
Il.. RAD
“ASE 35M! t0M1
1rnr-''" - ROW comm:
AtV-A9 - ADD ADDRESS
tvac cm War twan
1//-/)))'/'/'///i////)////))///f/)//'f/)//-/)'///
VOH - I
I/or-Vos
VALI D DATA- OUT
-: "H" or "L"
"j?,:?,'''''''''''" /
I-----------
TC51 4400J)z-8o
TCti1440Nlz--1 o t
HIDDEN REFRESH CYCLE (WRITE)
VIH - t
FEE Alt
VII. -
m j tam
V11. - t
23:”:22L
--A9 // Row COL N
Irrt,--- - ADD mm s
tij"il,i,l,i"ill"1.,l,,ls?"ll""l""-
7trtrrg T
oi-iii',
W////////////////////f///////////
im N,t,-,UliullilliipfpyipimyyNilluilliyiypuiiillliiiiijulh
tinte tm
Vol-Vo: If VALID DATA IN
1lfllllllWllllffffflfffffff000fl0ffffl,
a, "H" or "L"
TC51 4400Jlz-80
TC51 4400J)z--1 o
C'A'S BEFORE RAS REFRESH COUNTER TEST CYCLE
twr IH
AW-Ai) Ill
VI L -
READ CYCLE
F imITE VI”
VII! -
I/01~I/o4 VALID DATA-ODT
WRITE CYCLE
WRIT_E V1“ -
Volio: v1 VALID DATA-IN
READ-MODIFY-UR ITE CYCLE
V11. -
0E lil
V11. -
1/01~1/o4 1rVom--
VI/ttL--.
”II t "H" or "L" VALID DATA-OUT
TC51 4400J/z--80
TC51 440tulZ-1 o
VitTiX ' twg- BEFORE m REFRESH CYCLE
VIH - , t
m \ ms / \
vIL - .
VIH - - tr3812 .ttmtt
Tmr / \ gggaiai0iaiiaiaiiajij)
VIL - 7
IH 'y/j), "Til ff
Ira, - _
VOH - ',
1/01.~:L/04r [L OPEN
V01, - --.-...-a
OE, A0'uA9t "il" or "L" .= "H" or "L"
TC51 440tU2--80
TC51 440N)z--1 o
READ CYCLE IN THE TEST MODE
ms V94
CA8 vm
- COLUMN
AO " vu, ADDRESS
WRITE vm
m1~v04 v05 ------ VALID mn-OUT
vor, tteta
Note: tTiF. "L" 'l/A t "H" ot "L"
WRITE CYCLE (EARLY WRITE) IN THE TEST MODE
._ If -
cTs vm --
. v -.
A0~A9 IH
VII. -
wai'ra vm -
L tDHR
tm . tDH
L/OH/m vm ----------ivAhm ni-mr-------------------- OPEN
tti.-'"-
TC51 44oNM--8o
TC51 4400J)z--1 o
FAST PAGE MODE READ CYCLE IN THE TEST MODE
I/0ist/04
mu?” 1 v m DA A our:
Note: 05f = "L" TON. "ti" or "L"
FAST PAGE MODE WRITE CYCLE IN THE TEST MODE
W1~VO4
V11. -
TC51 440N)z-8o
TC51 440tulZ--1 o
TEST MODE
The TC51000J/z is the RAN organized 1,048,576 words by 4 bits, 1t is Internally
organized 524,288 words by 8 bits; In "Test Mode", data are written int0'8 sectors
in parallel and retrieved the same Way. Aoc is not used. If, upon reading, two bits
on one No pin are equal (all "I"s or "tPs), the I/O pin indicates a "1".
If they were not equal, the I/O pin would indicate a "0". Fig. 1 shows the block
diagram of Tc514400J/Z. In "Test Node", the mx 4 DRAM can be tested as If it
were a 5121(x 4 DRAM.
"WW, m- Before TiM-Refresh Cycle puts the device into "Test Mode". Arid
"CTS Before MT Refresh. Cycle" or ""RTS Only Refresh Cycle" puts it back ,into "Normal
Mode". In the Test Mode, "WiTTE, EK§ Before 1iiiir Refresh Cycle" Performs the refresh
operatioh with the internal refresh address counter. The "Test Mode" function re-
duces test times (1/2 in case of N test pattern).
TC51 440tulz-80
TC51 440NM-1 o
BLOCK DIAGRAM IN Th'ir TEST MODE
---',"f v00
--o I Normal
A00 A h
Normal --4Ns9---- S12E tnoee - v-JD’ 01031:
o----,. A
Vol -osc 1/01
Test A00 B
--0sGF------ 5121: block l T0”
3 E>----eel';
D I Normal
-------et Vcc
o Normal
A00 C .
Normal -
. F Test
1/02 --x2e, V02
Test 5C D
--os4 512K block C, Test
5 ID------??;'','-,
TNormal
A00 It
' A00 0°
---0 I Normal
N 1 A06 E '
orma -osd [ 5121: block - *4 0"
_ o--, E
1/0: -'se 1/03
Tact - A0 512K block . Test
E F )Er----ec';'';
normal.
I ' A00
DAOO Vcc
--o I Normal
Normal A00 5121: block 0 --tr--i-,ir:t-l
c -ehv-- Tr Test
Vos '--oso 1/04.
Test A00 H
-Korma.
Fig. 1
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