TC514400AZL-60 ,60 ns, 4-bit generation dynamic RAMfeatures include single power supply of SVi 10% tolerance, direct
interfucmg CupnbiliLy with high ..
TC514400AZL-70 ,70 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization . Low Power
. Fast access time and cycle time 550 ..
TC514400AZL-70 ,70 ns, 4-bit generation dynamic RAM1,048,576 WORD x4 BIT DYNAMIC RAM PRELIMINARY
DESCRIPTION
The TC514400APL/AJvASJLAZL is the n ..
TC514400AZL-80 ,80 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization . Low Power
. Fast access time and cycle time 550 ..
TC514400AZL-80 ,80 ns, 4-bit generation dynamic RAMABSOLUTE MAXIMUM RATINGS
Input Voltage LLiiiLLLCECCE-ECCECiiCCTCriTT
Output Voltage Vour
Pow ..
TC514400Z-10 ,100 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization . Low Power
. Fast access time and cycle time 578 ..
TC7WBL126FK ,Bus SwitchTC7WBL126FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TENTATIVE TC7WBL126FK Dua ..
TC7WBL3306CFK ,General-purpose bus switchabsolute maximum ratings and the operating ranges. Please design the appropriate reliability upon r ..
TC7WG00FC ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 mm × 25.4 m ..
TC7WG04FC ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 mm × 25.4 m ..
TC7WG04FK ,L-MOS LVP seriesabsolute maximum ratings Note 2: High or Low State. Do not exceed I Start of commercial productionO ..
TC7WG08FC ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 mm × 25.4 m ..
TC514400AZL-60
60 ns, 4-bit generation dynamic RAM
1,048,576 WORD X4 BIT DYNAMIC RAM
DESQBIPTION
This is advanced information and speeifica-
tions are subject to change without notice.
The 'F(5rjTiT0nAPL/AgL,iASJL/AzL is the new generation dynamic RAM organized 1,048,576 words by
4 bits. The '1‘C5l4400APL/AJL/ASJL/AZL utilizes TOSHIBA'S CMOS Silicon gate process technology as
well as advanced circuit techniques to provide wide operating margins, both internally and to the
system user.
Multiplexed address inputs permit the TC514400APL/AJL/ASJL/AZL to be packaged in a
standard 20 pin plastic DIP, 26/20 pin plastic SOJ(300/350mil) and 20 pin plastic MP. The package
size provides high system bit densities and is compatible with widely available automated testing and
insertion equipment. System oriented features include single power supply of 5Vk 10% tolerance, direct
intermcmg cuprubilicy with high performance logic families such as Schottky TTL.
FEATURE§
. 1,048,576 word by 4 bit organization .
. Fast access time and cycle time
TCr4400ApUAjUASjUATL - 60
hum RAS Access Time 60ns
tnn Column Address .
Access Time 30ns
trsu: £23 Access Time 20ns
ISIC Cycle Time ttons .
{pg Fast Page Mode 0
gm Time 45ns o
. Single power supply of 5V;t10%
with a built-in Vin, generator
Low Power
660mW MAX. Operating
(TC514400APL/AJL/ASJL/AZL-60)
1.1mW MAX. Standby
Outputs unlatched at cycle end allows two-
dimensional chip selection
Read-Modify-Write, CES before 17tg refresh,
m-only refresh, Hidden refresh, and Fast
Page Mode and Test Mode capability
All inputs and outputs 'ITL compatible
1024 refresh cycles/128ms
Package TC514400APL : DIP20-P-300C
TC514400AJL : SOJ26-P-350
TC514400ASJL: S0J26-P-300A
TC514400AZL : ZIP20-P-400A
jiLd1Cip_l/StLf1A_lVl
PIN NAMES
A0--A9 Address Inputs (ft Output Enable
RAI; Row Address Strobe |/01~|/04 Data Input/Output
tpit' Column Address Strobe Vcc Power(+5V)
WRiTE Read/Write Input V55 Ground
EIN CONNECTION (TOP VIEW)
Plasm Df
1/0101
1/02 2
Whitt ,
RAHI 4
Plastic SC)) Plasm ZIP
6E1) r'“a§
vouj "
vssfzz' iii'
TiGcy- NO.2 CLOCK -
GENERATOR F-,
COLUMN COLUMN
A0 0’ ADDRESS 10> DECODER
Al 0+ BUFFERSUO) J s
ENSE AMP
A? o- REFRESH IIO GATE
A3 cy- CONTROLLER -
A4 0’ _ t024 .
AS tr- REFRESH
A6 o- 0 coumsauo) x
A72: now t g ' MEMORY
A8 ADDRESS ui)4, 8 um ARRAY
A90» 8UFFERSt10) J u LEA l024xl024x4
_ Non CLOCK _
TASO-- GENERATOR F---! suasmu: aIAs
IIOI IIOI V03 AM
O id O Cl
(j---"--))
DATA IN DATA OUT ‘06:
BU FFERS BUFFERS
GENERATOR
TC51 4400APL/AJ L/ASJ L/AZL-GO
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage V," - I--? v 1
Output Voltage Vout - l-7 v I
Power Supply Voltage Vcc - t--7 V I
Operating Temperature Town (H-PO "C I
Storage Temperature Tsm - SS~150 'C 1
Soldering Temperature . Time Tsomen 260 . 10 "C . sec 1
Power Dissipation PD 700 mW 1
Short Circuit Dutput Current low so mA 1
RECOMMENDED DC OPERATING CONDITIONS (Ta = 0--70''c)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES
Vcc Supply Voltage 4.5 5.0 5.5 V 2
Ihr, Input High Voltage 2.4 - 6.5 V 2
" Input Low Voltage - 1.0 - 0.3 V 2
TC51 4400APL/AJL/ASJ L/AZL-60
DC ELECTRICAL CHARACTERISTICS (Vcc = 5V t 10%, Ta = 0~70°c)
SYMBOL PARAMETER MIN, MAX. UNITS NOTES
OPERATING CURRENT 3, 4
tcc, Average Power Supply Operating Current TcS1M00APL/AJUASjUAzL-60 - 120 mA
(EAT, tas, Address Cycling: tstcrctirc MIN.) 5
STANDBY CU RRENT
ICC? Power Supply Standby Current - 2 mA
(RTS = tT/G = VIH)
TAT ONLY REFRESH CURRENT
(:0 Average Power Supply Current, TOG Only Mode TcsmaoonPL/AJL/ASJUAZL»60 - 120 mA 3, S
(m Cycling, €76:th tnc=tR¢ MIN.)
FAST PAGE MODE CURRENT
Average Power Supply Current, Fast Page Mode TC51M00APuAJUAS)UAi60 - 70 mA
Itca (R'KSwu, TAS, Address Cycling: map; MIN.) 5
STANDBY CU RRE NT
lccs Power Supply Standby Current - 200 pA
(R73: m = Vcc - 0.2V)
tTG BEFORE RTA? REFRESH CURRENT
lcca Average Power Supply Current, it73- Before RAS TC514400APt.fAjLfASJUAi60 - 120 mA 3, 5
Modum, CAS Cycling: tgc=tRc MIN,)
8attery Back Up Current
Average Power Supply Current, Battery Back Up Mode
lccr (EKfmm Before R73 Cycling or 0.2V, t5tuucc-0nv, W=Vcc- - 400 pA 3, 6
0.2V, Athi-Vcc-thav or 0.2V, IlO1~4=Vcc- 0.2V,
0.2V or OPEN : tRc=125ps, tRAs= 300ns-lps)
Battery Back Up Current
Average Power Supply Current, Battery Back Up Mode
" (C13 = C3? Before AWS' Cycling or 0.2V, tTE=ucc- 0.2V, W=Vcc- - 300 pA 3, 6
0.2V, AO~9 = Vcc - 0.21/ or 0.2V, |IOI~4 = Vcc - 0.2V,
0.2V or OPENS tstc=125ps, IRAS=IRAS MIN. -300ns)
. INPUT LEAKAGE CURRENT
I. (L) Input Leakage Current, any input - 10 10 HA
(OVEVINSGJV, All Other Pins Not Under Test=0V)
OUTPUT LEAKAGE CURRENT
I .-1 1
O ic) (Dow is disabled, ovsvomsssw i) o pA
V OUTPUT LEVEL 2 4 V
Crm Output "H" Level Voltage(lou1= - 5mA) . -
OUTPUT LEVEL
V - 0.4 v
m Output "L" Level Voltage(louT=4.2mA)
TC51 4400APL/AJL/ASJ L/AZL-BO
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc=5Vt10%, Ta=0--70oc)(Notes 7, 8, 9)
TC514400APUAJUASJUAZL-60
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
tttc Random Read or Write Cycle Time 110 - ns
tmw Read-Modify-Write Cycle Time 165 - ns
trc Fast Page Mode Cycle Time 45 - ns
tpmw ttl,'';?,,',',,'"" Read-Modify-Write 100 - ns
tstat: Access Time from m - 60 ns "ods
1CAC Access Time from (ES - 20 M 10,15
tAA Access Time from Column Address l - 30 ns 10,16
tora Access Time from m Precharge - 40 ns It)
tCLz m to output in Low-? 0 - ns 10
ttws Output Buffer Turn-off Delay i) 20 ns 11
tr Transition Time(Rise and Fall) 3 50 ns 9
tap m Precharge Time 40 - ns
(M5 TOG Pulse Width 60 10,000 ns
tttaw m Pulse Width(Fast Page Mode) 60 200,000 ns
tag” ATG Hold Time 20 - ns
tttHot (il)?,] Hold Time From a_s Precharge 40 - ns
ast Page Mode)
15... ET: Hold Time 60 - ns
tou 53 Pulse Width 20 10,000 ns
taco TAT to m Delay Time 20 40 ns 15
tmo m to Column Address Delay Time 15 30 ns 16
tce m to m Precharge Time 5 - ns
tcp CAT Precharge Time 10 - ns
. usn Row Address Set-Up Time 0 - ns
tn" Row Address Hold Time 10 - ns
tasc Column Address Set-Up Time 0 - ns
chH Column Address Hold Time 15 - ns
tttac Column Address to -ttVG Lead Time 30 - ns
tats Read Command Set-Up Time 0 - ns
tam Read Command Hold Time 0 - ns 12
T051 4400APL/AJ L/ASJL/AZL-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Continued)
TCS 14400APUAlUASJtJAzL-60
SYMBOL PARAMETER UNITS NOTES
MIN. MAX.
Read Command Hold Time referenced
IRRH -.-- 0 - ns 12
to RAS
IWCH Write Command Hold Time 10 - ns
twp Write Command Pulse Width 10 - ns
IRWL Write Command to AA-s Lead Time 20 - ns
lcw1 Write COmmand to TM Lead Time 20 - ns
tos Data Set-up Time 0 - ns 13
IDH Data Hold Time 15 - ns 13
mar Refresh Period - 128 ms
twcs Write Command Set.UP Time t) - ns 14
1cwo CE to WRITE Delay Time 50 - ns 14
1.ng Tis- to WWE- Delay Time 90 - ns 14
inwo Column Address to WTtWt" Delay Time 60 - ns 14
[(pwo C". Precharge to WRITE Delay Time 70 - ns 14
tTG Set-Up Time
tcw - - 5 - n5
(CAS before RAS Cycle)
t CAS Hold Time 15
- -_-- - ns
CHR (CAS before RAS Cycle)
tqiac R733 to TN; Precharge Time 0 - ns
ti; Precharge TimeitTM before ENS"
1cm 30 - ns
Cou nter Test Cycle)
tRos: RTS' Hold Time referenced to US 10 - ns
10m tFt' Access Time - 20 ns
tow a to Data Delay 20 - ns
t Output buffer turn off Delay Time 0 20 ns 10
t35? from tyt"
ton. Tyt- Command Hold Time 20 - ns
t Write Commamd Set-Up Time 10
WTS (Test Mode In)
1 Write Commamd Hold Time 10
WTH (Test Mode In)
t WRTTE to R73; Precharge Time 10
- - - ns
WRP (CAS before RAS Cycle)
t WRWE to AW; Hold Time 10
_ - - __ - ns
WRH (CAS before RAS Cycle)
TC51 4400APL/AJL/ASJ L/AZU60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE
TEST MODE
TC5144OOAPUAJUASJL/AZL-60
SYMBOL PARAMETER UNITS NOTES
MIN. MAX,
tra: Random Read or Write Cycle Time 115 - ns
ttrc Fast Page Mode Cycle Time 50 - ns
tnAc Access Time from EAT - 65 ns "d'
tcac Access Time from tTAT - 25 ns 9,15
taa Access Time from Column Address - 35 ns 9,16
tcrux Access Time from GE Precharge - 45 ns 10
tm AAT Pulse Width 65 10,000 ns
mm» m Pulse Width (Fast Page Mode) 65 100,000 ns
tRsH m Hold Time 25 - ns
tcsn w: Hold Time 65 - ns
mm m Precharge to Ft7G Hold Time 45 - ns
tcas US Pulse Width 25 10,000 ns
tttAc Column Address to m Lead Time 35 - m
CAPACITANCE (Vcc = 5V t 10%, f=1MHz, Ta = 0~70°C)
SYMBOL PARAMETER MlN. MAX. UNIT
ci, Input CapacitanteiA0-A9) - S pF
Ce Input capatitanceiliM, TAT, WW. TR) - 7 pF
Co Irtputk)utput CapacitanteW01-WM) - 7 pF
TC51 4400APL/AJ L/ASJ L/AZL-60
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
All voltages are referenced to Vss.
ICCl. Iccs ICC4, Icce, Icc7 depend on cycle rate.
ICCI. ICC4 depend on output loading. Specified values are obtained with the output open.
Column address can be changed once or less while mam, and CKS=VIH.
$999030
teAs(max0---lps is only applied to refresh of battery-back up. tRAs(max.)=10ps is applied to
functional operating.
7, An initial pause of 200ps is required after power-up followed by 8 m only refresh cycles before
proper device operation is achieved. In case of using internal refresh counter, a minimum of 8
CRS before RAE refresh cycles instead of 8 KEg only refresh cycles are required.
8. AC measurements assume t'r=5ns.
9. V111 (min.) and VIL(max.) are reference levels for measuring timing of input signals. Also,
transition times are measured between 1% and VlL.
10. Measured with a load equivalent to 2 TTL loads and lOOpF.
11. tor1,(max0and tosz(max.)define the time at which the output achieves the open circuit condition
and are not referenced to output voltage levels.
12. Either titCH or tmm must be satisfied for a read cycle.
13. These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading
edge in Read-Modify-Write cycles.
14. tWCS, tnwo, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If twcs2. twcs(min.), the cycle is an early
write cycle and the data out pin will remain open circuit(high impedance) through the entire cycle;
If tani tuwl) (min.), towng tCWD (min.) , tAwogtAwp (min.) and tcemri2tcewo (min,) (Fast
Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from
the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data
' out(at access time) is indeterminate.
15. Operation within the tRCD(max.) limit insures that tlmc(max.)can he met.
tRCD(max.) is specified as a reference point only: If taco is greater than the specified tncn(max.)
limit, then access time is controlled by tCAc-
16. Operation within the tRAmmax.) limit insures that time (max,) can be met.
tRAD(max.)is specified as a reference point only: If tam) is greater than the specified tRAD(max.)
limit, then access time is controlled by tAA.
TC514400APL/AJL/ASJL/AZL-60
READ CYCLE
A0--A9 COLUMN
v01 l/OH----
AT _ T
~l104 Vor--- D A on
.: "H" or "L"
TC51 44OOAPL/AJ L/ASJ L/AZL-60
WRITE CYCLE (EARLY WRITE)
A0-A9 COLUMN
v01 VIH - _
- DATA - IN
1/04 " -
Eg.. "H" or "l."
TC51 4400APL/AJ L/ASJ L/AZL-60
WRITE CYCLE (W CONTROLLED WRITE)
m-iT'''''"
COLUMN
"l, 4:2: .r--rrrrr)s-----aiiiiiiiiiiiieiiiic ci-iii; ('iiiiiiiiiiiiiiiiiiiiEiiiiiiiiiiiiiiiijii'i'
%1 "H" or "L"
TC51 4400APL/AJ L/ASJ L/AZL-60
READ-MODIFY-WRITE CYCLE
COLUMN
VI/OH---
DATA-IN
VI/OL -
I: "H'' or "L"
TC51 4400APL/AJL/ASJ L/AZL-60
FAST PAGE MODE READ CYCLE
Er. "H" or "L"
TC51 4400APL/AJ L/ASJ L/AZL-60
FAST PAGE MODE WRITE CYCLE
thr, -
A0--A9
[/01 V H
~|/O4 D N
El.. "H'' or "L"
TC51 4400APL/AJL/ASJ L/AZL-GO
FAST PAGE MODE REA0.M0DH?Y-WRITE CYCLE
" Dom? " Dom2 " DourN
ET. "H" or (
TC51 4400APL/AJ L/ASJ L/AZ L-60
HAS ONLY REFRESH CYCLE
li7G "C'.1r.',..-..' ‘x: teas y" fix
I-tsh'-'--- Pe,
tTM ::::_/ ”\J
AAAAA "t "_.raiiisiiiiisficcF'ig,
Note: WE, UE="H" or "L" Bil. "H" or "L"
CA5 BEFORE RAE REFRESH CYCLE
_ tn? _ tm, C,
Vm - . A fix
" LL...) " . \.._____
itapc:
tts ss/tr.-...---...-..,.,)'"-"))''-' Cyf& gt 'tij),';';'!',))),';' r'i',iii'ii',';4
-dr0rt" ::':W‘ L...CLC,l,
['gg. : "H'' or "L"
Note: tfE, A0--A9="H" or "L"
TC51 4400APL/AJ L/ASJ L/AZL-GO
HIDDEN REFRESH CYCLE (READ)
m 1:: :'_Ԥ_ titas 7f titts 'i,:...,.,::-,,,.:-,)"-"'--;,.,,
m:::: 'gg: :‘f\\ trtsrt 1% tor,
Wm 1v,yri'ii'i'i'i ’1‘ w -iiiii2isr' tiiiiiih'iiiiiiiiiiiiiiiiiiiir
TC51 4400APL/AJ L/ASJ L/AZL-60
HIDDEN REEFRESH CYCLE (WRITE)
PAS " _---"-"".')" /L :\___J!tm a..-', tm, 'c.
CNS' C; I-cj)':' iii'-;',; ’§\ 1/
A0--A9 j: :flwélow W ////////////%<
Wkrtt- "t ,tiiiiiiiiiiiiiiiiiiiiii" - -iiiszzzss,,s,irii
Tft" :2: :////////////////////////////////////////////////////////////%
"e/o, C" L" {m ///////////////////////////////////////
'ea.. "H" or "L'
TC51 4400APL/AJ L/ASJL/AZL-60
CES BEFORE RAS REFRESH COUNTER TEST CYCLE
A0-A9 COLUMN
READ CYCLE
I Ihr,
wm i E
vol VOH
~I/o4 VALID DATA-OUT
WRITE CYCLE
IIOI VIH -
~l/04 VALID DATA - IN
. READ-MODIFY-WRITE CYCLE TCWD
IIOI VIIOH~
VIIOI. -
VALID DATA . OUT
Eiil: "H'' or "L''
TC51 4400APL/AJ L/ASJ L/AZL-60
WRITE, GAS BEFORE RAE REFRESH CYCLE
Itaf :1: I, tea, 7* m' c,
t7T :;::_/ "x: 7 ‘ , sttfs'
ih7firtt" _/r-resists,.?:---'- EtttigtttttttiiiiiitiiiEEEiE
I 4 ----.
VOL L---..:,
',bCftt'w, .. "H" or "L"
Note: UE, AO-AO.. "H" or "L"
TC51 4400APL/AJ L/ASJL/AZ L-60
TEST MODE
The TC514400APL/AJL/ASJL/AZL is the RAM organized 1,048,576 words by 4 bits, it is internally
organized 524,288 words by 8 bits. In "Test Mode", data are written into 8 sectors in parallel and
retrieved the same way. Aoe is not used. If, upon reading, two bits on one I/O pin are equal (all "I"s or
''0"a), the I/O pin indicates a"I".
If they were not equal, the I/O pin would indicate a "ty'. Fig.1 shows the block diagram of
'N514400APL/AJL/ASJL/AZL, In "Test Mode", the IMX4 DRAM can be tested as it it were a512KX4
“WRTTE, tWI Before m Refresh Cycle puts the device into'Test Mode". And"OM Before m
Refresh Cycle" or “m Only Refresh Cycle"puts it back into"Norma1 Mode". In the Test Mode,
"WMM, CKS Before m Refresh Cycle"Performs the refresh operation with the internal refresh
address counter. The "Test Mode"funetion reduces test times(1/2 in case of N test pattern).
TC51 4400APL/AJL/ASJ L/AZL-60
BLOCK DIAGRAM IN THE TEST MODE
Aoc Vcc
Aoc A \ 1Normal I
Normal -asds------ 512K block _) T st
CF---- K e
1/01 ---
Test 512K block " Test
: se.: g )rD--t'iil,,,-i
------o Normal
-----o ,
Aoc Vcc
Aoc C y 1Norma!
Normal -'w---- 512K block 3 a I
Cy----- t
l/O2 "k, 7irc- D l/O2
Test _ ss- 512K block ED Test
------0 Normal
-------o '
Aoc Vcc
Aoc E lNormal
Normal 512K block ._> T t
Ch----. E es
1/03 '--dN h7: F I/03
Test - 512K block 3 Test
"c ' ED-tii',',,,-)
---o iNormal
-----0 A
Aoc Vcc
. ADC G \ lNormal
Normal o---- tT es
I/Ot ---e8 .._.
C) Aoc H P04
Test 's. 512K block ' Test
F --)rD-----i''ils
?_.o I Normal
-------o ,
Fig. 1
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