TC514400AZL-70 ,70 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization . Low Power
. Fast access time and cycle time 550 ..
TC514400AZL-70 ,70 ns, 4-bit generation dynamic RAM1,048,576 WORD x4 BIT DYNAMIC RAM PRELIMINARY
DESCRIPTION
The TC514400APL/AJvASJLAZL is the n ..
TC514400AZL-80 ,80 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization . Low Power
. Fast access time and cycle time 550 ..
TC514400AZL-80 ,80 ns, 4-bit generation dynamic RAMABSOLUTE MAXIMUM RATINGS
Input Voltage LLiiiLLLCECCE-ECCECiiCCTCriTT
Output Voltage Vour
Pow ..
TC514400Z-10 ,100 ns, 4-bit generation dynamic RAMFEATURES
. 1,048,576 word by 4 bit organization . Low Power
. Fast access time and cycle time 578 ..
TC514400Z-80 ,80 ns, 4-bit generation dynamic RAMELECTRICAL CHARACTERISTICS (Vcc=5VilOZ, Ta-Om70°C)
SYMBOL PARAMETER 'lf-riff)?,??''?,'??,]
Aver ..
TC7WBL3306CFK ,General-purpose bus switchabsolute maximum ratings and the operating ranges. Please design the appropriate reliability upon r ..
TC7WG00FC ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 mm × 25.4 m ..
TC7WG04FC ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 mm × 25.4 m ..
TC7WG04FK ,L-MOS LVP seriesabsolute maximum ratings Note 2: High or Low State. Do not exceed I Start of commercial productionO ..
TC7WG08FC ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTNote 4: Mounted on an FR4 board. 2(25.4 mm × 25.4 m ..
TC7WG125FK ,L-MOS LVP seriesabsolute maximum ratings. OUTNote 3: V < GND OUTStart of commercial production 2006-021 2014-03-01 ..
TC514400ASJL-70-TC514400AZL-70-TC514400AZL-80
100 ns, 4-bit generation dynamic RAM
7fesiWt9)Wttt'r'r's.?'i?,
1,048,576 WORD x4 BIT DYNAMIC RAM PRELIMINARY
DESCRIPTION
The TC5144OOAPL/AJIJASJIJAZL is the new generation dynamic RAM organized 1,048,576 words by
4 bits. The TC514400AP1AkJUAsJL/AZL utilizes TOSHIBA’s CMOS Silicon gate process technology as
well as advanced circuit techniques to provide wide operating margins, both internally and to the
system user. Multiplexed address inputs permit the TC514400APLlAJ12A8JvAZL to be packaged in a
standard 20 pin plastic DIP, 26/20 pin plastic SOJ(300/350mil)and 20 pin plastic ZIP. The package
size provides high system bit densities and is compatible with widely available automated testing and
insertion equipment. System oriented features include single power supply of 5Vi10% tolerance, direct
interfacing capability with high performance logic families such as Schottky TTL.
FEATURES
. 1,048,576 word by 4 bit organization . Low Power
G Fast. access time and cycle time 550mW MAX. Operating
(T0514400APLIAJIJASJ L/AZL - 70)
'c5eRt,''yiki/hsea 468mW MAX. Operating
. (TC514400APUAJvA8J0AZL-.80)
(RN; A7GAccessTime 70ns 80ns lOOns 413mW MAX. Operating
tAA Column Id.dress 3Sns Mns Sons (TC514400APvAJL/ASJLlAZL-10l
Access Time 1.1mW MAX. Standby
tcat m Arms Time 20ns 20ns 2Sns . Outputs unlatched at cycle end allows two-
hut Cycle Time 130ns 150ns 180ns dimensional chip selection
1pc Fast Page Mode 4 6 . Read-Modify-Write, CA3 before m refresh,
Cycle Time 5ns 50ns tms -only refresh, Hidden refresh, and Past
. Page Mode and Test Mode capability
. Sl_ngle i?otrtr.suyply “$711096 . All inputs and outputs 'ITL compatible
with a built-in VBB generator 1024 refresh cycles/128ms
. Package TC514400APL C DIP20.P-300C
PIN NAMES TC514400AJL I SOJ26-P-350
TC514400ASJL: SOJ26-P-300A
A0-A9 Address Inputs ug Output Enable TC5144OOAZL : ZIPZO-P-400A
m Row Address Strobe IIOI~II04 Data Input/Output
C53 Column Address Strobe Vcc PowerhSV) B_Lf)..filfilAtiR/yyl
WRITE Read/Write Input vs, Ground AM voz vos v04
Vrc Vs:
i1rLtLCy)tl....E,.CLlO_N (TOP VIEW) I om 'll 'tft, sts'' .05;
aurm u
Plastic DIP Plastic SOI Plastic ZIP WWW ' 1 '
. ttiT, --- ' no.2 CCOCK
s t/O3 'Fi L2" 0:: WW cmzuron
.:: 74" 1/04
" Ld tcr, . COLUMN coumu
[/02 "Cl L5" V01 A00. moms Joy otcoou
-== cc WHITE Atth- s-ll-uf--',.'-!.'-'-)-'.?.!-,., J SENS! AMP 4
m C-e' mi' Ag Mo- umm In an:
Atari,': tSI no. counmun 41
CY:', CE At Mo- t "R''
A2 J?:! " A3 Mo- mum
v 1 .3 " commune)
cc J5. " "
AS Tii " A4 new now tl . MEMORY
:3: C.it.tiAs "o- Aopms "txt. g 10:4 MAM
A731" -- Moo. wmmac) u c, IOZIIIDZOII‘
'39 As i o
no.1 CLOCK
WH‘ cmnwon suasmvrs ms
GINEMTOI
TC51 4400APL/AJ L/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ UAZL-80
TC51 4400APL/AJ L/ASJ L/AZL-1 o
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage " - I~7 V 1
Output Voltage Vour - _ V I
Power Supply Voltage Vcc - _ f. V 1
Operating Temperature Tom; o-ro 'C 1
Storage Temperature Tsro - 55~150 'C I
Soldering Temperature .Time Tsowga 260 . 10 'C we: 1
Power Dissipation Po 700 mW 1
Short Circuit Output Current low so mA 1
RECOMMENDED DC OPERATING CONDITIONS (Ta=0--70''c)
SYMBOL I PARAMETER MIN. TYP. MAX. UNIT NOTES
ve Supply Voltage 4.5 5.0 5.5 v T 2
" Input High Voltage 2.4 - 6.5 V 2
" Input Cow Voltage ' -1.0 - 0.8 V 2
TC51440oAPL/A0L/ASJL/AzL-70, TC51 4400APL/AJ L/ASJ L/AZL--80
TC51 4400APL/AJ L/ASJ L/AZL--1 O
DC ELECTRICAL CHARACTERISTICS (Vcc = 5V , 10%, Ta = 0--7ty'c)
SYMBOL PARAMETER MIN. MAX. UNITS NOTES
OPERATING CURRENT TcsumaruAjUASJUAzL-ro - 100 3, 4
km Average Power Supply Operating Current TCSMlOOAPUAJUASJUAlL-GO - 85 mA
(R35, CAT, Address Cycling: tacartttt MIN.) TCstM00An,fAluA$lVJub10 C, - 75 S
STANDBY CURRENT
icct Power Supply Standby Current - 2 mA
(m: CAT a Vm)
m ONLY REFRESH CURRENT TC51M00ApUANASJuAj70 - 100
'cca Average Power Supply Current, W Only Mode TC5ud00AtruAJuASJuAzU80 - 85 mA 3, 5
tRAT Cycling, m! VIM: trtcmtitt MIN.) tCStM00APuAluASJuAittt - "
FAST PAGE MODE CURRENT TCstM00N'utuUA$luAZL.N - 70 3 4
Average Power Supply Current, Fast Page Mode TCMM00AtruAJuAsluATb80 - 60 mA
Itts FG=vo ar, Address Cyding: tet:=te MIN) TCstM00tu'UJuVASn,fA2L.t0 - 55 s
STANDBY CURRENT
lccs Power Supply Standby Current - 200 FA
(m=m= V(c-OJV) .
USS BEFORE m REFRESH CURRENT TCStM0oAPuAJUASNAi70 - 100
Iccs Average Power Supply Current, a: Before m TCM"00Al'uAJUASIUAV - as M 3, s
Mode (1055. CAT Cycling: tn! inc MIN.) Tcstoaiveouuasvaa.uj - "
Battery Back Up Current
Average Power Supply Current, Battery Back Up Mode
Iccr (CBJXS Before m Cycling or 0.2V, UEavcc-ozv, WRITE-vcc- - 400 M 3. 6
0.2V, A0~9=Vcc- 0.2V or 0.2V, IIOI~4nV¢c- 0.2V,
0.2V or OPEN: tac" 12Sps, tu5=SOOns --lpsl
Battery Back Up Current
Average Power Supply Current. Battery Back Up Mode
(mam Before W Cydinit or 0.2V, UE-Vcc-OJV. TWftGvcc- - 300 M 3, 6
0.2V, A0~9 I VCC' 0.2V or 0.2V, U01~4 I Vcc- 0.2V,
0.2V or OPEN: tu- 12hss, ‘mnm MIN. ~300ns)
INPUT LEAKAGE CURRENT
I. WI Input Leakage Current. any Input _ -10 10 pA
(ovsvmsssv, All Other Pins Not Under Testsov)
OUTPUT LEAKAGE CU RRENT
o (U (ow is disabled, ovs vows s.sv;
-10 10 M
OUTPUT LEVEL
. 0" Output "H" Level Vo1tagetiour= - SmA) 2.4 v
OUTPUT LEVEL
OL Output "L" Level Vottageitour=4.2mA) 0.6 V
TC514400APL/AJL/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ L/AZL--80
TC514400APL/AJL/ASJL/AzU-1 o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc= 5Vt10%. Ta =0-70''cl(Notes 7, 8, 9)
TC$14400APU ' TC514400APU TC514400APU
SYMBOL PARAMETER AJUASJUAZL-7D AJUASJUAZL-SO AJLIASJUAZL-10 UNIT NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
inc Random Read or Write Cycle Time 130 - ISO - 180 - ns
IRMW Read-Modify-Write Cycle Time 185 - 205 - 245 - ns
tec Fast Page Mode Cycle Time " - so - 60 - n5
. irmw t'S1e,e,eMode Read-Modify-Write . 100 - 105 - 125 - ns
teat: Access Time from m - 70 - 80 - 100 ns "d/
lug Access Time from CK! - 20 - 20 - " ns 10,15
tagx Access Time from Column Address - 35 - 60 - . so ns 10.16
km Access Time from EATS Precharge - 40 - 45 - " ns 10
ml IE to output in Low-z 0 - 0 - o - ns 10
torr Output Buffer Turn-off Delay 0 20 0 20 0 20 ns 11
tr Transition TimeiRise and Fall) 3 50 3 50 , so ns 9
tap m Precharge Time 50 - 60 - 70 - ns
lug m Pulse Width 70 10,000 80 10,000 100 10,000 ns
tnsp m Pulse WidthiFast Page Mode) 70 200,000 80 200.000 100 200,000 ns
mu m Hold Time 20 - 20 - " - n:
tnucp 'e,'sttui1a,')"'m m Precharge 40 - 45 - " - ns
tau 35 Hold Time " - 80 - 100 - ns
ttas ES Pulse Width 20 10,000 20 10.000 25 10.000 ns
‘nco m to ea, Delay Time 20 50 20 60 " " ns IS
ttuso m to Column Address Delay Time " 35 IS 40 20 50 ns 15
tou, CM to m Precharge Time 5 - s - 5 - ns
to, US Precharge Time 10 - 10 - 10 - ns
. ma Row Address Set-Up Time 0 - 0 - 0 - ns
1am Row Address Hold Time 10 - 10 - IS - ns
tatt Column Address Set-Up Time 0 - 0 - I 0 - ns
tom Column Address Hold Time IS - 15 - 20 - ns
tsrav Column Address to m Lead Time 35 - 40 - 50 - ns
mcs Read Command Set-Up Time t) - 0 - - ns
tam Read Command Hold Time 0 - 0 - O - ns 12
TC5144OOAPL/AJL/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ L/AZL--8o
TC51 4400APL/AJ L/ASJ L/AZL--1 0
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Continued)
TC5 I 4400APU TC514400APU TC514400APL/
SYMBOL PARAMETER AJL/ASJUAZL-7O AJUASJUAZL-BO AJL/ASJUAZL-IO UNITS NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
IR“ 'tfa?'''"'""" Hold Time referenced 0 - 0 - 0 - ns 12
two, Write Command Hold Time 15 - 15 - 20 - ns
twp Write Command Pulse Width IS - 15 - F 20 - n5
tewc Write Command to m Lead Time 20 - 20 - 25 - ns
tot Write Command to as Lead Time 20 - 20 - " - M
to; Data Set-Up Time t) - 0 . - O - n: 13
ttv, Data Hold Time 15 - 1S - 20 - ns 13
tees Refresh Period - 128 - _ 128 - 128 ms
twt:s Write Command Set-UP Time 0 - 0 - t) - ns "
tcwo G; to W517! Delay Time 50 - SO - 60 - ns "
1m, 1m to W! Delay Time 100 - no - 135 - ns 14
toss, Column Address to WRITE Delay Time 65 - 70 - 85 ... ns "
tcpwo m Precharge to WRIT: Delay Time 70 - " - 90 - ns "
Se - i
tcsn 2, b:f:feTR;; Cycle) 5 - s - 5 - ns
tco m Hold Time " - " - 20 - ns
(GS before Tory Cycle)
tree m to m Precharge Time 0 - 0 - 0 - ns
m Precharge TimeteAT before m
‘ch Counter Test Cycle) 40 - 40 - 50 .. m
tttou m Hold Time referenced to tit 10 - 10 - 20 - ns
tosa TE Access Time - 20 - 20 - 25 ns
tOED 5: to Data Delay 20 - 20 - 25 - ns
. tott Output buffer turn off Delay Time 0 20 O 20 0 20 ns 10
from O?
too; O? Command Hold Time 20 - 20 - " - ns
Write mmam - um
twrs (Test Mia. In) d Set Up Ti e 10 - Ti) ..' 10 - ttt
tww Write Commamd Hold Time 10 .. 10 - 10 - m
(Test Mode In)
tvote Wrtm! to m Precharge Time 10 - IO - 10 - ns
tUG before m Cycle)
twitr4 Fr/TTT to m Hold Time 10 - 10 - It) - ns
(33 before m Cycle)
TC51 4400APL/AJ L/ASJ L/AZL--70, TC51 4400APL/AJ L/ASJ L/AZL--80
TC51 4400APL/AJ L/ASJ L/AZ L--1 0
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE
TEST MODE
TC514400APU TCSIMOOAPU TC514400APL/
SYMBOL PARAMETER AJLIASIL/AZLJO AJUASJUAZL-BO AJUASiUAZUt0 UNITS NOTES
MIN, MAX. MIN. MAX, MIN. MAX.
tnc Random Read or Write Cycle Time 135 - 155 -" 18S - ns
trww Read-Modify-Write Cycle Time 190 - 210 - 250 - n:
tre Fast Page Mode Cycle Time 50 - 55 - 6S - ns
trtwt tlac,'')',,',,,""'' Read-Modify-Write 190 - 210 - aio - ns
tug Access Time from m - 75 - 85 - 105 n: "d'
tcac Access Time from GE - 25 - 25 - 30 ns 9,15
ttus Access Time from Column Address - 40 - 45 - 55 ns 9,16
ttyu, Access Time from m Precharge - 40 - 50 - 60 ns to
tRag m Pulse Width " 10,000 " 10,000 105 10,000 n5
tttasp m pulse Width (Fast Page Mode) 75 100,000 M 200.000 105 200,000 ns
tes" R23 Hold Time 25 - " - 30 - ns
tcsn 35 Hold Time " - M - 105 - M
mm m Precharge to 19:: Hold Time AS - SS - 65 - m
tcas CAT Pulse Width 25 10,000 25 10.000 30 _ 10,000 ns
MAL Column Address to m Lead Time 40 - " - 55 - ns
tcwo m to W Delay Time 55 - 55 - 65 - ns 14
two m to WATT! Delay Time 105 - 115 - 140 - ns "
um) Column Address to WRTT'E Delay Time 70 - 7S - 90 - ns "
tcpwo UTE Precharge to Tmr' Delay Time " - 80 - 95 - ns "
tom 55 Access Time from - 25 - 25 - 30 ns
tow tie Command Hold Time 25 - 25 ... 30 - m
CAPACITANCE (Vcc = 5V i10%, f =1MHZ, Ta = tP-70'c)
SYMBOL PARAMETER MIN, MAX. UNIT
Cu Input CapatitanteiA0-A9l - 5 pf
cm Input CapacitantetkM, ES, WRITE, tm - 7 pF
co lnput/Output Capat:itancetl/O1-Ahtl - 7 pF
TC5144OOAPL/AJ L/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ L/AZL--8o
TC51 4400APL/AJ L/ASJ L/AZL-1 0
NOTES:
I. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
2. All voltages are referenced to Vss.
3. km. Icca. Icc4, Ices, Icc7 depend on cycle rate.
4. ICCI. ICC4 depend on output loading. Specified values are obtained iarith the output open.
5. Column address can be changed once or less while AM---vu, and CKS=vm.
6. .tRAs(max.)=1ps is only applied to refresh of battery-back up. tRAs(max.)=10ps is applied to
functional operating.
7. An initial pause of 200ps is required after power-up followed by 8 BIS only refresh cycles before
proper device operation is achieved. In case of using internal refresh counter, a minimum of 8
CAS before m refresh cycles instead of 8 m only refresh cycles are required.
8. AC measurements assume tiw-tins.
9. Vm (min.) and Vu, (max,) are reference levels for measuring timing of input signals. Also,
transition times are measured between Vm and Vu..
10. Measured with a load equivalent to 2 TTL loads and 100pF.
ll, toFNmax.) and tosz0nax0detine the time at which the output achieves the open circuit condition
and are not referenced to output voltage levels.
12. Either tncu or tmm must be satisfied for a read cycle.
13. These parameters are referenced to CM leading edge in early write cycles and to WRITE leading
edge in Read-Modify-Write cycles.
14. twcs, tan, tCWD, tAWD and tcpwo are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If twcsgtwcs (min). the cycle is an early
write cycle and thedata out pin will remain open cireuitthigh impedance) through the entire cycle;
If tawogmwn tmin.), tcwngtcwn (min.) ' tAWDgtAWD (min.) and tCPwnZtCPwn (min) (Fast
Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from
the selected cell: it neither of the above sets of conditions is satisfied, the condition of the data
out(at access time) is indeterminate.
' 15. Operation within the tncpimax.) limit insures that tmcknax.) can be met.
tRCD (max.) is specified as a reference point only: If taco is greater than the specified tncp(max.)
limit, then access time is controlled by tCAC.
16. Operation within the tRADunax.) limit insures that titACtmax0 can be met.
tnADUnax.) is specified as a reference point only: If tam) is greater than the specified truuotmax0
limit, then access time is controlled by tAA.
TC51 4400APL/AJ L/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ L/AZL-80
TC51440oAPL/A0L/ASJL/AzL-1 o
READ CYCLE
A0-A9 v COLUMN
~IIO4 VOL -
DATA - OUT
Ear, "H" or "L"
TC514400APL/AJ L/ASJ L/AzL--70, TC51 4400APL/AJ L/ASJ L/AZL--80
TC51 4400APL/AJ L/ASJ L/AZL--1 0
WRITE CYCLE (EARLY WRITE)
A0-A9 COLUMN
1101 w, -
~ll04 " - DATA- IN OPEN
gig-. "H" or "L''
TC51 4400APL/AJ L/ASJ L/AZL--70, TC51 4400APL/AJ L/ASJ L/AZL-80
TC51 4400APL/AJ L/ASJ L/AZL-1 o
WRITE CYCLE tt5E CONTROLLED WRITE)
Ao-A9 '"
COLUMN
v01 DATA- m
“*4/04 " -
gg.. "H'' or "L'
TC51 44OOAPL/AJ L/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ L/AZL--80
TC51 44tmAPL/AJL/ASJL/AZL-1 o
READ-MODIFY-WRITE CYCLE
A0-A9 COLUMN
t/t91 I/i/OH---
~IIO4 Vl/OL -..-
ET "H" or 'L'
TC51 4400APL/AJ L/ASJ L/AZL--N, TC51 4400APL/AJ L/ASJ L/AZL--80
TCti1440oAPL/A0L/ASJUAzL--1 o
FAST PAGE MODE READ CYCLE
uoa Vor, -
gig: "H" or "L"
TC51 4400APL/AJ L/ASJ L/AZL--70, TC51 4400APL/AJ L/ASJ L/AZL-80
TC51 4400APL/AJ L/ASJ L/AZ L-1 O
FAST PAGE MODE WRITE CYCLE
Er. "H'' or "L"
TC51 4400APL/AJ L/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ UAZL-80
TC51 4400APL/AJ L/ASJ L/AZL-1 0
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
A0-A9 IH
V -...
I/Ot-. Vuon --
1/04 ' -
't 0our1 " Dom? " DourN
gg.. "H" or "L"
TC51 4400APL/AJ L/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ L/AZ L-80
TC51 4400APL/AJ L/ASJ L/AZL--1 o
mrs ONLY REFRESH CYCLE
tase IRAN
AO-M 't _ Row t'iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii'ifiitiiiiiii)
Note: WRITE. UB="H" or "L"
CAg BEFORE KES REFRESH CYCLE
Eg.. "H'' or 'L'
Ihr, - " a
m " .__/ S,
-,trtec...,
tsuis '-c,irc"-i...,
55; _/
twar twnH
77NTT slh,y"Ci'iis'iiftiii
u01~ 'ar--'"'"""'"")
1/04 N,,:---..;
Note , GE, A0~A9=“H" or "L"
"Ti,i,jfif,i'if',jti,if,ffj, '',iji,ii(fjjif,fiifs'i; 'i,'iiiiii'ii,
Eiir. "H'' or "L''
TC51 4400APL/AJ L/ASJ L/AZL--70, TC514400APL/AJ L/ASJ L/AZL-80
TC51 4400APL/AJ L/ASJ L/AZL--1 o
HIDDEN REFRESH CYCLE (READ)
tgt Inc
m etr---t" tttas 'rl'''' ?\‘n tttAS J "ci,
m 2:152 ts, un, tom 'e-ll'--------
A0-A9 ::: m@<°$W////////////
wmc,ru,,isiiriasz)it l, (iiazzazzaaa,
3?: C."'.".].-,.] l ti':,':" /%//////W
"yl,o, l? Cl"'--------- tttAC m g DATA-OUT m si"?-------
's44f, 2 "H'' or "L''
TC51 4400APL/AJ L/ASJ L/AzL--70, TC5144MAPL/AJL/ASJL/AzL-80
TC51 4400APL/AJ L/ASJ L/AZL-1 o
HIDDEN REEFRESH CYCLE (WRITE)
m rr.-------';" tpas m / tlo S. teat " k _,tetr \_
AAAAA ::: %@°
WRITE :1: coisiaisiiiiii, tw,,twc" ..,,,,/'" / w"'' /'1gi'i' be
o T..... oi''' ttm
Eil: "H" or "L"
TC51 4400APL/AJ L/ASJ LlAZL-70, TC51 4400APL/AJ L/ASJ L/AZL--80
TC51 4400APL/AJ L/ASJ UAZL-1 o
Chg BEFORE RES REFRESH COUNTER TEST CYCLE
Ihr, -
VII. -
A0~A9 COLUMN
READ CYCLE
77liiTT
um Von
L ~1/04 V VALID DATA-OUT
WRITE CYCLE
WRITE '"
IIOI " -
~IIO4 VALID DATA-IN
ts VIL -
READ-MODIFY-WRITE CYCLE
toso t
OS ttm
V01 Vvtm--
._.,04 VALID
vum - DATA-IN
VA D DATA . our
I: "H" or "L"
TC51 4400APL/AJ L/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ L/AZL-80
TC51 4400APL/AJ L/ASJ L/AZ L-I O
WRITE. CA3 BEFORE m REFRESH CYCLE
mar: 'N. tsuis / L_..,
wtzr: \I” "iiiiiiisaitiisst,itjiiii; iffiifjj,tit,'i' 'iftilii1 //%
Mmm? :rrjiaittigts" * "g,,,tis, ''jiiifjj,f'i'i(j,, /////// 'jiifififj.
Eiih "H'' or "L''
Note: UE, A0-A9'. "H" or "L"
TC51 4400APL/AJ L/ASJ L/ARL-N, TC51 44OOAPL/AJ L/ASJ L/AZL-80
TC51 4400APL/AJ L/ASJ L/AZL-c1 o
TEST MODE
The TC614400APvAJvA8Jh/AZL is the RAM organized 1,048,576 words by 4 bits, it is internally
organized 524,288 words by 8 bits. In "Test Mode", data are written into 8 sectors in parallel and
retrieved the same way. Aoc is not used. If, upon reading. two' bits on. one 110 pin are equal (all"I''s or
"0"s), the 1/0 pin indicates a"I''. '
If they were not equal, the I/O pin would indicate a "ty'.' Fig.1 (shows the block diagram of
TC5144OOAPL/AJL/ASJL/AZL. In "Test Mode", the 1Mx4 DRAM can be tested as if it were a512Kx4
DRAM. _
“WW. C213 Before R'A'S Refresh Cycle puts the device into'Test Mode". And "st Before m
Refresh Cycle" or “m Only Refresh Cycle" puts it back into "Normal Mode". In the Test Mode,
''WMllF, Wig Before m Refresh Cye1e"Performs the refresh operation with the internal refresh
address counter. The "Test Mode"function reduces test times(1/2 in case of N test pattern).
TC51 4400APL/AJ L/ASJ L/AZL-70, TC51 4400APL/AJ L/ASJ L/AZL-80
TC51 4400APL/AJ L/ASJ L/AZ L-I o
BLOCK DIAGRAM IN THE TEST MODE
--..-of)oc
Aac A Normal
Normal "KH- smc block “<74
o------ x
1/01 "N, L m B IIOI
Test 512K block . Test
a cy'_--s,:it,.:.,,
-.-.e, iNormal
-----o I
Aoc C 1Normal
Normal "se-- 5I2K block ucyr--q,?ts"-''H
o------ e
U02 -"'N, KC D U02
Test \° SIZK block x) Test
15 ED-tfir-,,-,
----o iNormal
------o
Aoc Vcc
-----.-o
Nc E Normal
Normal "se----- 512K block 'ED-ri,; I
w---- E
v03 'No- "ir-ic- F uoa
Test " 512K block " Test
'se r 'rD-ti'iis
L.r-, iNormal
Aoc Vcc
------o
Am: G 1Normal
Normal -'sf?--- sux block ,-E>--otf, I
C Ch---- 2:
VO Aoc H U04
Test - "s". SIIK block Test
IT 1ct:r,,iii'ia",
_° ciMormaI
Fig. 1
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