TC514101Z-10 ,100 ns, 1-bit generation dynamic RAMELECTRICAL CHARACTERISTICS (VCC-svnoz, Ta=0N70°C)
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PARAMETE ..
TC514101Z-10 ,100 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by 1 bit organization a Low power
. Fast access time and cycle time 57s ..
TC514260BFT-70 ,70ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMTOSHIBA
TC5 14260BJ /BFT-70/ 80
262,144 WORD X 16 BIT DYNAMIC RAM
DESCRIPTION
The TC514 ..
TC514260BFT-80 ,80ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMfeatures include single power supply of 5V:t 10% tolerance, direct
interfacing capability with hig ..
TC514260BJ-70 ,70ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMFEATURES KEY PARAMETERS
TC5 1 4260131
ITEM
'i_i-,t" s:,-',',',,',
Column Address 35ns
Acce ..
TC514260BJ-80 ,80ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMTOSHIBA
TC5 14260BJ /BFT-70/ 80
262,144 WORD X 16 BIT DYNAMIC RAM
DESCRIPTION
The TC514 ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)TC7W34FU/FK(UNDER DEVELOPMENT)The TC7W34FU is high speed CMOS BUFFER fabricated TC7W34FUwith silico ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)FEATURES TC7W34FK. High Speed ----tpd--6ns(Typ0 at VCC=5V0 Low Power Dissipation ... ICC-- 1PA(Max. ..
TC7W34FU ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)LOGIC DIAGRAM PIN ASSIGNMENT (TOP VIEW)(1) (7)a-dc ba,2A(5)(6)O)(2)2Y"l-2lp l-n"GND|4|| Lim,RECOMME ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC514101Z-10
100 ns, 1-bit generation dynamic RAM
4,194,304 WORD X "t BIT DYNAMIC RAll A This is advanced Information and specifications
are subject to change without notice.
DESCRIPTION
The TC514101J/T is the new generation dynamic RAN organized 4,194,304 words by 1
bit. The TCSl4lOlJ/Z utilizes TOSHIBA'S CMOS Silicon gate process technology as well
as advanced circuit techniques to provide wide operating margins, both Internally and
to the system user. Multiplexed address inputs permit the TCSlthlJ/Z to be packaged
in a standard 26/20 pin plastic SOJ and 20 pin plastic ZIP. The package size pro-
vides high system bit densities and is compatible with widely available automated
testing and insertion equipment. System oriented features include single power sup-
ply of 51lt10t tolerance, direct Interfacing capability with high performance logic
families such as Schottky TTL.
FEATURES
. 4,194,304 word by 1 bit organization , Low power
. Fast access time and cycle time 578mW Operating (Tc5141013/z-80)
TCil4lOlJ/Z-80/-10 495raTl Operating (TCSl4lOlJ/Z-10)
tRAC tTAT Access Time 80ns lOOns 5.5mH 'ef: Siazdby 1 d 11
. Out ut un atc e at c ce en a ows
tAA 22:22: hey'" 40ns SOns 't'e',.llhl'dCil'2"1' tlu'ys'/i'1'e'c"t"lo'l,
tCAC tts Access Time 20ns 25ns . Common I/O capability using "EARLY
tRC Cycle Time 150ns 180ns WRITE" operation -
th Nibble Mode tions 45ns . Read-rfod1fr"lr1te, TGT before RAS re-
Cycle Time fresh, RAS-only refresh, Hidden
refresh, Nibble Mode and Test Mode
. Single power supply of SthOZ with a
' _. capability
built 1n VBB generator . All inputs and output TTL compatible
. 1024 refresh cycles/16ms
. TOP VIEW
PIN CONNECTION ( ) . Package Plastic SOJ: TCSlthlJ
Plastic SOJ Plastic ZIP Plastic ZIP: 'N516101Z
" A9 "Tl ,-.
DOUT ji', L: m
DIN .E 'r.: VSS BLOCK DIAGRAM
Tat" 1y4 lia ifs” Wirig
N C -gl "
C:i,e, r 53 0.2233 D
A0 w 'il-l N.C. 36%;? IN
M a"- r-% At mama“ now
vcc 'ttn I11:“: A3 DATA our
Gun .16.A4 . BUFFER
A7 _1_93 r- ")
A8 A0 tr-- ADDRESS 11 ' COM
Al o-- BUFFERSOI) --. lat) DECODER
PIN ONES A2 H REFRESH - SENSE m
A0 N A10 Address Inputs A3 tc ccmnonuzn - f 1/0 aura ..
m Row Address Strobe ;;o_ k -4096-
DIN Data In 2; g: Ml?gi'la)
D D ca Out 10 E
OUT a A8o-- U iii MEMMY
i5M Column Address Strobe A92: now a 1024
T'irirt11" Read/Write Input AIO th"gii'u%, IO, iii l ARRAY
1lcc Power (+5V) f U a '
VSS Ground m - No.1 CLOCK - -
GENERATOR suasrm a BIAS Vcc
N.C. No Connection GENERATSR H Vss
A-1 37
TC5141 tMJ)Z-80
TC514101J/z--10
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTE
Input Voltage VIN ( 7 ll 1
Output Voltage Vouvr -1't, 7 v 1
Power Supply Voltage Vcc -1'u7 V 1
Operating Temperature TOPR 0s70 "c 1
Storage Temperature TSTG -55 'u 150 " 1
Soldering Temperature . Time TSOLDER 260 . 10 “C'sec 1
Power Dissipation PD . 600 EM 1
Short Circuit Output Current IOUT 50 mA 1
RECOMMENDED oc OPERATING CONDITIONS (Ta-O~70°C)
SYMBOL PARAMETER MIN . TYP . MAX . UNIT NOTE
VCC Supply Voltage 4.5 5.0 5.5 V 2
VIH Input High Voltage 2.4 - 6.5 v 2
VII, Input Low Voltage -1.0 - 0.8 V 2
oc ELECTRICAL CHARACTERISTICS (vctr5v-t10ro Tai70''C)
SYMBOL PARAMETER MIN. MAX. UNITS NOTES
OPERATING CURRENT TC51410tgi80 - 105
Iccl Average Power Supply Operating Current mA 3,4,5
(Tag, ieEr, Address Cycling: tRty''tRC MIN.) TCSHIOlJ/Z-lo - 90
STANDBY CURRENT
Iccz Power Supply Standby Current - 2 mA
(m=m=VIH)
RAS ONLY REFRESH CURRENT - -
ICC3 Average Power Supply Current, RAS Only Node TOSHIOU/z 80 105 mA 3,5
CErg Cycling, EE=VIH: tRC"tRC MIN.) TC514i01g.i10 - 90
NIBBLE MODE CURRENT -
ICCA Average POE Supply Current, Nibble Mode TC5t4t01g/Qr-80 60 mA 3,4,5
(mwu, CAS, Address Cycling: tNC=th MIN.) TC51410igpt-10 - 50
STANDBY CURRENT
Iccs Power Supply Standby Current - 1 mA
. (tThTr-=tTh%1rctr-0 . 2V)
t5irs- BEFORE m REFRESH CURRENT - TCSI‘IOIJ/Fso - 105
ICC6 Averais?ovttfupp1y Current, TgT Before RAS mA 3
Node (RAS, CAS Cycling: tchtRc MIN.) rcsuxou/z-lo .- 90
INPUT LEAKAGE CURRENT
Trtr,) Input Leakage Current, any input (OV§VIN§ 6.5V, A11 ~10 10 “A
Other Pins not under Test=0V)
100') OUTPUT LEAKAGE CURRENT
(1)01JT Is disabled, ovgvomg 5.5V) -10 10 ph
VOH OUTPUT LEVEL
Output "H" Level Voltage (Tour-Nah) 2.4 - ll
v OUTPUT LEVEL 4
Ol, Output "L" Level Voltage (IOUT'4-2m-A) - o. V
TC514101JM--80
TC514101J/z--.10
ELECTRICAL CHARACTERISTICS Allo RECOMMENDED AC OPERATING CONDITIONS
(vctr51rd:10T, Ta-O'h70°C) (Notes 6, 7, 8)
TC514101J/Z TC514101J/Z
SYMBOL PARAMETER -8tt -10 UNIT NOTES
MIN. MAX. MIN. MAX.
tRC Random Read or Write Cycle Time 150 - F, 180 - ns
tRNH Read-Modify-Write Cycle Time 175 - 210 - ns
tNC Nibble Mode Cycle Time " - 45 - ns
tNRMW Nibble Mode Read-Modify-ite Cycle Time 65 - 75 - ns
tRAC Access Time from tigig - 80 - 100 ns 9,14,15
tCAC Access Time from tTA-i)" - 20 - 25 ns 9,14
tAA Access Time from Column Address - 40 - 50 n5 9,15
tNCAC Nibble Node Access Time - 20 - 25 ns 9
tCLz 535 to Output in Low-Z 0 - - ns 9
tOFF Output Buffer Turn-off Delay 0 20 20 ns 10
" Transition Time (Rise and Fall) 3 50 50 ns 8
tRP Ttrt' Precharge Time 60 - 70 - ns
tRAS R-AT, Pulse Width 80 10,000 100 10,000 ns
tRSH tT7G Hold Time 20 - 25 - ns
tam 03 Hold Time 80 - 100 - ns
tCAs c-ig- Pulse Width 20 10,000 25 10,000 ns
tRCD "i'igT'9 to EK§ Delay Time 20 60 25 75 ns 14
tRAD EM to Column Address Delay Time 15 M 20 50 ns 15
tcm) EK§ to Tiiig Precharge Time 5 - 10 - us
top EK§ Precharge Time 10 - 10 -. ns
tASR Row Address Set-Up Time 0 - 0 - ns
tRAH Row Address Hold Time 10 ... 15 - ns
tAsc Column Address Set-Up Time 0 - 0 - ns
tcAH Column Address Bold Time 15 - 20 - n5
tAR Column Address Hold Time referenced to "iiTgt 60 - 75 - ns
tRAI, Column Address to EKS Lead Time 40 - 50 - ns
tRCS Read com1and Set-Up Time 0 - 0 - ns
tRCH Read Command Hold Time 0 - 0 - ns 11
tRRH Read Command Hold Time referenced to tTitT 0 - O - ns 11
twcn Write Command Hold Time 15 - 20 - ns
tHCR Write Command Bold Time referenced to -itTtif 60 - 75 - ns
twp Write Command Pulse Width 15 - 20 - ns
tRHI. Write Command to tTiG Lead Time 20 - 25 - n5
TC5141010/z-80
TC51 4101J/z--10
ELECTRICAL CHARACTERISTICS AND RECOMMENDED M OPERATING CONDITIONS (Continued)
TC514101J/Z TC514101J/Z
SYMBOL PARAMETER -80 -10 UNITS NOTES
MIN. 'ttAX. MIN. MAX.
tCHI, Write Command to eWLead Time 20. - 25 - tttt
tDS Data Set-Up Time il - O - us 12
tDH Data Hold Time 15 - 20 - ns 12
tDHR Data Hold Time referenced to FEE 60 - 75 - ns
CREF Refresh Period - 16 - 16 ms
CWCS Write Command Set-Up Time 0 - 0 - ns 13
tcm) ChT to WifTE Delay Time 20 - 25 - ns 13
tRWD EAT; to wire Delay Time 80 - 100 - ns 13
tAUD Column Address to WiTTE Delay Time 40 - 50 - ns 13
tCSR t2%T Set-Up Time (CM before R-gh" Cycle) 5 - 5 - ns
tCHR c-Ag Hold Time CCM before tiTftT Cycle) 15 - 20 - ns
tRPC Tair to Crit" Precharge Time 0 - 0 - ns
tCPT "eiyTU'rechargt..Eime _ 40 - 50 - m,
(CAS before RAS Counter Test Cycle)
tNCAS Nibble Mode Pulse Width 20 - 25 - ns
tNCP Nibble Mode t7tf Precharge Time 10 - 10 - ns
tNRSH Nibble Node TiEg Hold Time 20 - 25 - ns
tNCHD Nibble Mode CM to Tmrrif Delay Time 20 - 25 - ns
Nibble Mode Mtriig7Gamand to E? Lead
tNRWL Time 20 - 25 - ns
tNCWL ?:bble Node WiTTE Command to CIS Lead 20 - 25 - n3
tNTS Write Command Set-Up Time (Test Mode In) 10 - 10 - n8
tWTH Write Command Hold Time (Test Node In) 10 - 10 - ns
‘WRP J-gl-gut/il,'',,'?:):',','; me IO - 10 - “3
tHRH ‘WEEEE to "RTfrtItis.1d Time 10 - 10 - ns
(CAS before RAS Cycle)
TC5141ty1J/z--80
TC5141 old/z-IO
ELECTRICAL CHARACTERISTICS AND RECOMMENDED M OPERATING CONDITIONS IN THE TEST MODE
(vcc-svnoz, Ta-o~7o°0) (Note 6, 7, 8)
rcsuloulz TC516101J/z
SYMBOL PARAMETER ~80 . -10 UNIT NOTES
MIN. MAX; MIN. MAX.
tRC Random Read or Write Cycle Time 155 - 185 - ns .
CRAC Access Time from m - 85 - 105 ns 9,14,15
tCAC Access Time from m - 25 - 30 tttt 9,14
tAA Access Time from Column Address - 45 - 55 ns 9,15
tmxs rth""g Pulse Width 85 10,000 105 10,000 as
tnsa ‘RTs Hold Time 25 - 30 - ns
toga tTrg Bold Time _ 85 - 105 - n8
“ms tTirg Pulse Width 25 10,000 30 10,000 as
tRAL Column Address to tTiig Lead Time 45 - 55 - . n8
CAPACITANCE (Vcc-SVtIOZ, f=lMHz, Ta"0y 70''C)
SYMBOL PARAMETER MIN . MAX . UNIT
CIl Input Capacitance (AO'VAIO, DIN) - 5 pF
C12 Input Capacitance (m, BM, ihTtrt0 - 7 p1?
CO Output Capacitance (DOUT) - 7 pF
TC514101Jlz--8o
TC514101J/Z-10
NOTES:
l, Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All voltages are referenced to Irss.
3. TCCI, 1cc3, ICCA: ICCB depend on cycle rate.
tl. TCCI, ICC4 depend on output loading. Specified values are obtained with the
output open.
5. Column address can be changed once or less while §K§=VIL and EKS-VIH.
6. An Initial pause of 200us ls required after power-up followed by 8 Eig only
refresh cycles before proper device operation is achieved. In case of using
Internal refresh counter, a minimum of 8 CAS before RAS refresh eyelea Instead
of 8 RAS only refresh cycles are required.
7. AC measurements assume tT=5ns.
8. VIH(min.) and VIL(max.) are reference levels for measuring timing of Input
signals. Also, transition times.are measured between VIE and VIL.
9. Measured with a load equivalent to 2 TTL loads and lOOpF.
10. toFF(max.) defines the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
11. Either tRCH or tRRH must be satisfied for a read cycle.
12. These parameters are referenced to EKS Sleading edge in early write eyeles and
to WRITE leading edge in read-eodlfy-yrite, cycles.
13. tHCS, CRWD, tCHD and tAWD are not restrictive operating parameters.. Therare-
included in the data sheet as electrical characteristics only. If twcsz twcs
(min. ), the cycle is an early write cycle and data out pin will remain open
circuit (high impedance) through the entire cycle; If tRHDittmm0tdrt.),
' tam); tcwn(min. ) and cm): tAWD(min. ), the cycle ls a read-modify-write cycle and
data out will contain data read from the selected cell: " neither of the
above sets of conditions Is satisfied, the condition of the data out (at access
time) is indeterminate.
14. Operation within the tRCD(max.) limit insures that tRAc(max.) can be met.
(max.) is specified as a reference point only: If tRCD is greater than the
specified tRCD(max.) limit, then access time is controlled by tCAC.
Operation within the tRAD(max.) limit Insures that t c(max.) can be met.
tRAD(max.) is specified as a reference point only: ff tRAD is greater than the
specified tRAD(max.) limit, then access time is controlled by teg.
TC514101Jlz--8o
TC514101J/Z-10
TIN I NG low EFORMS
READ CYCLE
AO-AI tr
Dom~ -t.-.----..... VALID DA
WRITE CYCLE (EARLY WRITE)
Ttig IH
Ers" IH
VII. -
. A0--A10 VI" - ADDRESS
Dm VALID mm
VIL - t
BOUT VOL--- . " " tt u
m . H or L
TC5141010/Z--80
TC514101J/z--10
READ-MOD 1FY-HRITE CYCLE
AO-AI 0
DOUT VALID IMTA
/f2f t "H" or "L"
TC514101JM-8o
TC5141ty1J/z--10
NIBBLE MODE READ CYCLE
AO-AIO m
Finn IH
NIBBLE MODE WRITE CYCLE (EARLY WRITE)
TiM IH
tTi3 m
A0910 IH
. Yrt,
______ V
WRITE m
DTN vm YP man
Do T VOL
"H" or "L"
TC5141o1JM-80
TC514101d/z-10
NIBBLE MODE READ-MODIFY-W'RITE CYCLE
A0 A10 vm
V01! VALID ALID
Dour v DATA TA
': "H" or "L"
TC514101J/z-80
TC514101Jlz-10
rag ONLY REFRESH CYCLE
A0 .-A9
Vii) -fffy
-: "H" or "L"
WiTi"H" or "L" ' Alo-IIHII or "L"
TC514101J/Z-8o
TC5141ty1J/z-10
t5ii'tT BEFORE m REFRESH CYCLE
._.... vm -- tms
RAS / N, / ,
VIL -.-. tape
CP CSR term
i5if; vm - / N _f)f7ff)7jEg)))))f))))))))i7j)j'
VIL - y
tmu, twnu
va, -'""-"'-"''''"""-"'""t
BOUT r OPEN
VOL --------g,
NOTE: A0":A10=="H" or "L" -: "H" or "L"
TC5141 tMJ/Z-tX)
TC514101J/z-10 '
HIDDEN REFRESH CYCLE (READ)
VIH ----""'"_.. t t
- s RAS
ms m / \
tear tncn trum
- t F"-""-""
--- vm can
VII, - 'e
tmu) tRAL
tAsa tam use tcue
VIH -- . -
AO~AID / now COLUMN "lllllllllllllllllllllllllllllli.llllllllllllL
VIL - -
tRCS ‘m‘ tmu, twnn
VIH - -
VIL -..... tCAC
tmc tort
Dom _.""'-'-'"'""""'"-'-"'""'-"" VALID DATA
(t'L' ' "H" or "L"
A-1 49
TC514101Jlz--8o
TC514101J/z-10
HIDDEN REFRESH CYCLE (WRITE)
AO-AIO
vm ------"-q
VIH - a
vm *3332:
\ ttus / \ tms
CRP RCD l m tam
:‘TWWW/m twp //// kgssaggssi,
'tC'r-'"l]]]E[iEff[i)i, mm Ql0[lffllfll]illlfflllllffflllillL
val---.
7" "B" or "L"
TC5141ty1J)z--80
TC514101J/z--1 o
its BEFORE RAS REFRESH COUNTER TEST CYCLE
tms tgp
VII. ""
Vit. -
AO-AIO IH
" VII. -
READ CYCLE
Dour v - VALID DATA
- VIH -
WRITE CYCLE
_ Von -
MUTE IH
VII. -
DIN VALID mu
V11. -
REAgy-hi0DIFY-HRITE CYCLE t
ttua on
Von - -
Door v OPEN 4% VALID mm F---
OL - _
tAA tam,
tWRP tWRH t t
v - t--- 'a'"l AWD RM.
WRITE IH 222337 1llllllllll) tncs \ /
V11. -
tcwn twp
DIN v VALID mm
tDs th
ar. "H" or "L"
TC5141 old/Z-M
TC51 41 old/Z-IO
m, era BEFORE m REFRESH CYCLE
ITig / tape l tms /
-thRr 3::_/ (i'" tam /aiiaiaiiEEiia%EiJj'j'
voH -""--""-'i-
VOL -----..-a
NOTE: DIN. AONAlO: "H" or "L" ff/Cl I "H" or "L"
"rC514101JM-80
TC5141tMJ)z-10
READ CYCLE IN THE TEST MODE
V11. -
- vm -
A0 A10 vm .--.
MUTE m
vu, ---
D OH VALID DA
vor. ----
MUTE CYCLE (EARLY WRITE) IN THE TEST MODE
A0~A10 vm ..---
y -..-
WRITE m
V11. --
D VIH .q.q..-
w VALID mu
va, ---
DOUT - OPEN
l: "u" or "L"
A-1 53
TC514101J/z--80
TC5141ty1d/Z-1 0
APPLICATION INFORMATION
ADDRESSING
The 22 address bits required to decode 1 of the 4,194,304 cell locations within
the TCSl4101J/z are multiplexed onto the 11 address inputs and latched into the oh-
chip address latches by externally applying two negative going TTL-level clocks.
The first clock, the Row Address Strobe 0t%7), latches the 11 row address bits
into the chip. The second clock, the Column Address Strobe tem, subsequently
latches the 11 column address bits Into the chip. Each of these signals, EM, and
tar, triggers a sequence of events vhich are controlled by different delayed inter-
nal clocks.
The two clock chains are linked together logically in such a way that the ad-
dress multiplexing operation ts done outside of the critical path timing sequence
for read data access. The later events in the Chg clock sequence are inhibited
until the occurrence of a delayed signal derived from the Ex: clock chain. This
"gated tWy' feature allows the ttts clock to be externally activated as soon as the
Row Address Hold Time specification (CRAB) has been satisfied and the address Inputs
have been changed from Row address to Column address information.
DATA Illp0T/01JTPtJT
Data to be written into a selected cell ls latched Into an on-chip register by
a combination of wm and ear while iig'is active. The later of the signals Gfirfg
or 533) to make its negative transition is the strobe for the Data In (DIN) register.
This permits several options In the write cycle timing. In a write cycle, if the
Tlt1Ttg input ls brought low (active) prior to CET, the DIN is strobed trtCM' ahd the
set-up and hold times are referenced to ar. If the Input data is not available at
teirt- time or if it is desired that the cycle be a read-write cycle, the VKTTE signal
will be delayed until after c-AT has made its negative transition. “In this "delayed
write cycle" the data Input set-up and hold times are referenced to the negative
edge orTrert rather than tTM. (To Illustrate this feature, DIN is referenced to
WETTE in the timing diagrams depicting the read-write and nibble mode write cycles
while the "early write" cycle diagram shows DIN referenced to CM).
Data ls retrieved from the memory in a read cycle by maintaining WiTTE in the
inactive or high state throughout the portion of the memory cycle in which tTEtT 18
active (low). Data read from the selected cell will be available at the ouptut
within the specified access time.
TC5141ty1d)z--80
TC514101J)Z-1o
DATA OUTPUT CONTROL
The normal condition of the Data Output (DOUT) of the TC51610L1/2 is the high
impedance (open circuit) state. This is to say, anytime CM is at a high level, the
DOUT pin will be floating. The only time the output will turn on and contain either
a logic 0 or logic 1 ls at access time during a read éycle. DOUT will remain valid
from access time until CM ls taken back to the inactive (high level) condition.
NIBBLE MODE
Nibble mode operation allows faster successive data operation on 4 bits. The
first of 4 bits ls accessed in the usual manner with read data coming out at tCAC
time. By keeping EB low, tgg can be cycled up and then down, to read or write the
next three pages at high data rate. Row and column Address need only be supplied
for the first access of the cycles. From then on, the falling edge of EKE will
activate the next bit. After four bits have been accessed, the next bit will he
the same as the first bit accessed (wrap-around method).
(o, 0)-(0, 1)--HI, O-HI, 1)
Address A10 determines the starting point of the circular 4 bits nibble. Row A10
and column A10 provide the two binary bits needed to select one of four bits.
From then on, successive bits come out in a binary fashion; 00 + 01 + 10 +211 with
A10 row being the least significant address.
A nibble cycle can he a read, write, or delayed write cycle. Any combinations
of reads and writes or late writes will be allowed. In addition, the circular wrap-
around will continue for as long as 10rg ts kept low.
TM;" ONLY REFRESH
Refresh of the dynamic cell matrix is accomplished by performing a memory cycle
at each of the 1024 row address (A0sA9) within each 16 millisecond time interval.
Although any normal memory cycle will perform the refresh operation, this function
is most easily accomplished with "m-only" cycles.
TC5141tMJlz--80
TC5'141tyfJ)z--1 0
C s BEFORE EA? REFRESH
t"5A"T before liM refreshing available on the TCSlthlJ/Z offers an alternate
refresh method. If tgig is held on low for the specified period (tCSR) before tLTg
goes to low, on chip refresh control clock generators and the refresh address counter
are enabled, and an internal refresh operation takes place. After the refresh op-
eration is performed, the refresh address counter ls automatically incremented in
preparation for the next 5K3 before EiT refresh operation.
HIDDEN REFRESH
An optional feature of the TC514101J/Z is that refresh cycles may be per-
formed while maintaining valid data at the output pin. This referred to as Hidden
Refersh. Ridden Refresh is performed by holding 533 at VIL and taking fi7G high and
after a specified precharge period (tRp), executing a tTiG before "tWg refresh cycle.
(See Figure below)
MEM2RY CY C LE REFRESH CYCLE REFRE SH CYCLE
m """-""l r“
.m 0pm__( 3;
This feature allows a refresh cycle to be "hidden" among data cycles without
affecting the data availability.
TC51 41 O1 J/Z-Am
TC51 4'1010lz--10
cts BEFORE FITS- REFRESH COUNTER TEST
The internal refresh operation of TC514101J/Z can be tested by m BEFORE m
REFRESH COUNTER TEST. This cycle performs READ/WRITE operation taking the internal
counter address as row address and the Input address as column address.
The test is performed after a minim of 8 m before tag cycles as initializa-
tion cycles. The test procedure is as follows.
CD Write "0" into all the memory cells at normal write mode.
© Select one certain column address and read "0" out and write "1" in each cell
by performing CE BEFORE R-AT REFRESH COUNTER TEST (READ-WRITE CYCLE).
Repeat this operation 1024 times.
© Check "1" out of 1024 bits at normal read mode, which was written at Q).
C) Using the same column as © ' read "1" out and write "0" in each cell per-
forming a: BEFORE m REFRESH COUNTER TEST.
Repeat this operation 1024 times.
s Check "0" out of 1024 bits at normal read mode, which was written at o.
© Perform the above C) to (5) the complement data.
TC5141ty1Jlz-80
TC5141tyulz-10
TEST MODE
The TC514101J/Z ls the RAM organized 4,194,30h words by 1 bit, it ls internally
organized 524,288 words by 8 bits. In "Test Mode", data are written Into 8 sectors
in parallel and retrieved the same way. AlOR, A100 and Me. are not used. If, upon
reading, all bits are equal (all "l"s or "0"s), the data output pin indicates a "1".
If any of the bits differed, the data output pin would indicate a "0". Fig. 1 shows
the block diagram of TC514101J/Z. In "Test Mode", the till DRAM can be tested as If
it were a 512K DRAM.
”WKTTE, 'tsry Before FEE Refresh Cycle" puts the device into "Test Mode". And
"CKE Before m" Refresh.Cyc1e" or ''liEtT Only Refresh Cycle" puts it back into "Normal
Mode". In the Test Mode, 'Tiktig, EK§ Before §K§'Refresh Cycle" performs the refresh
operation with the internal refresh address counter. The "Test Mode" function reduces
test times (1/8 in case of tl test pattern).
TC514101J/Z-80
TC514101J/Z-1 o
BLOCK DIAGRAM IN TEST MODE
A10R,At0C,A0C
A1011, AIOC, AOC
512K block
A1 OR,A10C, A50
512K block
A1 0R,A15§,AOC
512K block
nomuocjo‘é
512K bi oek
"" Bout
MT E,A10C, AOC
512K block
-Artrri,Aiocarc"
512K block
AlOR,A15C,AOC
512K block
Normal
-AT0Tt,hT6e,Me
512K block
AIOR,A10C,AOC
Fig. l
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