TC514101AZ-80 ,80 ns, 1-bit generation dynamic RAMfeatures include single power supply of 5V:e10% tolerance, direct
interfacing capability with high ..
TC514101Z-10 ,100 ns, 1-bit generation dynamic RAMELECTRICAL CHARACTERISTICS (VCC-svnoz, Ta=0N70°C)
tiiiLlEAiuiWaiiiFsC,
—-'-n
' '
PARAMETE ..
TC514101Z-10 ,100 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by 1 bit organization a Low power
. Fast access time and cycle time 57s ..
TC514260BFT-70 ,70ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMTOSHIBA
TC5 14260BJ /BFT-70/ 80
262,144 WORD X 16 BIT DYNAMIC RAM
DESCRIPTION
The TC514 ..
TC514260BFT-80 ,80ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMfeatures include single power supply of 5V:t 10% tolerance, direct
interfacing capability with hig ..
TC514260BJ-70 ,70ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMFEATURES KEY PARAMETERS
TC5 1 4260131
ITEM
'i_i-,t" s:,-',',',,',
Column Address 35ns
Acce ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)TC7W34FU/FK(UNDER DEVELOPMENT)The TC7W34FU is high speed CMOS BUFFER fabricated TC7W34FUwith silico ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)FEATURES TC7W34FK. High Speed ----tpd--6ns(Typ0 at VCC=5V0 Low Power Dissipation ... ICC-- 1PA(Max. ..
TC7W34FU ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)LOGIC DIAGRAM PIN ASSIGNMENT (TOP VIEW)(1) (7)a-dc ba,2A(5)(6)O)(2)2Y"l-2lp l-n"GND|4|| Lim,RECOMME ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC514101AZ-80
100 ns, 1-bit generation dynamic RAM
4,194,304 WORD x 1 BIT DYNAMIC RAM PRELIMINARY
DESCRIPTION
The TC514101AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1
bit. The TC514101AP/AJ/ASJ/AZ utilizes TOSHIBA’s CMOS Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and to the system user.
Multiplexed address inputs permit the TC514101AP/AJ/ASJ/AZ to be packaged in a standard 18 pin
plastic DIP, 26/20 pin plastic SOJ (300/350mil) and 20 pin plastic ZIP. The package size provides high
system bit densities and is compatible with widely available automated testing and insertion
equipment. System oriented features include single power supply of 5Vi10% tolerance, direct
interfacing capability with high performance logic families such as Schottky 'ITL. The special feature
of TC511001AP/AJ/ASJ/AZ is nibble mode, allowing the user to serially access 4 bits of data at a high
data rate.
FEATURES
. 4,194,304 word by lbit organization 0 Low Power
0 Fast access time and cycle time 550mW MAX. Operating
TC514101AP/Al/AS)/A2 - 70/80/l0 (TC51410IAP/AJ/ASJ/AZ -70)
- . 468mW MAX. Operating
teat: RAS Access Time 70m 80ns 100ns (Tc514101AP/AJ/ASJ/AZ--80)
‘AA Column Address 413mW MAX. 0 eratin
. 35 40 50 P g
Iffy' Time ns m ns (TC514101AP/AJ/ASJ/AZ--10)
tcac CAS Access Time 20ns 20ns 25ns 5.limW MAX, Standby _
um Cycle Time 130ns 150ns 180m . Outputs unlatehetr at cycle end allows two-
mm Nibble Mode 20 dimensional chip selection
AccessTime ns 20ns 25tts 0 Common I/O capability using "EARLY
luc Nibble Mode WRITE" operation
Cycle Time 40ns 40ns Mns q B_ea_d-Modiry-Write, CM before m refresh,
. Single power supply of 5V:t10% m-only refresh, Hidden .rtrresh, Past Page
with a built-in V33 generator Mode and Test Mode capability
. All inputs and outputs TTL compatible
. 1024 refresh cycies/16ms
f.1l.tLt.1./yyLEf . Package TC514101AP : DIP18-P-300E
AO~A1O Address Inputs RIT Read/Write Input TC514101AJ : SOJ26-P-Mt)
TAT Column Address Strobe Vcc Power(+5V) ''1ig'n1t111t0,1dy 33%J26'P'300A
DIN Data In Vss Ground 51 01 . 20-P-400A
Dom Data Out NC. No Connection BLOCK DIAGRAM
m Row Address Strobe -.-.._-----.- o n
V t V '
PIN CONNECTION (TOP VIEW) , f ttWI/ 'tlt/ll"
. . W'm'! l J t I
. Plum DIP Plastic SOJ Plank ZIP
Nth? Ctt20t
" . sumo:
. COLUMN COL MN
ji' 2:; M? 02.21%, lil 5:33;;
”5:” 3:: -e'h'lllh, 'tttrAmrt6
ifs: M An» 2m
E1283“ 'd2
rfti " f.
-- no, new a umonv
"o- .693???” Tr v , g m uuuv
m HO.t tLoot
GENIM‘I’OK SUBWAY! Ill}
6ttttRATtNt
TC51 41 ty1AP/AJ/ASJ/AZ--70, TC51 41 01 AP/AJ/ASU/AZ-M
TC5141 o1AP/AJ/ASJ/Az-1 0
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage V... -1~7 V 1
Output Voltage Vour - _ V 1
Power Supply Voltage Vcc - _ V 1
Operating Temperature Ton (p-ro 'C 1
Storage Temperature TSTO - 55-450 'C 1
Soldering Temperature . Time Tsowgn 260- 10 'C . sec 1
Power Dissipation Po 700 mW 1
Short Circuit Output Current ‘OUT 50 mA 1
RECOMMENDED DC OPERATING CONDITIONS (Ta =0--70''c)
SYMBOL PARAMETER MIN, TYP. MAX. UNIT NOTES
Vcc Supply Voltage 4.5 5.0 5.5 V 2
V.“ Input High Voltage 2.4 - 6.5 V 2
" Input Low Voltage - 1.0 - 0.8 V 2
TC51 41 01 AP/AJ/ASO/AZ-N, TC51 41 01 AP/AJ/AN/AZ-tm
TC51 41 01 AP/AJ/ASO/AZ-l o
DC ELECTRICAL CHARACTERISTICS (Vcc = 5V i 10%, Ta = 0--70oc)
SYMBOL PARAMETER MIN. MAX. UNITS NOTES
OPERATING CURRENT "s"""""'"'",""" - 100 3, 4
1cm Average Power Supply Operating Current TC514101APIAJIASJIAl-80 - 85 mA
tfiM, UK, Address Cydin9: tathac MIN. l TCstM0tAFtAlfASltAbt0 - " 5
STANDBY CURRENT
1cce Power Supply Standby Current - 2 mA
(m .-.REG Vm)
m ONLY REFRESH CURRENT TCriat01tutttutASuaz-70 - 100
lco Average Power Supply Current, m Only Mode ’ICSMIOIAPIAJIASJIAZ-SO - 85 mA 3,5
(W Cycling, CKthI 1x<=tac MIN. , TCsi4t01AWAgfA53tAbul - "
mam; MODE CURRENT TCStMttUuVAJmSttAbr0 - 70 3,4
Icce Average Power Supply Current, Nibble Made TCM410tAl'tAJtASINt80 - 86 mA
(m‘VILr CET, Cycling: tNC=trtc MIN. ' TC$TM01N'tAltASltAbu7 - SS 5
STANDBY CURRENT
Iccs Power Supply Standby Current - 1 mA
(m: car, Vcc - 0.2V)
W BEFORE RAT REFRESH CURRENT TC51‘101AP/AHASNAl-70 - 100
lccs Average Power Supply Current, as tttfore RAT TCsu10tAWAJtAWAb8t) - 85 mA 3.5
MOUMW. m Cycling: #10 tet: MIN. ' Tcsumuvwmsuu-w - 75
. INPUT LEAKAGE CURRENT(any input except TF)
htc) Input Leakage Current, any input - 10 10 pA
(OVSVmS 6.5V, All Other Pins Not Under Test-OV)
OUTPUT LEAKAGE CURRENT
t - IO 10
DN (Dow is disabled, ovsvoms 5.5V) IIA
OUTPUT LEVEL
Von " . 2.4 - v
Output H Level Voltage (Iowa - SmA)
OUTPUT LEVEL
V - .4
Ot Output ( Level Voltage0ouro.2m/0 0 V
A-1 87
TC51 41 o1AP/AJ/AS0/Az--70, TC51 41 O1 AP/AJ/AN/AZ-tm
TC51 41 o1AP/AJ/ASJ/AZ-1 o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc = 5v , 10%, Ta = 0~70°c)(Notes 6, 7, 8)
TC514101APIAJ/AS} TC51410 IAPIAJ/ASJ TC514101APIAJ/ASl
SYMBOL PARAMETER /A2-70 "tfo /AZ.t0 UNIT NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
Inc Random Read or Write Cycle Time 130 - 150 _., 180 - n5
tnmw Read-Modify-Write Cycle Time 155 - 17S - 210 - ns
tNC Nibble Mode Cycle Time 40 - 40 - " - ns
1NRMW tlt,? Mode 1ead""dify Write Cycle 65 - 65 - 70 - m
tttac Access Time from m - h) - 80 - 100 n: ?'SM
ton: Access Time from m - 20 - 20 - 25 ns 9,14
taa Access Time from Column Address - 3S - 40 - 50 m 9,15
tNou: Nibble Mode Access Time - 20 - 20 - 25 ns 9
tcu m to Output in Low-Z - tl - - ns 9
toss Output Buffer Turn-off Delay 20 0 20 20 ns 10
tr Transition Time (Rise and Fall) 50 3 50 50 n: 8
to, F76 Precharge Time 50 - 60 - 70 - ns
IRAs m Pulse Width 70 10,000 80 10,000 100 10,000 OS
m5... m Hold Time 20 - 20 - 25 - ns
16,. m Hold Time 70 - so - 100 - ns
tcas m Pulse Width 20 10,000 20 10,000 25 10,000 n:
taco m to m Delay Time 20 SO 20 60 25 75 n: "
(m, m to Column Address Delay Time " 35 15 40 20 so ns 15
tae m to m Precharge Time 5 - S - 10 - ns
tcp 2733 Precharge Time 10 - 10 - 10 - ns
tate Row Address Set-Up Time 0 - t) - 0 - ns
t“... Row Address Hold Time 10 - 10 - IS - ns
tasc Column Address Set-Up Time 0 - 0 - O - ns
(CAM Column Address Hold Time 15 - 15 - 20 - n:
teat Column Address to 1053 Lead Time 35 - 40 - 50 - ns
tics Read Command Set-Up Time 0 - t) - 0 - ns
. lncu Read Command Hold Time referenced 0 - 0 - i) - ns 11
to CI:
“RH Read Command Hold Time referenced 0 - 0 - 0 - n 11
to m '
two, Write Command Hold Time " - ls - 20 - ns
twp Write Command Pulse Width 15 - 15 - 20 - ns
tam Write Command to m Lead Time 20 - 20 - 25 - ns
tcwc Write Command to 0?: Lead Time 20 - 20 - " - ns
tos Data-In Set-Up Time 0 - O - 0 - ns 12
TC51 41 o1AP/AJ/ASJ/AZ-70, TC51 41 o1AP/AJ/ASJ/AZ-80
TC51 41 o1AP/A0/ASJ/Az-10
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Continued)
TC514101AP/ ICSN‘IOIAPI TCSMIOIAPI
SYMBOL PARAMETER AJ/ASJ/AZ-7O AltASWW80 AJ/ASJIAZ-io UNITS NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
ton Data-In Hold Time 15 - Is' - t, 20 - ns 12
us: Refresh Period ... 16 - 16 - 16 ms
twcs Write Command Set-UP Time 0 - 0 - 0 - ns 13
ttwo m to WRITE Delay Time 20 - 20 - 25 - ns 13
tirwo m to WI Delay Time 70 - 80 - 100 - ns 13
(Am; Column Address to WEITE Delay Time 35 - 40 - 50 - ns 13
GE s t-U Ti
tcsn e p Ime S - 5 - 5 - ns
(as before m )
55 Hold Time
l5 - 15 - 20 - ns
tco (m before m ,
lkpc m Precharge to m Active Time 0 - 0 - 0 - ns
OTSP th eTime mb foam
tor re arg ' I e 40 - 40 - . so - ns
Counter Test ,
Inns Nibble Mode Pulse Width 20 - 20 - 25 - ns
thp Nibble Mode CAT Precharge Time ' 10 - 10 - 10 - ns
tnnsu Nibble Mode W Hold Time 20 - 20 - 25 - ns
Nibble Mode (33 to WE Delay
tucwo . 20 - 20 - 25 - ns
Nibble Mode WRIIE Command tom
tmum. . 20 - 20 - " - ns
Lead Time
Nibble Mode WRITE Command tom
tNCWL . 20 - 20 - 25 - ns
Lead Time
t Write Command Set-Up Time 10 10 10 n
wrt (Test Mode ln) s
t Write Command Hold Time 10 IO 10
WTH (Test Mode In) - - ns
Wlrth to1iMPrethargerime
twep 1O - IO - IO - n:
(m beforemCyde)
i t WiTITTtoWGHotdtime 10 10 10
WRH (m before m Cycle) - - - ru
TC51 41 01 AP/AJ/MJ/AZ-N, TC51 41 tMAP/AJ/ASO/Az-M
TC51 41 01 AP/AJ/ASU/AZ-l o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATION CONDITIONS IN THE
TEST MODE (Vcc = 5V , 10%, Ta = 0--7ty'Cl (Note6, 7, 8)
TC5t4101Apl TC514101AW TC514101API
SYMBOL PARAMETER AJ/ASJIAZ-70 AJ/ASJ/AZ-so AJIASJIAZ-10 _ UNITS NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
lac Random Read or Write Cycle Time 135 - 155 - 185 - ns
hoaw Read-Modify-Write Cycle Time 160 - 180 - 21S - n3
tgat: Access Time from TAT - 75 - 85 - 105 m mus
tcat Access Time from CAT - 25 - 25 - 30 ns 9,14
taa Access Time from Column Address - 40 - " - 55 m 9.15
Isms m Pulse Width " 10,000 85 10,000 105 10,000 n:
tag" as Hold Time 25 - 25 - 30 - ns
tcs" CET Hold Time 75 - BS - 105 - ns
tcas EAT Pulse Width 25 10,000 25 10,000 30 10,000 ns
tam, Column Address to R75 Lead Time 40 - " - " - ns
tcwo i7Ttoii7iTiTTdeuy Time 25 - 25 - 30 _ ns
titwo A7G to WT! Delay Time 75 - 8S - 105 - ns
tasso Column Address to WRTT'E Delay Time 40 - 45 - ss - ns
CAPACITANCE (VCC = 5V 1'10%, f =1MHZ, Ta = 0~70°C)
SYMBOL PARAMETER MIN MAX. UNIT
Cn Input Capacitance (A0~A10, DIN) - 5
Cu Input Capacitance (m, TM, WE) - 7 pF
Co Output Capacitance (Dow) - 7
TC514101AP/Ad/ASd/AZ-70, TC51 4101AP/AJ/ASJ/Az--80
TC51 41 01 AP/AJ/AN/AZ-I 0
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
2. All voltages are referenced to Vss.
3. Ian, Ices, Icc4, ICCG depend on cycle rate.
4. ICC1, Icc4 depend on output loading. Specified values are obtained with the output open.
5. Column address can be changed once or less While man, and twr--vm.
ii. An initial pause of 200ps is required after power-up followed by 8 RES only refresh cycles before
proper device operation is achieved. In case of using internal refresh counter, a. minimum of 8
Wig before HS refresh cycles instead of 8 m only refresh cycles are required.
7. AC measurements assume tr=5ns.
8. Vm (min,) and Vu, (max.) are reference levels for measuring timing of input signals. Also,
transition times are measured between vu, and V11,
9, Measured with a load equivalent to 2 TTL loads and lOOpF.
10. torr(max.)detines the time at which the output achieves the open'circuit condition and is not
referenced to output voltage levels.
11. Either tRCH or tan“ must be satisfied for a read cycle.
12. These parameters are referenced to m leading edge in early write cycles and to WRM5 leading
edge in read-write cycles.
13. twcs. tttwp, tcms, tAwn and tcpwp are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If twcsiittwtztrnin.), the cycle is an early
write cycle and data out pin will remain open eireuitihigh impedance) throughout the entire cycle;
If tamo2ittRvro(min0, tcwDkttcwnfmin0, tAwoittAwo0nin.) and tcrwo?-ttcPwoonirt.) (Fast Page
Mode), the cycle is a read-write cycle and the data out will contain data read from the selected
cell:' If neither of the above sets of conditions is satisraed, the condition of the data out (at access
time) is indeterminate.
14. Operation within the men (max.) limit insures that tRAC (max.) can be met.
tncmmax.) is specified as a reference point only: If tRCD is greater than the specified tnco(max.)
. limit, then access time is controlled by tCAC.
15. Operation within the tttAio0nax.llimit insures that time (max.) can be met.
tuAD(max.) is specified as a reference point only: If tRAD is greater than the specified tnAD(max.)
limit, then access time is controlled by tAA.
TC51 41 01 AP/AJ/MJ/AZ-N, TC51 41 o1AP/AJ/ASJ/AZ-80
TC5h4101AP/AJ/ASJ/Az--10
TIMING WAVEFORMS
READ CYCLE
Vm "--""-"""''f
_ " - -e
lnsu V
tTG " - /
tou, r i
"s), - ‘CAS
IASR ‘RAH I
Atv-Ast/irc.';?,;;';";'?,), ROW jstiy
7WITrE- 11,/rC,iifii'tiig f'tri,j,fjj'i
Dom OH OPEN
ttttrt:
tiii'Y
RiiiiiitE
DATA-OUT
ET "H" or "L''
TC51 41 01 AP/AJ/AN/AZ-N, TC51 41 o1AP/AJ/ASJ/Az--80
TC51 41 o1AP/AJ/ASd/Az-10
WRITE CYCLE (EARLY WRITE)
AO-AIO COLUMN
ths l DATA . IN
oow OPEN
'i4'it .' "H" or "L"
TC5141 o1AP/AJ/ASJ/AZ-70, TC51 4101AP/AJ/ASJ/Az--80
TC51 41 01 AP/Ad/ASO/AZ-l O
READ-MODIFY-WRITE CYCLE
AO-AIO _ COLUMN
DIN DATA. IN
Dour - DATA . OUT
Eg.. "H'' or "U'
TC51 41 O1 AP/AJ/AN/AZ-N, TC51 41 o1AP/AJ/ASJ/AZ-80
TC51 41 o1AP/AJ/ASJ/AZ-1 0
NIBBLE MODE READ CYCLE
m “M ----
A0~Alo VT
D Von DATA DATA
our VOL - om - OUT
W7? Ihr,
NIBBLE MODE WRITE CYCLE(EARLY WRITE)
Ao~AIo vi:
WRIIE V
ths Vlic
' VOH -
Dour VOL
(eg, : "H" or "L'
Tttsi 41 o1AP/AJ/ASJ/Az--70, TC51 41 01 AP/AJ/ASO/AZ-tm
TC51 4101AP/AJ/ASJ/AZ-10
NIBBLE MODE READ - MODIFY - WRITE
AO-AIO -
DIN IH
TC51 41 01 AP/AJ/AN/AZ-N, TC51 41 tll AP/AJ/AN/AZ-M
TC51 41 tMAP/AJ/ASO/AZ-l 0 ,
FAg ONLY REFRESH CYCLE
----S Ins .,r-'--'s
m - 't y R
tour 3:9:
taol tram
--A9 If _f'" Row 1etJtl,;
W/A : "H'' or "L"
Note: WHITE: "H" or "L" A10="H" or "L"
TC5141 01 AP/AJ/ASO/AZ-N, TC51 41 01 AP/AJ/AN/AZ-tm
TC51 41 o1AP/AJ/ASJ/AZ-1 O
CA3 BEFORE RM REFRESH CYCLE
VIL - ttoc 'c, 'sc....,,.
m 't :__/”"\r too gift;),': , 'jfiji,;'ijj4i,i',itijj', _ ',i'i,'iii'ij',ii,
twap twer, I
sv-mr','?--'--.)"';,;';'',;',)';)';-,),,:''' ///// // 'f,i,'iifiiijfj.
Vost---
our f om:
VOL -.-.---..'
Note: A0~A10="H" or "L" ET. "H" or "L''
TC51 41 01 AP/AJ/ASO/AZ-N, TC51 41 o1APaJ/ASJ/Az--8o
TC51 41 ty1AP/AJ/ASJ/Az-1 o
HIDDEN REFRESH CYCLE (READ)
m :3 L-f"""'"""'"') tst/xt f tep Jr-----'-''-.-
eas:,::rr.,.,/" ttut 1%: '
AO-AIO I:,':-:-.-:;:,,);)'). nélw AM 'e-li-ci,',-," WWW
DATA - OUT
Ea.. "H" or "L"
TC51 41 01 AP/AJ/MJ/AZ-ro, TC51 41 01 AP/AJ/AN/AZ-M
TC51 41 o1AP/AJ/ASJ/AZ-1 0
HIDDEN REFRESH CYCLE (WRITE)
m " S; 1M; J; 'ts,, tn;
" - "t n- -x l
-. taco -t tsts" 1:55 l
. Ant ¢//////////////////////////////////////
ihrRTTé 'tr-tiii/sister-tslr,,' -iv"twtCrgsii, 'ifjjiij'ifi, 'iiifrti,'iiij,, 'j;itifi'iif,,i'f,ff,
"fJit', .. "H'' or "L''
TC51 41 o1AP/A0/ASJ/Az--70, TC51 41 01 AP/AJ/AN/AZ-M
TC514101AP/AJ/ASJ/Az--1 0
CAS BEFORE RA§ REFRESH COUNTER TEST CYCLE
Ihr: -
A0--A9 COLU MN
READ CYCLE
Dom VALID DATA
VOL two 1.ng
WRlTE CYCLE
vort---
OUT VOL -
DIN VALID DATA
READ-MODIFY-WRITE CYCLE
Dour Von. - VALID DATA
cu 't :WWW Wm I-ii-sc-"-';"-,::-,:-;:"'''''''''';'''"''''' sf/sf,',
tos -'"liigr. "H'' or "L"
TC51 41 01 AP/AJ/AN/AZ-N, TC51 41 01 AP/AJ/ASU/AZ-tm
TC51 41 01 AP/AJ/ASO/AZ-l 0
WETTE, CAg BEFORE m REFRESH CYCLE
mat: ff S: '"', b 'su,
m :z::._/f’*\f’ tom ,WW/////// 'i)t'ji'fiitll'
WRITE :1: W/
Note: Dmyur-iud---m" or "L'' 8ft : "H" or 'W'
TC51 41 01 AP/AJ/AN/AZ-N, TC51 41 o1AP/AJ/ASJ/Az-80
TC51 41 o1AP/AJ/AN/Az-10
APPLICATION INFORMATION
ADDRESSING
The 22 address bits required to decode 1 of the 4,194,304 cell locations within the TC514101AP/AJIASJ/AZ
are multiplexed onto the 11 address inputs and latched into the on-chip address latches by externally applying
two negative going 'ITL-level clocks.
The first clock, the Row Address Strobe (RES), latches the 11 row address bits into the chip. The second
clock, the Column Address Strobe (6K3), subsequently latches the 11 column address bits into the chip. Each
of these signals, m, and CKS. triggers a sequence of events which are controlled by different delayed
internal clocks.
The two clock chains are linked together logically in such a way that the address multiplexing operation is
done outside of the eiitieal path timing sequence for read data access. The later events' in the Chg clock
sequence are inhibited until the occurrence of a delayed signal derived from the m clock chain. The "gated
CE" feature allows the CM clock to be externally activated as soon as the Row Address Hold Time
specification (tmn) has been satisfied and the address inputs have been changed from Row address to Column
address information.
DATA INPUT/OUTPUT
Data to be written into a selected cell is latched into an on-chip register by a combination of WRITE and
CES While m is active. The later of the signals (WRITE or Chg) to make' its negative transition is the
strobe for the Data In (Dm) register. This permits several options in the write cycle timing. In a write cycle,
if the WErrg input is brought low (active) prior to CM, the DIN is strobed by CKS and the set-up and hold
times are referenced to CM, If the input data is not available atm time or if it is desired that the cycle be a
read-write cycle, the Wsignai will be delayed until after tsrg has made its negative transition. In this
"delayed write cycle"the data input set-up and hold times are referenced to the negative edge of WRITE rather
than TAS. (To illustrate this feature, Dm is referenced mm in the timing diagrams depicting the read.
modify-write and nibble mode write cycles while the "early write"cycle diagram shows DIN referenced to
Data is retrieved from the memory in a read cycle by maintaining WRITE in the inactive or high state
throughout the portion of the memory cycle in which CKS is active (low). Data read from the selected cell will
be available at the output within the specified access time.
RATA OUTPUT CONTROL
The normal condition of the Data Output (DOUT) of the TCSl4101AP/AJ/ASJ/AZ is the high impedance
(open circuit) state. This is to say, anytime CXS is at a high level, the DOUT pin will be floating. The only
time the output will turn on and contain either a logic 0 or logic 1 is at access time during a read cycle. BOUT
will remain valid from access time until m is taken back to the inactive (high level) condition.
NlBBLE MODE
Nibble mode operation allows faster successive data operation on 4 bits The first of 4 bits is accessed in the
usual manner with read data coming out at tCAC time. By keeping m low, TM can be cycled up and then
down, to read or write the next three pages at high data rate (faster than tCAc). Row and column addresses
need only be supplied for the First access of the cycles. From then on, the falling edge aim will activate the
next bit, After four bits have been accessed, the next bit will be the same as the first bit accessed (wrap-
around method) .
TC51 41 01 AP/AJ/AN/Az-FO, TC51 41 o1AP/AJ/ASJ/AZ-80
TC51 41 01 AP/AJ/AN/AZ-I o
---i0,0l---t0,1)--it1.0)---t1,1)---
Address A10 determines the starting point of the circular 4 bits nibble. Row A10 and column A10 provide the
two binary bits needed to select one of four bits.
From then on, successive bits come out in a binary fashion; 00-'01-10-°11 with A10 row being the least
significant address.
A nibble cycle can be a read, write, or delayed write cycle. Any combinations of reads and writes or late
writes will be allowed. In addition, the circular wraparound will continue for as long as EM is kept low.
RAS ONLY REFRESH
Refresh of the dynamic cell matrix is accomplished by performing a memory cycle at each of the 1024 row
address (Air-At)) within each 16 millisecond time interval.
Although any normal memory cycle will perform the refresh operation, this function is most easily
accomplished with "RM-only" cycles.
t7G BEFORE R71? REFRESH
cra before m refreshing available on the TC514101AP/AJ/ASJ/AZ offers an alternate refresh method. If
FATS is held on low for the specified period (tcsn) before RAS goes to low," on chip refresh control clock
generators and the refresh address counter are enabled, and an internal refresh operation takes place. After
the refresh operation is performed, the refresh address counter is automatically incremented in preparation
for the next CA5 before m refresh operation.
HIDDEN REFRESH
An optional feature of the TC514101AP/AJ/ASJIAZ is that refresh cycles may be performed while
maintaining valid data at the output pin, This referred to BS Hidden Refresh. Hidden Refresh is performed by
holding TM at vu, and taking m high and after a specified precharge period (tap), executing a CM before
m refresh cycle. (see Figure below)
MEMORY CYCLE REFRESH CYCLE REFRESHCYCLE
'TN; fiJJLJ_
DOUT -- OPEN -d
This feature allows a refresh cycle to be "hidden" among data cycles without affecting the data avilability.
TC51 41 01AP/AJ/ASd/Az--70, TC51 41 O1 AP/AJ/ASJ/AZ-BO
TC51 41 01 AP/AJ/ASO/AZ-l 0
-t7G8EFORiir0GREFRESH COUNTERTiiST
The internal refresh operation ofTC514101AP/AJ/ASJ/AZ can be tested by CKS BEFORE m REFRESH
COUNTER TEST. This cycle performs READ/WRITE operation taking the internal counter address as row
address and the input address as column address.
The test is performed after a minimum of 8 UM before chycles yes initialization cycles. The test
procedure is " follows.
C) Write "0" into all the memory cells at normal write mode.
© Select one certain column address and read "0" out and write "I'' in each cell by performing tWI
BEFORE m REFRESH COUNTER TEST (READ-WRITE CYCLE) . Repeat this operation 1024
times.
© Chick "I'' out of1024 bits at normal read mode, which was written at © '
G) Using the same column as (2), read "I" out and write "0" in each cell performing m BEFORE m
REFRESH COUNTER TEST. Repeat this operation 1024 times.
© Check "o" out of 1024 bits at normal read mode, which was written at © .
© Perform the above C) to © to the complement data.
TC51 41 o1AP/AJ/ASJ/AZ-70, TC51 41 01 AP/Ad/AN/Az-tm
TC51 41 ty1AP/AJ/ASJ/AZ-1 o
TEST MODE
The 'N514101AP/Air/ASJ/AT is the RAM organized 4,194,304words by 1 hit, it is internally organized
524,288 words by 8 bits. In "Test Mode", data are written into 8 sectors in parallel and retrieved the same
way. A1012. A100 and AOC are not used. If, upon reading, all bits are equal (all "1"s or" O"s), the data output
pin indicates a "I". If any of the bits differed, the data outputpin would, indeate shows the block diagram of
TC514101AP/ASJ/AZ. In"Test Mode", the 4M DRAM can be tested as ifit were a 512K DRAM.
"WRITE t UM Before mrs Refresh Cycle" puts the device 'Test Mode'', And "CM Before ms Refresh
Cycle" or" m Only Refresh Cycle"puts it back into "Normal Mode".In the Test Mode, “WRITE. CE
Before 1523 Refresh Cycle" performs the refresh operation with the internal refresh address counter. The
'Test Mode" functiom reduces test times(1l8 in case of N test pattern)
TC51 41 o1AP/AJ/ASJ/Az--70, TC51 4101 AP/AJ/AN/AZ-M
TC51 41 tMAP/AJ/ASO/Az-l o
BLOCK DIAGRAM IN THE TEST MODE
A10R,AIOC,AOC
Normal
ATOR, AIOC. AOC
512K block
mommoc. T t
512K block "
AIOR.W.AOC
512K block
Attyt.7s5Te,
Test S12K block __ Dom
Normll MEKMOLADC
512K block
WAIOQW
512K block
mmm M Test
512K block
Normal
AKR, AIOC, NK
512K block
Fig. 1
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