TC514100J-10 ,100 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by 1 bit organization . Low Power
. Fast access time and cycle time 5 ..
TC514101AZ-80 ,80 ns, 1-bit generation dynamic RAMfeatures include single power supply of 5V:e10% tolerance, direct
interfacing capability with high ..
TC514101Z-10 ,100 ns, 1-bit generation dynamic RAMELECTRICAL CHARACTERISTICS (VCC-svnoz, Ta=0N70°C)
tiiiLlEAiuiWaiiiFsC,
—-'-n
' '
PARAMETE ..
TC514101Z-10 ,100 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by 1 bit organization a Low power
. Fast access time and cycle time 57s ..
TC514260BFT-70 ,70ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMTOSHIBA
TC5 14260BJ /BFT-70/ 80
262,144 WORD X 16 BIT DYNAMIC RAM
DESCRIPTION
The TC514 ..
TC514260BFT-80 ,80ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMfeatures include single power supply of 5V:t 10% tolerance, direct
interfacing capability with hig ..
TC7W32FU ,DUAL 2-INPUT OR GATELOGIC DIAGRAM TRUTH TABLE PIN ASSIGNMENT (TOP VIEW)2B(6)L2y2YiEl-, FIE”GNDITI %2ACHARACTERISTIC SYM ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)TC7W34FU/FK(UNDER DEVELOPMENT)The TC7W34FU is high speed CMOS BUFFER fabricated TC7W34FUwith silico ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)FEATURES TC7W34FK. High Speed ----tpd--6ns(Typ0 at VCC=5V0 Low Power Dissipation ... ICC-- 1PA(Max. ..
TC7W34FU ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)LOGIC DIAGRAM PIN ASSIGNMENT (TOP VIEW)(1) (7)a-dc ba,2A(5)(6)O)(2)2Y"l-2lp l-n"GND|4|| Lim,RECOMME ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC514100J-10
100 ns, 1-bit generation dynamic RAM
4,194,304 WORD X 1 BIT DYNAMIC RAY!
DESCRIPTION
The TCSlAlOOJ/Z is the new generation dynamic RAN organized tt,194,304 words by 1
* This is advanced information and specifications
are subject to change without notice.
The Tc51h100J/t utilizes TOSHIBA's CMOS Silicon gate process technology as well
as advanced circuit techniques to provide wide operating margins, both internally and
to the sy
stem user .
Multiplexed address inputs permit the TCSlthOJ/Z to be packaged
in a standard 26/20 pin plastic $03 and 20.pin plastic ZIP.’
The packagé size pro.-
vides high system bit densities and is compatible with widely available automated
System oriented features include single power supply
of 5Vt10r, tolerance, direct interfacing capability with high performance logic families
such as Schottky TTL.
testing and Insertion equipment.
FEATURES
. 4,19h,304 word by 1 bit organization
. Fast access time and cycle time
TC51ll100J/z--80/-10
tRAC RAS Access Time . 80ns lOOns
w 22:22: ()/t2ess m sens
tCAC CA3 Access Time 20hs 25ns
tRC Cycle Time 150ns 180as
CPC I,a,htep?fgrde sens eons
. Single power supply of SVilOZ with a
Low Power
550aN Operating (ic51k100J/Z-80)
468mw Operating (TC51k100J/2-10)
5.5mw MAX. Standby
Output unlatched at cycle end allows two-
dimensional chip selection
Common I/O capability using "EARLY WRITE"
operation
Read-Nodify-Hrite, i5irg before TCAT; refresh,
§K§Fonly refresh, Hidden refresh, Fast
Page Mode and Test Mode capability
built-in VBB generator . All inputs and output TTL compatible
. 1024 refresh cycles/l6ms
PIN CONNECTION (TOP VIHJ) . Package Plastic MJ: TC51h100J
-c. P1 ta' ' c 1410
Plastic SOJ .FIhstic ZIP as 1c ZIP T 5 02
a Vss 59’-E r"
2r.r, i2 m
D UT D bEe,
'l-i. 3g: :3 Ciilrtm BLOCK DIAGRAM
tf.?. WiiiiriE
N.C. "t =-
" Jf' "I'. [j A10 W30 " E:
. . tze, Cit). N.C. imrtr--- DATA IN DIN
A8 2: 9:11 {15: Al No.2 CLOCK BUFFER Door
AT s,1-ii' C1Digus GENERATOR , mu our --o
A6 Vccgg HéAa - . BUFFER
A5 A3 9;, ifii A6 1
At , -.. . =
AT Jf.? {awe m_ ll 33% n J 'ii';','',',,'',
PIN ONES AIO- Emma” =---c:r=.--uab
A20-- nmrnssn . - SENSE AMP,
AONIAIO Address Inputs AGO- ,CONTROLLER I/b GATE
RAS Row Address Strobe 222:: REFRESH _ --409.6---
DIN Data In A6th-, COUNTERCD)
DOUT Data Out :33] {NJ :1: 5
-15..i.3 Column Address Strobe Agom ROW 3E1”; MEMORY
TErh7 Read/Write Input Ath ll 33ng 10 )gg ;- ANIAX
Vcc Power (+5V) l _J I
it -- No.1 CLOCK ---
SS Ground ms o-- GENERATOR SUBSTRATE BIAS "'-07Ct:
N.C. No Connection GENERATOR ..°vss
TC51 41 othW--80
TC51 41 o0J)Z--1 o
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTE
Input Voltage VIN .-1n, 7 V 1
Output Voltage Vom: -1'1, 7 v 1
Power Supply Voltage vCC -1n.7 V 1
Operating Temperature TopR 04,70 °C 1
Storage Temperature TSTG -5rv150 " 1
Soldering Temperature. Time TSOLDER 260- 10 °C-sec 1
Power Dissipation PD 600 mH 1
Short Circuit Output Current 100T 50 mA 1
RECOMMENDED DC OPERATING CONDITIONS (Ta-tPohl'':)
SYMBOL PARAMETER MIN. TYP. L MAX. UNIT NOTE
Vcc Supply Voltage C5 5.0 5.5 V 2
VIH Input High Voltage 2.4 - 6.5 V 2
VIL Input Low Voltage -l.0 - 0.8 ll 2
DC ELECTRICAL CHARACTERISTICS (VCC=SV:102, Tai70''C)
SYMBOL PARAMETER MIN. MAX. UNITSNOTES
OPERATING CURRENT - -
ICCl Average Power Supply Operating Current Tcsl‘lOOI/z 80 109 mA 3,4,5
(RTs, "t-hW, Address Cycling: tRo-tRc MIN.) TMu1o0v2-lo - 85
STANDBY CURRENT
ICCZ P235: Supply Standby Current - 2 mA
(tThTr--0rG--vw)
fire ONLY REFRESH CURRENT TmmoJ/Zreo -
ICC3 Average Power Supply Current, Torg Only Node 100 mA 3,5
(RAS Cycling, tTA-g-vw.. tRc=tRC MIN. ) Tt3sutoo7p2-1o - 85
FAST PAGE MODE CURRENT -
Icca Average Power Supply Current, Fast Page Mode' 1651‘100I/2_8° 60 mA 3,4,5
(rt7f"ir-=irrr., tTM' , Address Cycling: tpc-cpc MIN.) Ttmu10ov2-10 - 50
STANDBY CURRENT
ICCS Power Supply Standby Current - 1 ttth
. (rtii"g---.lyivcc--0. 2V)
m BEFORE m REFRESH CURRENT TtmUM0J/W-tto - 100
Icce Average Power Supply Current, CA M Before . mA 3
RAS Mode ttts,, tar Cycling: tRc-tnc MIN. l.. 2tJtru1otWqb-1o - -85
INPUT LEAKAGE CURRENT
II(L) Input Leakage Current, any input (0V. VI“. 6. 5V, All Other -10 10 ph
Pins Not Under Test'OV)
~0UTPUT LEAKAGE CURRENT
Toto,) (BOUT is disabled, 0vtivours 5.5V) -10 10 Ph
OUTPUT LEVEL
Oil Output "H" Level Voltage (1tme-5mA) 2.4 ll
OUTPUT LEVEL
VOL Output "L" Level Voltage (IOUT=4.2mA) - 0.4 V
TC51 41 oNlz-80
TC5141oNlz-10
ELECTRICAL CHARACTERISTICS AND RECOMMENDED M OPERATING CONDITIONS
(1lcty--5vt10''2, Ta=0'u70''C) (Notes 6, 7, a)
TC514100J/D-80 TC514100J/Z-10
SYMBOL PARAMETER UNIT NOTES
MIN. MAX . MIN. MAX .
tRC Random Read or Write Cycle Time 150 - 180 - ns
tRMW Read-Hodify-Write Cycle Time 175 - 210 - ns
tPC Fast Page Mode Cycle Time 50 - 60 - ns
tPRMW :::§eP;§:eMOde Read-Modify-Write 75 - tio - ns
tRAC Access Time from "Eia" - 80 - 100 ns 9,14.15
tCAC Access Time from E55? - 20 - 25 ns 9,1h
tAA Access Time from Column Address - 40 - 50 ns 9,15
tCPA Access Time from -d7ig Precharge - 45 - 55 ns 9
CCLZ tA-s to Output in 1.ov-z - 0 - ns 9
tOFF Output Buffer Turn-off Delay 0 20 0 20 ns 10
tT Transition Time (Rise and Fall) 3 50 3 50 ns 8
tRP Tig Precharge Time 60 - 70 - ns
tRAS Rtts Pulse Width 80 10,000 100 10,000 ns
tRASP RVs Pulse Width (Fast Page Node) 80 200,000 100 200,000 us
tRSH Ftiriy Hold Time 20 - 25 - ns
ccsn EZE Hold Time 80 - 100 - ns
tRHCP ers Precharge to iirurHo1d Time 45 - 55 - ns
tCAS ESE Pulse Width 20 10,000 25 10,000 ns
tRCD rag to GEE Delay Time 20 60 25 75 ns 14
tRAD ii-AT; to Column Address Delay Time 15 40 20 50 ns 15
tCRP tTM to Ers Precharge Time 5 - 10 - ns
tcp . CZE Precharge Time 10 - 10 - ns
tASR Row Address Set-Up Time 0 - o - ns
tRAH Row Address Hold Time 10 - 15 - ns
tASC Column Address Set-Up Time 0 - O - ns
CCAH Column Address Hold Time 15 - 20 - ns
thut Eglg§§ Address Hold Time referenced 60 - 75 - ns
tRAL Column Address to iiEii Lead Time " - 50 - ns
CRCS Read Command Set-Up Time - o - ns
tRCH Read Command Hold Time - - ns 11
CRRH E:a%3%ommand Hold Time referenced 0 - 0 - ns 11
CHCH Write Command Hold Time 15 - 20 - ns
TC5141 oN/Z-tm
TC51410tu2-10
ELECTRICAL CHARACTERISTICS AND RECOMMENDED M OPERATING CONDITIONS
TC514100J/Z TC514100J/Z
SYMBOL PARAMETER -80 -10 UNITS NOTES
MIN. MAX. MIN. MAX.
EWCR Egite Command Hold Time referenced to 60 - 75 - ns
tgp Write Command Pulse Width 15 - 20 - ns
tRm. Write Command to tis Lead Time 20 - . 25 - ns
ttVI. Write Command to ITirg Lead Time 20 - 25 - ns
tDS tjaea Set-Up Time 0 - 0 - ns 12
tim Data Hold Time 15 - 20 - ns 12
tDHR Data Hold Time referenced to ETS- 60 - 75 - ns
tREF Refresh Period - 16 _.... 16 ms
twcs Write Command see-op Time 0 - 0 - ns 13
tCWD as to HR-ITE' Delay Time 20 - . 25 - ns 13
I tRWD Trt- to WIT-r: Delay Time 80 - 100 - ns 13
l tAUD Column Address to V?TTE Delay Time 40 - 50 - ns 13
I - MrtTfit" TI
tCPWD ??isirg:gzrgzd:; PRITE Delay me 45 - 55 - ns 13
tCSR CK? Set-Op Time (CTT before REE Cycle) 5 - 5 - ns
tCHR CiG Hold Time (CKg before EX? Cycle) 15 - 20 - ns
tRFC Ri; to CK§ Precharge Time 0 - 0 - ns
tCPT ctj-sPT2Q't-sJ-/tue, Test Cycle) 40 - 50 - ns
trrrs Write Command Set-Up Time(Test Mode In) 10 - 10 - ns
tpry Write Command Hold Time (Test Mode In) 10 - 10 - ns
tWRP 'ii-ii-sl-uh')),"-,-]-:,)',?,',; Time 10 - 10 - ns
t;mq FCr.t7 to R_A§_Ii_ca_ld Time 10 - 10 - ns
(CAS before RAS Cycle)
TC51410N/z--80
TC5141oN/z--1 0
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN THE TEST MODE
(VCC=5Vt10Z, Ta=0~70°C) (Notes 6, 7, 8)
TC5141003/Z TCSl4100J/Z
SYMBOL PARAMETER -30 -10 UNIT NOTES
MIN. MAX. MIN. MAX.
tRC Random Read or Write Cycle Time 155 - 185 - ns
tpc Fast Page Mode Cycle Time 55 - 65 - ns
(RAG Access Time from iuTg - 85 - 105 ns 9,14,15
tCAC Access Time from EK§ - 25 - 30 ns 9,14
tAA Access Time from Column Address - 45 '.. 55 n5 9,15
tCPA Access Time from tTii? Precharge - 50 - 60 ttS 9
CRAS 3% Pulse Width 85 10,000 105 10,000 ns
CRASP iuTif Pulse Width (Fast Page Node) 85 200,000 105 200,000 ns
titsit ITA''?? Hold Time 25 - 30 - ns
tcsu tTire Hold Time 85 - 105 - ns
tRHCP tyrs Precharge to Tig Bold Time 50 - 60 - ns
tCAS 53E Pulse Width 25 10,000 30 10,000 as
tRAI, Column Address to Ers Lead Time 45 - 55 - ns
CAPACITANCE (Vcc=5V:102, f=lMHz, Ta=0~70°C)
SYMBOL PARAMETER MIN . MAX . UNIT
C11 Input Capacitance (AO-AIO, DIN) - 5 p?
C12 Input Capacitance (EEE, Ers, i7Eirz) - 7 pF
C0 Output Capacitance (BOUT) - 7 PF
TC51 41 oN/z-tyo
TC51410tulZ--10
‘NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All voltages are referenced to Ilss.
3. 1cc1, Icc3, Icc4, Icce depend on cycle rate.
k. ICCls ICCA depend on output loading. Specified values ate obtained with the
output open.
5. Column address can be changed once or less while rTiiuvrr, and CK§=VIH.
6. An Initial pause of 200us ls required after power-up-followed by 8 m- only
refresh cycles before proper device‘operation is achieved. In case of using
internal refresh counter, a minimum of 8 TWg before Ftrs" refresh cycles instead
of 8 R-AS" only refresh cycles are required.
7. AC measurements assume tT=5ns.
8. VIH(min-) and VIL(max.) are reference levels for measuring timing of input
signals. Also, transition times are measured between VIH and VIL-
9. Measured with a load equivalent to 2 TTL loads and lOOpF.
10. topp(max.) defines the time at which the output achieves the open circuit Cott--
dition and is not referenced to output voltage levels.
11. Either tRCH or tRRH must be satisfied for a read cycle.
12. These parameters are referenced to t%T leading edge in early write cycles and
to WRITE leading edge in read-modify-write.cycles.
13. tHCS, tRRD, tCHD, tAWD and tCPWD are not restrictive operating parameters. They
are included in the data sheet at electrical characteristics only. If twcsitwcs
. (min.), the cycle ls an early write cycle and data out pin will remain open cir-
cuit (high impedance) through the entire cycle; If titimit CRUD (min.),
tam: tCWD(min.). tsum?, tARD (min.) and rt/ist,"' tchD (mim) (Fast Page Mode),
the cycle is a read-modify-Vrite cycle and t e data out will contain data read
from the selected cell: If neither of the above sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.
Ill, Operation within the tRCD(max.) limit insures that t c(max.) can be met,
tRCD(max.) is specified as a reference point only: fl tRCD is greater than the
specified tRCD(max.) limit, then access time Is controlled by tatc.
15. Operation within the tRAD(max.) limit Insures that tRAc(max.) can be met.
tRAD(max.) is specified as a reference point only: If t D is greater than the
specified tRAD(max.) limit, then access time is tii,,e1h'il1d by tAA.
TC51 41 Ood/z-Am
TC51 41 tXhllz--1 o
TIMING WAV EFORMS
READ CYCLE
V15 --""""'% I tmu;
m 'i? / C.,...
VII. -....
' tom» - tRC1) ‘RSH tear
v - t;
m m ll cw / j
VIL - .
cASH ‘mui ' use tcax M»
AtysA10 ROW _ comma //
Ittt, -- ,
tRCS tsuui
/ 1(flfl2
VIL - tom
tRag topp
Iras -
OPEN ----------rQY VALID DATA . .
t "ii" or "L"
TC51 41 oN/Z-tyo
TC51 41Gu/z--1 o
WRITE CYCLE (EARLY WRITE)
“RAB Z 'ic,
tttsit
. tear
Cs AS / /
t; tan.
“m tcm
AO-AIO o/fi)] ROW
tWP 'ffffffffllffi'ffWl%,
(lgfffff)i%fff7fjif%jg,
TC51 41 otulz-80
TC51410thW--10
READ-MOD IFY-WR ITE CYCL E
-...._ VIH
.-.....-- Ir H
CAS. I
A0~A10 COLUMN
DIN m VALID DATA
Dou'r v --.t.-..q--- VALID DATA
if/ff/ t "B" or "L"
T051 41 ON/Z-M
TC5141 0toz--1 o
FAST PAGE MODE READ CYCLE
_ VIH -
Vii, -
AO~A10
Wrtrr'E""
2T, ' IIHH or "L"
TC51410N/z-80
TC51410N/Z-1 o
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
vm -"-"""'""-"'er tmsr
ms 2 ,
tm . tnsx-z
Icap RCD on top top
P t(ms tom
---. VIE - _ -
CA J R /
Iru, - - -
1:” tASK: tASC
tasn tau! tASC tom tcan top
Vm - - -
AO-AIO ROW cor. 1 con 2 COL N
VIL - k-
twcs tmm twas ‘wcn
tms twcH
twp twp .
v ll - twp
m I 7j7%fjijif.7j)e, dh /h tf7ji%77i%)f,)
VIL - l "I
tbs rm; tDs tDE the tDH
VIH - 4 -1:
Day VALID DATA 1 VAIID DAIA2 VALID DATA 2fllllllNlllll
VII, - T
V051 -
Door OPEN
VOL --
': "H" or "L"
TC51 41 tXkllz-80
TC51410N/z--10
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
AO~A10
vm - tmsp /
VII, -
tcsu tPRMir t
tan? tHen Ttn' to? ESE
vm - \lss tCAS 'ss tCAs/ is' tcas //
vv, --.....2
[ “HAL
tate tm tASC Com tASC tCAH tASC tCAH
EY ROW [ily CouutN 1 (le C0LOMN 2 2% G0WMtltl [(EEEEEiE
RAD -EED ‘CWD tcw: tma,
tttct tamy-e tcew I
‘AWD tAWD tawn CRirt,
V - ctmr, -
Ill EtiEtiiiflifg; 'f-e / \ t f
twp ttgp twp
. trx/ tDH tDs tpH crm tDH
IH 7VALID VALID VALID
/) DATAl rum: 2 DAM N
ceLz tCLz tCLz
CCAC, tear tCAC
tux tAA Em
tRAc tCPA tCPA
OH VALID VALID VALID
DATAl DATA2 DATA N
Rm? ‘Rnw Rn?
t "H" or "L"
TC51 41 ON/Z-M
TC51 41 00J/Z-10
Ers" ONLY REFRESH CYCLE
VIE _".'.,".-.-'"-""-"''''; “RAB /
VII: -- N
VIE - .
TiM / \ /
tAS tam
VIE - - .
AO~A9 22i ROW 1llllllllllllillllll2lllllllGllllllllllllllllllllll.L
Von --
Dou'r OPEN
FT t "IP or "L"
NOTE: WRITE-"H" or "L", Alo-"H" or "L"
TC51 41 tXhyz--80
TC51 41 MJ/Z-l t)
C s BEFORE RAS REFRESH CYCLE
ITig (e, Ir--?"', x tite . i (u,
Tiii5 :3; -- CP l . tam gg2iggggggigggEi', y
mi: "f...)'), (fffy ' 'slllllMllillillillllilyllWflililiNh
NOTE: A0~A10="H" or "L" . 'I/A t "B" or "L"
TC51 41 otulz-80
TC5141tXhW-10
HIDDEN REFRESH CYCLE (READ
rar VIH ."..-.r'-'1 cm is hut;
m- '---''-'"'---r/ /
tear tRon 1511er
mg, V13 - tCHR 1r""T-""
1rII, - \
tRAD tRAL
tAsR tans tASC tCarr
A0sA10 :3: Row [(iii)t COL0MN (fffffffff _iii,i,i''''''''''z''i'z''''2
TRCS ‘ml s..,..)),,., tttm
vrt, - tcm
tmc . Torr
Dom- ---t-------_... . VALID DATA
t "ll" or "L"
Teil 41 oN/z-M
TC51410Nlz--10
HIDDEN REFRESH CYCLE (WRITE)
--.-""'-Nr
m \ " /
“CR? RB
--.-.. m - \
L - / .
tm HAL
tam tA AH
A0sA10 ?/', C.EI)i: mm me t20LUMtl 1fiiifiNllllil,
'lllfll0llllfffG0fffl,
VIH - W?
m Jfjffi
tns tbs
'1sllllllllllllllllllllllL
DIY Z: .r..-aaiiizizy IrALTD DATA 1llll0fff0ff0fflfllfflIfi0filfllr
’:llll
TC51 41 oN/Z-tyo
TC51410NM-10 .
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
m VIH -
Irst, -
Tig VIH -
VIL --
AO-AIO vm -
".. VIL -
READ CYCLE _ tRAI,
l nom- :2: I VALID DATA
Km VIL mr-..-
WRITE CYCLE
r Do Von -
WRITE :m C] twp
IL t1:8 tDH
DIN VIH - VALID DATA
l Irrt, -
REM-MODIFY-HMO: CYCLE tCAC to
Dou'r VOH - VALID DATA
VOL - ten
WRITE VIH -- tRcs
VIL - tm tm,
gm :1 - TMllllllfl0Wll%ll]WfllW0h mm sselGl]EUllll.1.
tns t1m
EEr. "H" or "L"
TC51 41 ooJ)z--80
TC51 41 ON/z-M O
WIT; E276 BEFORE m" REFRESH CYCLE
VIZ: - I
Irtir C"l"in'n0iii'i')
V31. - '
tRag /
tam REjiigi-iaa5gW0Ei;, ff
VOL ----a
"ll" or "L" IE: "B" or "L"
TC51410thhlz--80
TC5141 oN/Z-I o
READ CYCLE IN TIIE TEST MODE
-...-. VIH ---""-'"''""--T, tms .
ms l . \
VII. -
tear tnon tnsu . ttme
- VIH - tms -
w _yi' LLL11s....v..t1._,2
VII. - T
Hun tau.
tAStt tam tASC ‘CAH
A0--A10 Ee W (ii); cm
tRCS tam
riri"ii m VZ/Al/[W 1(fglit
vit, - ' tcate
tasc tOFF
RWT -----. OPEN -----------g VALID DATA F------
' V01. -
al' "H" or "L"
TC51 41 ON/Z-M
TC5141 ON/Z-I O
WRITE CYCLE (EARLY WRITE) IN THE TEST MODE
__ VIH -
V11. -
- VIH -
tAsc tcm
AO~A10 COLUMN
VIL --
twcs tma
Vm - twp
va, - l /1
tm ton
VIH -l, - .
DIN VALID DATA
DOUT H OPEN
VOL - .
'//f t "H" or "L"
TC51 41 ON/Z-Am
TC514100J/z--1o
FAST PAGE MODE READ CYCLE IN THE TEST MODE
AO~A1 0
vm ---"-""""9. tmsp
VII.”-
tttHCP
tCSH tPC
tttRP ‘ch tCAS tCP tcp
vm-- / is"), / V”! N, tCAS
vrr, - -
tAR , l, tau.
tASR tam IASC 195;! t sc tea Ix, tC
H ROW 2% COL 1 at cox. 2 ily CO.L N 1llllli.lj2llllllll.h
var, - B-------",
‘m tRCH ‘mm
t tacs tttCH tRCS tttal
RCS - I
vm -Uli'llljjlllfl]j] W/ /
VII, - tCAC tCAC ‘CAC
Bu ‘M Eu.
tam lcm tCPA
V - ' .
0H 1 VALID ) VALID VALID
v L l DATA 1 DATA2 mm N
tCI,g low tcm torg tcnz tOFF
-: "tt" " "L"
TC5141 othW--80
Tc51410tulz-1 o
FAST PAGE MODE WRITE CYCLE (EARLY WRITE) IN THE TEST MODE
AO-AIO
Tr""""-"''', ‘BASP
tPC tasu
tCRP lac!) tCAS tcp tcp
- l / \tm / N)) ms T-''-"-"""'-
AR 'ASC tASC
tASR ‘RAH' ‘ASC ‘CAH 'CAH . 1cm
((g)l ROW C)] COL 1 COL 2 COL N K
thS tWCH tWCS tttil
twcs twca
twp “WP
WW twp dh /h /
tDS tDH ins tDH tns tDH
j)%i7)7jTfj)i VALID DATA IWWMD m afavAuDrusxN)(ffff/ffff/fh/ff/(v/fff
-.: "B" or "L"
TC5141 otulz-80
TC51410tu2-10
TEST MODE
The TCSlthOJ/Z is the RAM organized 4,194,304 words by 1 bit, it is internally
organized 524,288 words by 8 bits. In "Test Node", data are written into 8 secotrs
in parallel and retrieved the same way. Aloe, A100 and AOC are not used. If, upon
reading, all bits are equal (all "1"s or "0"s), the data output pin Indicates a "i".
If any of the bits differed, the data output pin would indicate a "0". Fig. 1 show.,
the block diagram of TC514100J/Z. In "Test Mode", the 4M DRAM can be tested as if
it were a 512K DRAM. ..
'Trrrrg, -crs Before EKE Refresh Cycle" puts the device intd "Test Mode".
And "tTiFs Before Ers' Refresh Cycel" or "Eiil? Only Refresh Cycle" puts it back Into
"Normal Mode". In the Test Mode, "WiTTE, CK§ Before EhT; Refresh Cycle" performs
the refresh operation with the internal refresh address counter. The "Test Mode"
function reduces test times (1/8 in case of N test pattern)..
TC51 41 ON/z-tro
TC51 41 oN/Z-l o
BLOCK DIAGRAM IN THE TEST MODE
A1.08., AlocPe
Alon, 3100.500
A103, A10c, "RK-
7$1013., A10c , Aa:
ririi,Aloc,7ia"
A1011, Alec, Aty3
AmxlocEE
512K block
512K block
512K block
512K block
512K block
512K block
512K block
512K Block
Fig. 1
Alon. Aloe, *oc
Normal
Tee: f)
Nonnal I
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