TC514100ASJ-60 ,60 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by 1bit organization . Low Power
0 Fast access Lime and cycle time ..
TC514100ASJ-70 ,70 ns, 1-bit generation dynamic RAM4,194,304 WORD x l BIT DYNAMIC RAM
DESCRIPTION
PRELIMINARY
The TC514100AP/AJ/ASJ/AZ is the ..
TC514100AZ-70 ,70 ns, 1-bit generation dynamic RAMBLOCK DIAGRAM
WT!
,_____
UK: DATA m <0 the
w BUFFER
Nth2 CLOCK 2'yt.2l'-...l'-'"
GENERATOR
..
TC514100J-10 ,100 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by 1 bit organization . Low Power
. Fast access time and cycle time 5 ..
TC514101AZ-80 ,80 ns, 1-bit generation dynamic RAMfeatures include single power supply of 5V:e10% tolerance, direct
interfacing capability with high ..
TC514101Z-10 ,100 ns, 1-bit generation dynamic RAMELECTRICAL CHARACTERISTICS (VCC-svnoz, Ta=0N70°C)
tiiiLlEAiuiWaiiiFsC,
—-'-n
' '
PARAMETE ..
TC7W32FU ,DUAL 2-INPUT OR GATELOGIC DIAGRAM TRUTH TABLE PIN ASSIGNMENT (TOP VIEW)2B(6)L2y2YiEl-, FIE”GNDITI %2ACHARACTERISTIC SYM ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)TC7W34FU/FK(UNDER DEVELOPMENT)The TC7W34FU is high speed CMOS BUFFER fabricated TC7W34FUwith silico ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)FEATURES TC7W34FK. High Speed ----tpd--6ns(Typ0 at VCC=5V0 Low Power Dissipation ... ICC-- 1PA(Max. ..
TC7W34FU ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)LOGIC DIAGRAM PIN ASSIGNMENT (TOP VIEW)(1) (7)a-dc ba,2A(5)(6)O)(2)2Y"l-2lp l-n"GND|4|| Lim,RECOMME ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC514100ASJ-60
60 ns, 1-bit generation dynamic RAM
4,194,304 WORD M 1 BIT DYNAMIC RAM
This is advanced information and specifica-
tions are subject to change without notice.
p.ffi.C_R.LP..I.Lt2ftl
The TC514100AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1
bit. The ’I‘C514100AP/AJIASJ/AZ utilizes TOSHIBA's CMOS Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and to the system user.
Multiplexed address inputs permit the TC514t00AP/AJ/AN/AZ to be packaged in a standard 18 pin
plastic DIP, 26/20 pin plastic SOJ(300/350mil)and 20 pin plastic ZIP. The package size provides high
system bit densities and is compatible with widely available automated testing and insertion
equipment. System oriented features include single power supply of 5Vd:10% tolerance, direct
interfacing capability with high performance logic families such as Schottky TTL.
F_irAifi.Edi
0 4,194,304 word by lbit organization . Low Power
0 Fast access time and cycle time 660mW MAX. Operating
1C514100AP/AJIASJIAZ - 50 (T05 14100AP/AJ/ASJ/AZ - 60)
tttat: "ii/TS- Access T me 60m 5.5mW MAX. Standby
tan Column Address 0 Outputs unlatched at cycle end allows two-
Access Tnme 30ns dimensional chip selection
tcac TAT Access Time 20ns . 2rppte I/O Ieeility using"EARLY
. o era 1011
:2: Eczftleprgngemwe Hons . Lf/dyj'di'leyRl?i'le, m before RM refresh,
Cycle Time 45ns m-only refresh, Hidden refresh, Fast Page
0 Single power supply of 5Vi10% Mod'e and Test. Mode capability .
with a built-in Vim generator 0 All inputs and outputs 'l'TL compatible
O 1024 refresh cycles/16ms
0 Package T0514100AP : DIPlB-P-300E
8.lt.Lti../1l1tLEf. TC514100Ad .' SOJ26-P-350
AO-AIO Address Inputs WRITE Read/Write Input TC514100ASJ : SN26-P-300A
Tis' Row Address Strobe Vcc Power(+SV) T0514100AT ', ZIP20-P-400A
Dw Data ln vss Ground
Dom Data Out N C No Connection
(TAG Column Address Strobe
PIN CONNECTION (TOP VIEW) BLOCK DIAGRAM
Plank DIP Flame SOI mm: zlp OAtA D
_ IN IN
F-, aumn
A9_I_ d Cf TM NO.2 CLOCK
Ody! Dour J....' i" V GENERATOR - ( DATA OUT o Dow
, . tur."., 2” L', . aumn
d: cc, WW: L" COLUMN
:1 no o- ADDRESS 11> COLUMN
7 Al o» aurrsnsnn j "o DECOOER
- A2 o- REFRESH SENSE AMP.
A3 O. CONTROLLER - vo GATING
A4 CF- ---4096---
as o- couummm
x --r--
A7 o- [j, t tl ,' MEMORY
A8 cr- o "W ARRAY
A9 cr- now >0: 3 l
ADDRESS il o l
Alt) 0’ aumnsnu
I '-e, V
No.1 CLOCK CL.. suasrurz ems cc
KM o-- GENERATOR l asusuroa ro Vss
TC5141 OOAP/AJ IASJ IAZ-BO
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage " - l-r V 1
Output Voltage Voue - _ V 1
Power Supply Voltage Vcc - I--7 V I
Operating Temperature Tom 0~70 'C t
Storage Temperature Tsus - 55~150 'C l
Soldering Temperature . Time Tsoumt 260. IO 'C-sec 1
Power Dissipation Po 700 mW 1
Short Circuit Output Current louy 50 mA I
RECOMMENDED DC OPERATING CONDITIONS (Ta=0~70°C)
SYMBOL PARAMETER MIN. TYP. MAX. UNIT NOTES
Vcc Supply Voitage 4.5 5.0 5.5 V 2
l/s, Input High Voltage 2.4 - 6.5 V 2
Va Input Low Voltage - 1.0 - 0.8 V 2
TC51 41 OOAP/AJ IASJ /AZ-60
DC ELECTRICAL CHARACTERISTICS (Vcc = 5V 110%, Ta = 0--70oc)
SYMBOL PARAMETER MIN. MAX. UNITS NOTES
I TERA“? CURSRENTI o . c TC514100AP/AJ/ 120 3,4
CCI verage ower upp y perahng urrent - mA
(m, TAT, Address Cycling: tgc=tac MIN. ) ASJ/AZ-GO 5
STANDBY CURRENT
ICC? Power Supply Standby Current - 2 mA
(RT; = W = VIH)
m ONLY REFRESH CURRENT - TC514100AP/AJ/
ICC3 Average Power Supply Current, RAS Only Mode - 120 mA 3,5
- ASJ/AZ-GO
(RAS- Cycling, CAS=V1HI tRC=tRC MIN. )
I If, PAC: M025 CTR? T F P M d TC514100AP/AJ/ 60 A 3, 4
4 vera e ower uppy urrent, est a e o e - m
CC g g ASJ/AZ-6O 5
(man. iCNi, Address Cycling: tpc=tpc MIN. ,
STANDBY CURRENT
Iccs Power Supply Standby Current - 1 mA
(FAT: CAS = Vcc - 0.2V)
CAS BEFORE RAS REFRESH CURRFlT _ TC5t4100AP/A)/
lcca Average Power Supply Current, CAS Before R7373r AS /A2 60 - 120 mA 3, 5
Modelm, CK; Cycling: tRC=titc MIN, l J -
INPUT LEAKAGE CURRENT(any input except TF)
hm Input Leakage Current, any input ~10 10 pA
(OVSVWS 6.5V, All Other Pins Not Under Test: 0V)
l OUTPUT LEAKAGE CURRENT It) 10 A
ooo (ow is disabled, ovsvoms 5.5V) V
OUTPUT LEVEL
VOH 2.4 - V
Output "H" Level Voltage (lour= -5mAl
OUTPUT LEVEL
VOL " " - 0.4 v
Output L Level Voltage(IoUT=4.2mA)
TC51 41 OOAP/AJ IASJ/AZ-60
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc = 5V l 10%, Ta = 0~70°c)(Notes 6, 7, 8)
TC514100AP/AJIASJIAZ‘60
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
IRC Random Read or Write Cycle Time HO - ns
tsow Read-Modify-Write Cycle Time 135 - ns
tpc Fast Page Mode Cycle Time as - ns
tpRMw Fast Page Mode Read-Modify-Write Cycle Time 70 - ns
tug Access Time from Tis" - 60 ns 'li,"
ICAC Access Time from TAT - 20 ns 9,14
taa Access Time from Column Address - 30 ns 9,15
tora Access Time from EA? Precharge - 40 ns 9
[cu th9 to Output in Low-Z 0 - , ns 9
to” Output Buffer Tum-off Delay 0 20 ns 10
M Transition Time(Rise and Fall) 3 50 ns 8
tap ’R'Ai Precharge Time 40 - ns
teas R775 Pulse Width 60 10,000 ns
tnAsp COTS Pulse Width(Fast Page Mode) 60 200,000 ns
ter, RAS Hold Time 20 - ns
1mm, RAE Hold Time From CAS" Precharge (Fast Page-Mode) 40 - ns
ICSH ENS Hold Time 60 - ns
tras CM Pulse Width 20 10,000 ns
lam RAS to CAS" Delay Time 20 40 ns 14
1mm RAS to Column Address Delay Time 15 30 ns 15
law thy to iii9 Precharge Time 5 - ns
" u ths Precharge Time 10 - ns
v Case Row Address Set-up Time 0 - ns
(Rm. Row Address Hold Time 10 - ns
tasc Column Address Set-Up Time 0 - ns
tum Column Address Hold Time 15 - ns
tun: Column Address to RAS Lead Time 30 - ns
. tart; Read Command Set-Up Time 0 - ns
_th,. Read Command Hold Time 0 - ns 11
1mm Read Command Hold Time referenced to RAS o - ns 11
me Wme Command Hold Time 10 - ns
TC5141 OOAP/AJ IASJ IAZ-60
ELECTRICAL CHARACTGERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Continued)
TCS 1 4 l 00APtAjtASl/A2-60
SYMBOL PARAMETER UNITS NOTES
MIN. MAX.
twp Write Command pulse Width 10 - n5
terw Write Command to m Lead Time 20 - ns
tom Write Command to m Lead Time 20 - ns
tos Data Set-Up Time 0 - ns 12
to” Data Hold Time IS - ns 12
1m Refresh Period - 16 ms
twcs Write Command Set-UP Time 0 - ns 13
ttwo m to W‘RTTE Delay Time 20 - ns 13
two A7G to WRITE Delay Time 60 - ns 13
two. Column Address to WRIT? Delay Time 30 - ns 13
tcpon m Precharge to WRTT'E' Delay Time 40 - m 13
m Set-Up Time
tcsn (m before m Cycle) 5 - ns
too CAT Hold Time 15 - m
(:33 before m Cycle)
lnpt m to CAT Precharge Time 0 - ns
tCPT tie'',""'""" Time ' before m Counter Test 30 - ns
Write Command Set-Up Time
(Test Mode In)
Write Command Hold Time
twrr, 10 -
(Test Mode In)
t WHITE to m Precharge Time 10
w" (EH before R713 Cycle)
t WRIiE to "rt7T Hold Time
. WRH (CK; before WG Cycle)
TC5141 OOAP/AJ IASJ IAZ-60
ELECTRICAL CHARACTGERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN
lee TEST MODE
(Vcc = 5V i 10%, Ta = o~70°C) (Notes 6, 7, 8)
TC514IOOAPIAJ/ASJ/AZ-60
SYMBOL PARAMETER UNIT NOTES
MIN. MAX.
[m Random Read or Write Cycle Time 115 - _ ns
1pc Fast Page Mode Cycle Time 50 - ns
w“ Access Time from m - 65 ns :14
ICAE Access Time from US - 25 ns 9,14
tna Access Time from Column Address - 35 ns 9,15
ttpa Access Time from chS Precharge - 45 ns 9
tans R73 Pulse Width 65 10,000 ns
twaw RE Pulse Width (Fast Page Mode) 65 200,000 ns
trise RR Hold Time 25 - n5
WC? EAT Hold Time From WG Precharge (Fast Page Mode) 45 - ns
ttsn C75 Hold Time 65 - ns
ttns firs Pulse Width 25 10,000 as
um Column Address to Ith-s Lead Time 35 - ns
CAPACITANCE (l/cc = 5V :.t:10%,f=1MHz,Ta = o~70°C)
SYMBOL PARAMETER MIN. MAX. UNIT
Cu Input Capacitance(A0-At0, Dm) - 5
C.) Input Capacitance (m, t?AT, WRITE) - 7 pF
Co Output Capacitance(Dour) - 7
TC514100AP/AJ/ASJ/AZ-60
NOTES:
I. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
All voltages are referenced to Vss.
I001. 1003. ICCA. lay, depend on cycle rate.
1001. 1004 depend on output loading. Specified values are obtained with the output open.
Column address can be changed once or less While I7S--rvtt, and CM.-cchrm,
@9199.”
An initial pause of 200ps is required after power-up followed by 8 RAS only refresh cycles before
proper device operation is achieved. In case of using internal refresh counter, a minimum of 8
CKS before WG refresh cycles instead of 8 ms only refresh cycles are required,
7. AC measurements assume tT=6ns.
8. VIH (min.) and V11,(max.) are reference levels for measuring timing of input signals. Also,
transition times are measured between V1” and Vic,
9. Measured with a load equivalent to 2 'ITL loads and lOOpF.
10. tolrrr(max.)defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
11. Either tRCll or tmm must be st1tisfied for a read cycle.
12. These parameters are referenced to m leading edge in early write cycles and to WRITE leading
edge in Read-Modify-Write cycles.
13. twcs, tnwp. tcwn, tAWD and tcpwo are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If twcsiit twcs(min.). the cycle is an early
write cycle and data out pin will remain open circuit(high impedance)throughout the entire cycle;
If mvnr72titwotmin.), tcwoiittcwD(min.), tAwoiittAwD(min.) and tcpwpgtcpwp (min.)(Fast Page
Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the
selected cell: If neither of the above sets of conditions is satisfied, the condition of the data outfat
access time) is indeterminate.
14. Operation within the tRCD(max.)limit insures that time (max.) can be met.
titCD(max0 is specified as a reference point only: If LRCI) is greater than the speciried tncnmmx.)
.limit, then access time is controlled by tCAC.
15. Operation within the tRAD(max.) limit insures that UtAC(rttax0can be met.
tuAD(max.)is specified as a reference point only: If tum) is greater than the specified htAD(max.)
limit, then access time is controlled by tAA.
TC51 41 OOAP/AJ /ASJ/AZ-60
TIMING WAVEFORMS
READ CYCLE
AO-AIO COLUMN
. .__W Vm
Dom .--._-_ DATA - OUT
Eg.. "H'' or "L"
TC51 41 OOAP/AJ/ASJ IAZ-BO
WRITE CYCLE LEARLY WRITE)
AO-AIO COLUMN
Dm DATA - IN
DOUT _ OPEN
vos----
.2 "H" or "L''
TC5141 OOAP/AJ IASJ IAZ-60
READ-MODIFY-WRITE CYCLE
AO-AN COLUMN
Dm DATA - IN
VoH---
Dour DATA " OUT
.: "H'' or "L''
TC51 41 OOAP/AJ IASJ /AZ-60
FAST PAGE MODE READ CYCLE
VIL ---
AO-AIO
V01. -
Ea.. "H" or "L"
TC51 41 OOAP/AJ IASJ IAZ-60
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
toxse _ ----
- VIH - a V
" - 'k T
1pc tRSH
t RP tam ,..tse. , E15}? I _
‘ " tcas tcas teas
“H Vm - -d _
CAS / tl
VIL -.- §__7' -
‘ASRV, -_ huh tas _ ‘CAH tatc -M- ICAH % 15AM r
AO-AIO Virs '1ff RD a "
V W COL.1 COL.2 COLN
I ' ' twcs twcu twcs twcu
twcs twc t t 7 t t
Vm IH p),?,,'-' WP V wpr
(L 1 k
toi 10H ttrs - ton ttys ton
vo, - I
DIN Dm 1 J DIN 2 DIN N
l/are--
Dom OPEN
Eil: "H" or "L''
TC51 41 OOAP/AJ IASJ /AZ-60
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
{RASP ------
V -.. ’1 "*
"it7G m N [L 'N...
tou, _ taco
" -.. A
:73 L/
ttMitt tmu,
- --t-s"-F--
v _..4
IH Xii)h(.
‘ tou,
ttttsr,""
W%TE- 1C-.iij''i'itiEr''' ti,,,
" "t -rf.fi/l/iffJff)jft/fffif/
’_:__;_//‘
AO-AIO
Vor. -
T051 41 OOAP/AJ IASJ IAZ-GO
RKS ONLY REFRESH CYCLE
_icvsse,
u5z''gii, '. "H'' or "L"
TC51 41 OOAP/AJ /ASJ IAZ-BO
m BEFORE m REFRESH CYCLE
tras":.].".--'",.' x J} ’\_
-c"l-'i'r.: -trci-ru CHR
55 II? I - s))',iijCiiii,''r,j;; i"j,iii,i',ii'i'i',i,
‘twapr ‘tWRHr
WW VIC C5fgiiffiiif' , 'iijifji'i'i's'ii,
D vote----' , OPEN
OUT vo--.-.-.-.)
Note: AO-AIO.-.. "H'' or "L"
.: "H" or "L"
TC514100AP/AJ/ASJ/AZ-60
HIDDEN REFRESH CYCLE(READ)
COLUMN
DATA .. OUT
ET. "H" or "L''
TC51 41 OOAP/AJ IASJ /AZ-60
HIDDEN REFRESH CYCLE (WRITE)
A0~A10 COLUMN
Dm DATA . IN
Dour O P E N
.: "H" or "L"
TC51 41 OOAP/AJ IASJ /AZ-60
UAS BEFORE rt7ig REFRESH COUNTER TEST CYCLE
AO-AIO COLUMN
READ CYCLE
f VOH ..--..
Dour DATA . OUT
Ot. ---.
g WRIT":
1 VII.
WRITE CYCLE
( VOH -
Dour VOL -
READ-MODIFY-WRITE CYCLE
f VOH -.--
BOUT DATA - our
VOL ---.'
Eil: "H" or "L''
TC514100AP/AJ/ASJ/AZ-60
WRITE. CKS BEFORE m REFRESH CYCLE
m C1rr.r, W \ i) L
m :,:r.r.r,.r...v-i'"-"iC"'' tcmt w,//'" // siii'
177mTt :1: -= -= /////////////////////////////
Dour l
Note: Dm, A0--A10= "H" or "L"
','i'"tf5; : "H" or "L"
TC51 41 tX9AP/Ad/ASJ/AZ-60
TEST MODE
The TC514100AP/AJ/ASJ/AT is the RAM organized 4,194,304 words by 1 bits, it is internally
organized 524,288 words by 8 bits. In "Test Mode", data are written into 8 sectors in parallel and
retrieved the same way. Altm, A100 and A00 are not used. If, upon reading, all bits equal(all"I"s or
"O"s), the data output pin indicates a"1". If any of the bits differed, the data output pin would indicate
a"0". Fig.1 shows the block diagram of TC514100AP/AJ/ASJ/AZ. In "Test Mode", the 4M DRAM can be
tested as if it were a512K DRAM.
“WW, tWI Before m Refresh Cycle"puts the device into "Test Mode", And 'CAS Before m
Refresh cyele''or"RES Only Refresh Cycle"puts it back into“Normal Mode". In the Test Mode,
“WW, CKS Before TtTG Refresh Cycle"performs the refresh operation with the internal refresh
address counter. The"Test Mode"function reduces test times(1l8 in case of N test pattern).
T051 41 OOAP/AJ IASJ/AZ-BO
BLOCK DIAGRAM IN THE TEST MODE
Aum AIOC1A0C
Normal
Anon- Aux:
512K block
No, Anx. “ac Test
512K block
Alan. Aux. “ac
512K block
Aum.Amo A94:
512K block
(.. Dom
Normal Amp A mo N:
512K block
Alum Amo Aoc
512K block
Amm A mo Aoc
512K block
Normal
Anew Amer A0:
512K block Axon. A100 Aoc
Fig. 1
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