TC514100AZ-70 ,70 ns, 1-bit generation dynamic RAMBLOCK DIAGRAM
WT!
,_____
UK: DATA m <0 the
w BUFFER
Nth2 CLOCK 2'yt.2l'-...l'-'"
GENERATOR
..
TC514100J-10 ,100 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by 1 bit organization . Low Power
. Fast access time and cycle time 5 ..
TC514101AZ-80 ,80 ns, 1-bit generation dynamic RAMfeatures include single power supply of 5V:e10% tolerance, direct
interfacing capability with high ..
TC514101Z-10 ,100 ns, 1-bit generation dynamic RAMELECTRICAL CHARACTERISTICS (VCC-svnoz, Ta=0N70°C)
tiiiLlEAiuiWaiiiFsC,
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PARAMETE ..
TC514101Z-10 ,100 ns, 1-bit generation dynamic RAMFEATURES
. 4,194,304 word by 1 bit organization a Low power
. Fast access time and cycle time 57s ..
TC514260BFT-70 ,70ns; V(in/out): -1 to +7V; 700mW; 50mA; 262,144 word x 16 bit dynamic RAMTOSHIBA
TC5 14260BJ /BFT-70/ 80
262,144 WORD X 16 BIT DYNAMIC RAM
DESCRIPTION
The TC514 ..
TC7W32FU ,DUAL 2-INPUT OR GATELOGIC DIAGRAM TRUTH TABLE PIN ASSIGNMENT (TOP VIEW)2B(6)L2y2YiEl-, FIE”GNDITI %2ACHARACTERISTIC SYM ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)TC7W34FU/FK(UNDER DEVELOPMENT)The TC7W34FU is high speed CMOS BUFFER fabricated TC7W34FUwith silico ..
TC7W34FK ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)FEATURES TC7W34FK. High Speed ----tpd--6ns(Typ0 at VCC=5V0 Low Power Dissipation ... ICC-- 1PA(Max. ..
TC7W34FU ,TRIPLE NON-INVERT BUFFER (UNDER DEVELOPMENT)LOGIC DIAGRAM PIN ASSIGNMENT (TOP VIEW)(1) (7)a-dc ba,2A(5)(6)O)(2)2Y"l-2lp l-n"GND|4|| Lim,RECOMME ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC7W53F ,2-CHANNEL MULTIPLEXER/DEMULTIPLEXERTC7W53F/FU/FKv,logical amplitude/I/cc-GN?) control signal. TC7W53FUJVI u-I -t.E.rFor example, in th ..
TC514100AP-80-TC514100ASJ-70-TC514100AZ-70
100 ns, 1-bit generation dynamic RAM
4,194,304 WORD x
DESCRIPTION
1 BIT DY
NAMIC RAM
PRELIMINARY
The TC514100AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1
bit. The Tc514100AP/AJ/ASJ/A2 utilizes TOSHIBA'S CMOS Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and to the system user.
Multiplexed address inputs permit the TC514100AP/AJ/ASJ/AZ to be packaged in a standard 18 pin
plastic DIP, 26/20 pin plastic SOJ (300/350mil) and 20 pin plastic MP. The package size provides high
system bit densities and is compatible with widely available automated testing and insertion
equipment. System oriented features include single power supply of 5Vi10% tolerance, direct
interfacing capability with high performance logic families such as Schottky 'ITL.
FEATURES
0 4,194,304 word by lbit organization .
. Fast access time and cycle time
TC5l4100AP/Aj/ASj/A2 - 70/80/10
{MC COST Access Time 70ns 80ns lOOns
taa fee,',"",,"),',? ress 35ns 40m 50ns
ICAC m Access Time 20ns 20ns 25ns
tRC Cycle Time 130ns 150ns 180ns
1pc Fast Page Mode .
Cycle Time 45ns Sons 60ns
. Single power supply of 5V:t10% .
with a built-in V1313 generator .
?1tLtukly1U
AO-AIO Address Inputs WW Read/Write Input I
W Row Address Strobe Vcc Power ( + SV) .
Dw Data In vss Ground .
Dow Data Out NC No Connection
CAT Column Address Strobe
PIN CONNECTION (TOP VIEW)
Plastic DIP
Plastic SOJ Plastic tit' W
" T", rf" US In o-
D T F 'tcc No.2 CLOCK
'r'tt Dom?”
, D T', 'fs; vs: GENERATOR
F _ IN .4 "
9 m..._ E6” WET!
”Ly. ?:AIO (OLUMN
TCr, " N.C. A0 cy- Aoonzss
M-l-ll. rsrat A10» aunnsm) -l
A21 I t.S:
LA.:' At A3 A2 o- nmrsn
Vcc??.'.. 'rsu, A3 o- CONTROLLER -
2:3: " A6 M o- mass”
- J - AS tr-
Ao., A8 A6 0. coumsn (IO)
M o- i
A9 0- ROW
ADDRESS
AN CF- BUFFERSUI)
NCht CLOCK
m o ' _ GENERATOR
Low Power
550mW MAX. Operating
(TC514100AP/AJ/ASJ/AZ-70)
468mW MAX. Operating
(TC514100AP/AJ/ASJ/AZ-80)
413mW MAX. Operating
(TC514100AP/AJ/ASJ/AZ - 10)
5.5mW MAX. Standby
Outputs unlatched at cycle end allows two-
dimensional chip selection
Common I/O capability using"EARLY
WRITE" operation
Read-Modify-Write, Chg before m refresh,
EES-only refresh, Hidden refresh, Fast Page
Mode and Test Mode capability
All inputs and outputs TTI, compatible
1024 refresh cycles/16ms
Package
TC514100AP
TC514100AJ
TC514100ASJ
TC514100AZ
BLOCK DIAGRAM
.' DiP18-P-300E
: SOJZS-P-350
: SOJ26-P-300A
: T1P20-P-400A
DATA IN <0 Dw
BUFFER
DATA our o Door
BUFFER
COLUMN
DECODER
SENSE AMP.
" ammo
DECOOER
' MEMORY
10,14 ARRAY
suasnw: ems *0 Vcc
GENERATOR 3-0 Vts
TC5141 ooAP/AJ/ASJ/AZ-70, TC51 41 o0AP/AJ/ASJ/AZ-80
TC51 41 MAP/Au/AN/AZ-I o
ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNITS NOTES
Input Voltage Ve; -1-7 V 1
Output Voltage Vow -1~7 V 1
Power Supply Voltage Vcc - _ V 1
Operating Temperature Tom 0~70 'C 1
Storage Temperature Tsro - 55-150 'C 1
Soldering Temperature . Time TSOLDER 260 . 10 'C ' sec l
Power Dissipation Po 700 mW 1
Short Circuit Output Current lour 50 mA 1
RECOMMENDED DC OPERATING CONDITIONS (Ta=0--7ty'C)
SYMBOL PARAMETER MIN. TYP.
Vcc Supply Voltage 4.5 5.0
" Input High Voltage 2.4 -
" Input Low Voltage -
TC51 41 ooAP/AJ/ASJ/Az--7o, TC51 41 ooAP/AJ/ASJ/AZ--80
TC51 41 ooAP/AJ/ASJ/AZ--1 o
DC ELECTRICAL CHARACTERISTICS (VCC = 5V f.. 10%, Ta = 0~70°C)
SYMBOL PARAMETER 1-'MIN. MAX. UNITS NOTES
OPERATING CURRENT TC5M100APuufASlfAZ.70 - 100 3 4
Ict, Average Power Supply Operating Current TCSHIOOAPIAJIASJIAZ-BO - 85 mA
(m, (TS. Address Cycling: tuna: MIN. ) TtCSto00AptAJ/AwAbit) - 75 5
STANDBY CURRENT
'ccz Power Supply Standby Current .- 2 mA
(m=m=le)
tTAS ONLY REFRESH CURRENT TC$ta100ANAJ/ASUAb7t) - 100
lcca Average Power Supply Current, "i7T Only Mode T0Mt00AtNtutA$ltAb8t) - 85 mA 3.5
(R73 Cycling, m=Vmi tac=tac MIN. ) TCS16t00APnulASl/tu.t0 - 75
FAST PAGE MODE CURRENT TCS1o00AtVAJtASJ/Ab7t) - 60 3 4
'cca Average Power Supply Current, Fast Page Mode TC8tql00M'fAJtAWAb8t) - 50 mA
(m=VIL. m. Address Cycling: tpc=trrc MIN. ) TCs14100APtAJfA$J/Ab10 - 45 s
STANDBY CURRENT
lccs Power Supply Standby Current - 1 mA
(m =i7T= Vcc - 0.2V)
TAT BEFORE :03 REFRESH CURRENT TCS1M00tuVtkttASJtAbt0 - 100
Iccs Average Power Supply Current, a: Before RAT TCSlMOOAPIAJ/ASJIALBO - 85 mA 3,5
Mode0iM, CET Cycling: trrc=tstc MIN. , Ttm4t00tUVAJfASJfA2.t0 - 75
INPUT LEAKAGE CURRENT
lucy Input Leakage Current, any input -10 10 PA
(OVSVINS 6.5V, All Other Pins Not Under Test=0v)
I OUTPUT LEAKAGE CURRENT 10 IO PA
Ott) (Dow is disabled, 0VSVours5.5V)
OUTPUT LEVEL
Von " . 2.4 - v
Output H Level Voltage(loura -5mA)
OUTPUT LEVEL
VOL " . - 0.4 V
Output L Level Voltage0our=4.2mA)
TC51 41 o0AP/AJ/ASJ/AZ--70, "rC514100AP/AJ/ASJ/Az-80
TC51 41 ooAP/AJ/ASJ/AZ-1 o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vcc = 5V i 10%, Ta = 0~70°c)(Notes 6, 7, 8)
TC514100AP/ TCSIMOOAPI l' TCSIMOOAP/
SYMBOL PARAMETER AJIASJ/AZJO AJIASJIAZ-BO AJ/ASJIAZ-10 UNIT NOTES
MIN. MAX. MIN. MAX, MIN. MAX.
Inc Random Read or Write Cycle Time 130 - 150 - 180 - ns
‘me Read-Modify-Write Cycle Time 155 - 175 - 210 - ns
lpc Fast Page Mode Cycle Time " - SO - 60 - ns
Ipmw 'cj1,''p,,','eMode Read-Modify-Write 70 - 75 - 90 - ns
inc Access Time from m - 70 - 80 - 100 ns 9'15”
tou: Access Time from (K? - 20 - 20 - 25 ns 9, 14
tan Access Time from Column Address - 35 - 40 - 50 ns 9, 15
[CPA Access Time from m Precharge - 40 - 45 - 55 ns 9
[cu m to Output in Low-Z 0 - O - O - n: 9
to“ 0011301 Buffer Tum-off Delay 0 20 0 20 0 20 ns 10
tt Transition Time(Rise and Fall) 3 50 3 50 3 50 ns 8
tap m Precharge Time 50 - 60 - 70 - ns
teat m Pulse Width 70 10,000 80 10,000 100 10,000 m
tttasp k7T Pulse Width(Fast Page Model 70 200,000 80 200,000 100 200,000 ns
tag” m Hold Time 20 - 20 - 25 - ns
tchP 'rf/til/l',':',,,')"'"' ES Precharge 40 - " - ss - ns
tcsn m Hold Time 70 - 80 .. 100 - ns
toss C75 Pulse Width 20 10,000 20 10,000 25 10.000 ns
1.ch m to m Delay Time 20 so 20 60 25 " ns "
tam m to Column Address Delay Time 15 " IS 40 20 50 ns 15
tou, m to m Precharge Time 5 - S - 10 - ns
tos TAT Precharge Time 10 - 10 - 10 - ns
tate Row Address Set-Up Time 0 - 0 - 0 - ns
[RAH Row Address Hold Time 10 - IO - 15 - ns
tasc Column Address Set-Up Time 0 - 0 - 0 - ns
tow Column Address Hold Time 15 - 15 - 20 - ns
titat Column Address to R755 Lead Time 35 - 40 - 50 - ns
tncs Read Command Set-Up Time 0 - 0 - 0 - ns
‘ncu Read Command Hold Time 0 - 0 - 0 - ns 11
1mm 'eii1sco"'""""d Hold Time referenced 0 - O - 0 - ns ll
twcu Write Command Hold Time IS - 15 - 20 - ns
TC51 41 o0AP/AJ/ASJ/Az--70, TC5141 o0AP/AJ/ASJ/AZ-8o
TC51 41 ooAP/AJ/ASJ/AZ--1 o
ELECTRICAL CHARACTGERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Continued)
TC514100AP/ TC514100AP/ I' TC514100API
SYMBOL PARAMETER AJ/ASJ/AZ-70 AJIASJ/AZ-8O AJIASJIAZ-IO UNITS NOTES
MIN. MAX. MIN. MAX. MIN. MAX.
twp Write Command Pulse Width 1S - 15 - 20 - ns
tRwL Write Command to m Lead Time 20 - 20 - 25 - ns
1ch Write Command to ES Lead Time 20 - 20 - 25 - ns
ttrs Data Set-Up Time 0 - O - 0 - ns 12
tttrt Data Hold Time 15 - 15 - 20 - ns 12
tRES Refresh Period - 16 - 16 - 16 ms
twcs Write Command Sel-UP Time 0 - t) - 0 - ns 13
tcwo EX; to TNRI-TE Delay Time 20 - 20 - . 25 - ns 13
two m to WRTTE Delay Time 70 - 80 - 100 - ns 13
tam, Column Address to W'RTTE Delay Time 35 - 40 - 50 - ns 13
tcpwo G's Precharge to W! Delay Time 40 - 45 - " - n, 13
tcstt US Set-Up Time 5 - 5 - 5 - ns
(CK before W Cycle)
tom 0:: Hold Time 15 - IS - 20 - m
(03 before m Cycle)
trot m to m Precharge Time 0 - 0 - O - ns
tcpm m Precharge Time 40 - 40 - 50 - ns
(OT: before us Counter Test Cycle)
twrs Write Command Set-Up Time 10 - 10 - 10 - ns
(Test Mode In)
twm Write Command Hold Time 10. - IO - 10 - ns
(Test Mode In)
twro WW? to m Precharge Time 10 - 10 - 10 - M
(m before RAT Cycle)
twm WWITT to W Hold Time 10 - IO - 10 - ns
(CE before m Cycle)
TC51 41 o0AP/AJ/AS0/Az--70, TC51 41 ooAP/AJ/ASJ/Az--80
TC51 41 MAP/AJ/AN/AZ-I o
ELECTRICAL CHARACTGERISTICS AND RECOMMENDED AC OPERATING CONDITIONS IN
THE TEST MODE (Vcc = 5V i 10%, Ta = 0--70''C) (Notes 6, 7, 8)
TC514100AP/ TC514100AP/ _ TC514100AP/
SYMBOL PARAMETER AJ/ASJ/AZ-70 AJ/ASJ/AZ-80 Aj/ASI/At-lo UNIT NOTES
MIN. MAX, MIN. MAX. MIN. MAX.
tttc Random Read Write Cycle Time 135 - 155 - 185 - ns
tassw Read-Modify-Write Cycle Time 160 - 180 - 215 -
tpc Fast Page Mode Cycle Time 50 - SS - 65 - ns
tpruvw Fast ly" Mode Read-Modify-write 75 _ 80 - 95 - ns 13
Cycle Time
Inc Access Time from m - 75 - 85 - 105 ns '',1s''
tom Access Time from t73 - 25 - 25 - 30 m 9, 14
tun Access Time from Column Address - 40 - 45 - 55 ns 9, 15
ICPA Access Time from TA-T Precharge - 45 - 50 - 60 ns 9
WA; m Pulse Width 75 10,000 85 10,000 105 10,000 ns
‘RASF "k7i5 Pulse Width (Fast Page Mode) 75 200,000 85 200,000 105 200,000 ns
tttsri m Hold Time 25 - 25 - 30 .. ns
icsu 3? Hold Time 75 - 85 - 105 - M
13.40 553 Prechrge to ITM Hold Time 45 - 50 - 60 - ns
tcas CAT Pulse Width 25 10,000 " 10,000 30 10,000 ns
IRAL Column Address to m Lead Time 40 - 45 - 55 - ns
ttwo EB to W! Delay Time " - 25 - 30 - ns 13
IRWD ATG to BhTh Delay Time " - 85 - 105 - ns 13
IAWD Column Address to iWiT2 Delay Time 40 - 45 - 55 - ns 13
tcpwo m Precharge to WFTTE Delay Time 45 - SO - 60 - ns 13
CAPACITANCE (vcc = 5V t 10%, f = 1MHz, Ta = 0~70°C)
SYMBOL PARAMETER MIN. MAX. UNIT
C” Input CapatitancelA0-A10, DIN) - S
(.2 Input Capacitance0iM, c_AS, WRITE) - 7 pF
Co Output Capatitante(Dour) - 7
TC5141 o0AP/Ad/ASJ/Az--70, TC51 41 00AP/AJ/ASJ/AZ-80
TC51 41 o0AP/AJ/ASu/AZ-1 o
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device.
All voltages are referenced to vss.
ICCI. Icca, ICOS, ICC6 depend on cycle rate.
Icc1, ICC4 depend on output loading. Specified values are obtained with the output open.
Column address can be changed once or less While Ma”, and CKS=VHL
mcnp-mgo
An initial pause of 200ps is required after power-up followed by 8 tITG only refresh cycles before
proper device operation is achieved, In case of using internal refresh counter, a minimum of 8
Wig before RAS refresh cycles instead of 8 PIS only refresh cycles are required.
7. AC measurements assume br=5ns.
8. VI” (min.) and Vit, (max.) are reference levels for measuring timing of input signals. Also,
transition times are measured between Vm and Vu,,
9. Measured with a load equivalent to 2 TIT loads and lOOpF.
10. tom: (max0defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
11. Either tncu or tmm must be satisfied for a read cycle.
12. These parameters are referenced to TM leading edge in early write cycles and to WRITE leading
edge in Read-Modify-Write cycles.
13. twcs, tRWD, tCWD, tAWD and tcpwp are not restrictive operating parameters. They are included
in the data sheet as electrical characteristics only. If twcsg twcs(min.), the cycle is an early
write cycle and data out pin will remain open circuit (high impedance) throughout the entire cycle;
If tawo2-t tRWDKmin.), tcvmittcwn(min0, tAwD2ttAwn(min.) and tcPwro2ttcPwD(min.) (Fast Page
Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data read from the
selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out(at
access time) is indeterminate.
14. Operation within the tncp(max.) limit insures that tRAC (max.) can be met.
tRcu(max.)is specified as a reference point only: If tncp is greater than the specified tttCD (max.)
limit, then access time is controlled by tCAC.
15. Operation within the tRAD(max.) limit insures that tmc(max.) can be met.
tnm)(max.)is speciried as a reference point only: If tRAD is greater than the specirsed tRAD(max.)
limit, then access time is controlled by tAA.
TC51 41 ooAP/AJ/ASJ/Az--70, TC51 41 MAP/AJ/AN/Az-Am
TC51 41 o0AP/AJ/ASJ/AZ-1 O
TIMING WAVEFORMS
READ CYCLE
AO~A10 COLUMN
DoUT DATA - OUT
Eiir. "H" or "L"
TC51 41 MAP/AJ/AN/AZ-N, TC51 41 ooAP/A0/ASJ/Az-80
TC51 41 ooAP/AJ/ASJ/Az--1 0
WRITE CYCLE (EARLY WRITE)
AO-AIO COLUMN
DIN DATA - IN
Dour OPEN
Eg.. "H'' or "u"
TC5141MAP/AJ/ASJ/Az--70, TC51 41 o0AP/AJ/ASJ/AZ--8o
TC51 41 o0AP/AJ/ASJ/AZ-1 o
READ-MODIFY-WRITE CYCLE
AO-AIO COLUMN
ths DATA- IN
Door DATA - our
Eiil.. "H" or "L''
TC51 41 o0AP/Ad/ASJ/AZ--N, TC51 41 tX9P/AJ/ASJ/Az-80
TC51 41 ooAP/AJ/ASJ/AZ--1 0
FAST PAGE MODE READ CYCLE
ga.. "H" or "L''
A-1 03
TC51 41 tXW'/AJ/ASJ/Az--70, TC51 41 o0AP/AJ/AS0/Az--80
TC51 41 o0AP/AJ/ASJ/AZ--1 o
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
Vic ---
oom OPEN
.: "H'' or "L''
TC51 41 MAP/AJ/ASU/AZ-N, TC5141 MAP/AJ/AN/AZ-M
TC51 41 o0AP/AJ/AS0/AZ-1 o
FAST PAGE MODE READ-MODIFY-WRITE CYCLE
AO-AIO
Vos----
Eiir. "H'' or "L"
TC51 41 o0AP/AJ/ASJ/AZ-70, TC5141 00AP/AJ/ASJ/AZ-80
TC51 41 o0AP/AJ/ASJ/AZ-1 O
m ONLY REFRESH CYCLE
mar: 's, V "is.,.,
_ 'ic.y/'
"i-ii- "j,iggiggggigggggigggiggggggggg
7% : "H'' or "c"
TC51 41 MAP/AJ/ASO/AZ-N, TC51 41 o0AP/AJ/ASJ/Az--80
TC51 41 o0AP/A0/ASJ/Az--1 o
CM BEFORE m REFRESH QYCLE
A Mac '
' -------_
" - -k V
terrc _
" _ -H tcrm '
m " ___/ " /wt,,j,i; biiil)iij, 'ff)'),
twsu, ‘wrm
m:1:7//////////% ttii;; 'fjt,ii'tif,'i4tsi,i';Ct,'ii?ii,'
Dom l OPE N
VOL -----..,-a
Note: AO-AIO-- "H" or 'L'
'gfgr, t "H" or "L'' "lic)?.,'?:'
TC51 4100AP/AJ/ASJ/Az-70, TC51 41 MAP/AJ/ASU/AZ-M
TC5141 MAP/AJ/ASU/AZ-l 0
HIDDEN REFRESH t2LQig2fLUiALI21
Vit ---
A0--AI0 COLUMN
WWT'EV
Dom VOL - DATA-OUT
IE.. "H'' or "L''
TC5141 MAP/AJ/ASU/Az-ro, TC51 41 ooAP/AJ/ASJ/AZ-80
TC51 41 OoAP/AJ/ASJ/Az--1 o
HIDDEN REFRESH CYCLE (WRITE)
VIH -...
AO-AIO COLUMN
om DATA- IN
Dom OPEN
ga.. ''H. or 'L'
TC51 41 O0AP/AJ/ASJ/AZ-70, TC51 41 tXhiP/AJ/ASJ/Az-80
TC51 41 o0AP/AJ/ASJ/AZ--1 o
UAS BEFORE m REFRESH COUNTER TEST CYCLE
AO-AIO COLUMN
READ CYCLE
Dom DATA.- OUT
I WRITE CYCLE
/ Von -
Dom VOL -
ths DATA . IN
READ-MODIFY-WRITE CYCLE
Dour DATA . OUT
thr: ', DATA . IN
Ea.. "H" or "L''
TC51 41 ooAP/AJ/ASJ/AZ-70, TC5141 o0AP/AJ/ASJ/AZ-80
TC51 41 o0AP/AJ/ASJ/AZ-1 o
WRITE. CXS BEFORE RAS REFRESH CYCLE
:7: -:ii,,;ifti'ffg)rgiiEh, WTS
VOH--' R
Von. ----=.-.-:1.
" - 'is,
lhc - are
ii: .4
V:L --.-_,_y/ i)'
//////////////////////////////%
'////////////////////////%
'f/J) .. "H'' or "L''
TC51 41 o0AP/AJ/ASJ/Az-70, TC51 41 MAP/AJ/AN/AZ-M
TC51 41 o0AP/AJ/ASJ/AZ-1 o
TEST MODE
The TC514100AP/AJ/ASJ/AZ is the RAM organized 4,194,304 words by 1 bits, it is internally
organized 524,288 words by 8 bits. In "Test Mode", data are written into 8 sectors in parallel and
retrieved the same way. Alon, A100 and A00 are not used. If, upon reading, all bits equal (all"1"s or
"O"s), the data output pin indicates a"I". If any of the bits differed, the data output pin would indicate
a"0". Fig.1 shows the block diagram of TC514100AP/AJ/ASJIAL In 'Test Mode", the 4M DRAM can be
tested as if it were a512K DRAM.
”WRITE, (KS Before m Refresh Cyele"puts the device into "Test Mode". And“m Before m
Refresh Cycle" or "m Only Refresh Cycle"puts it back into "Normal Mode". In the Test Mode,
"WRTT‘E, CTS Before m Refresh Cycle"performs the refresh operation with the internal refresh
address counter. The "Test Mode"function reduces test timesW8 in case of N test pattern).
TC51 41 o0AP/AJ/ASJ/AZ-70, TC51 41 00AP/AJ/ASJ/Az--80
TC51 41 o0AP/AJ/ASJ/Az-.1 0
BLOCK DIAGRAM IN THE TEST MODE
Awn. Atoc, Aoc
Normal
Aum. Aux. A0:
512K block
AIDRrAIM- Ne Test
512K block
aum.ATCtx" 5 I 2K block
AIOII Aoc. Ne
512K block
Test - Dom
Am. Asoc,Ne
Normal
512K block
77A i7
ton uk Aoe 512K block
Non: KEN: Test
512K block
AnomAmz-Aoc Normal
512K block A]OR,A|OC,AOC
Fig. 1
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