TC5092AP ,CMOS Digital Integrated Circuit Silicon MonolithicGENERAL DESCRIPTION I
The TC5092AP is an integration 13-bit A/D converter
of high precision and ..
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SILICON MONOLITHIC
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. 4,194,304 word by lbit organization
. Fast access time and cycle time
TCS 1 AIO ..
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. 4,194,304 word by 1bit organization . Low Power
0 Fast access Lime and cycle time ..
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DESCRIPTION
PRELIMINARY
The TC514100AP/AJ/ASJ/AZ is the ..
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TC7W08FU ,DUAL 2-INPUT AND GATETC7W08F/FU/FKT(‘7WDRF "rf'mfunmul "rf'mhm$trit-‘vv. 'IVVI v,VVII‘The TC7WO8 is a high speed CZMOS 2 ..
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TC5092AP
CMOS Digital Integrated Circuit Silicon Monolithic
CZMOS DIGITAL INTEGRATED CIRCUIT T QZAP
SILICON M0N0LlTHl0
rIJ - I - I --
TC5092AP CZMOS 13-BIT A/D CONVERTER
GENERAL DESCRIPTION
The TC5092AP is an integration 13-bit A/D converter
of high precision and low power consumption.
The 13-bit, B-state data output is capable of
independent enable in h bits so as to be connected
directly to 4-bit/8-bit/12-bit data bus. (LSB is
common to lower order 4 bits.)
Further, since this converter has an 8-channel analog
multiplexer, and a serial clock output function, it
is most suitable as data collectibn unit of various
industrial control instruments.
1MP42(6D42A-P)
FEATURES:
. High precision ......... ...il LSB(Typ.)
. Low power consumption-nom/a.)
Single power supply ....... VDD=5ViO.5V
PIH ASSIGNMENT
. High-speed conversion.....fcp Max.---5MHz
8-channel analog multiplexer contained
. TLL/CMOS compatible digital Input/Output
. Capable of direct connection to 4-/8-/12-bit bus
APPLICATIONS:
. Various industrial control instruments DBle 1 42 VDD
. Data collection modules DELL 2 ll XIN
DBIO 3 IO XOUT
DB 9 t 39 GCKO
DB 8 5 38 HDEN
DB 7 6 . 37 Cl
r1,'t'l,A DB 6 7 36 ca
DB 5 8 '55 INTO
ABSOLUTE MAXIMUM RATINGS DB l 9 " INTJ
CHARACTERISTIC SYMBOL RATING UNIT DB 3 33 INTI
DB 2 32 AINO
DC Supply Voltage VDD VSS-0.5-VSS+7 V DB 1 31 AINl
Input Voltage VIN VSS-0.r-vDD+0.5 V DB 0 GO AINZ
EOC 29 A N3 Anal
33:22:” Supply VREF VAGND" VDD+0.5 V LDEN 28 Aim Inp‘ig
MDEN py AIN5
Analog Ground Voltage VAGND VSS-0.r-VREF V STC 26 AING
Output Voltage VOUT llsS-0.r-VDD+0.5 ll CHSZ 25 A1N7
DC Input Current IIN ilO mA CHSl " VREF
CHSO 23 1/2 VREF
Power Dissipation PD 300 mil vas 22 AGND
2,ecting Temperature Topr -ti0--85 °C (TOP VIEW)
:::;:ge Temperature Tstg -65--150 "C
35093»
FUNCTION OF EACH PIN
Tl Symbol NAME & FUNCTION ii? Symbo] NAME d FUNCTION
1 DBI_2, Reference voltage supply
2 ll terminal, which suppliesthe
BEN 23 REF/l on f VREF - AGND
3 DBIO V age o 2
DB 9 24 VREF Eefeienie voltage supply
5 DB 8 3-State Parallel erm na
6 DB 7 Data Outputs 25 AIN7 Analog Input terminal
Input voltage range:
7 DB 6 DB12 , MSB AGNDq‘VREF
8 DB 5 DB 0 : LSB 26 AIN6 Arbitrary input can be se-
9 lected by CHS input.
DB , 27 AINS
10 DB 3 CHSo CHSl CHS2 Am
11 DB 2 28 PINK L L L AINO
12 DB 1 , H L L AIN1
13 DB 0 29 1N3 L H L AINZ
End of Conversion A H H L AIN3
EOC goes to "L" level at the 30 1N2 L L H AINA
14 EOC fall of STC signal, and re-
turns to "H" level at the 31 A1N1 H L H AIN5
end of conversion. L H H AIN6
Low Data Enable 32 AINO H H H AIN7
15 LDEN DBOAJDBA are read by "H"
level input. Integrator Input
. _ Integrator Junction
Medium Data Enable
l6 MDEN 0135mm,B are read by "H" 33 INTI Integrator Output .
l 1 i t The Integrator consists of
téYEU npu . these three terminals.
Start Conversion
Conversion starts at thefall RI CI
time, if pulse input at "H" cr i. 9
17 STC level is provided. "L" level 34 INTJ
should be kept during con- INTI INTJ INTO
ver51on. ' R1 and C1 should satisfythe
l8 CHS2 Channel Select Inputs following formula and beset
These pins are addressinputs as small a value as possible
for selectin ei ht analo 13000
19 CHS g g g .
1 inputs of AmowAINL and 35 INTO RI C1 > fosc [sl
20 CHSo are taken 1nto the internal However R of 1 m 2NCI should
latch '
be used.
21 V . . .
SS Digital Ground 36 C Capacitors connection tervinals
22 AGND Analog Ground 2 for offset calibration.
FUNCTION OF EACH PIN
2f Symbol NAME & FUNCTION
0.1uF is connected between
37 Cl C2 and C1, and 0.01uF C1 and
VSS, respectively.
High Data Enable
38 HDEN DB91DB12 are read by "H"
level input.
Gated Clock Output
39 GCKO Pulses of ?umber equivalent
to conver51on data are out-
put during conversion.
Terminals for system clock
40 XOUT oscillation.
Crystal oscillators are con-
41 XIN nected to both the ends of
terminals.
42 VDD Supply Voltage 5Vi0.5V
TC5092AP
4-74-74—
Data Bus
HDENMDENLDENGCKOIO 1 2 3 4 5 6 7 8 9 10 11 12
6 39 3
SYSTEM DIAGRAM
EOC l4 l3—BIT DATA HOLD LATCH WITH PRESET FUNCTION
l3—BIT RIPPLE CARRY BINARY COUNTER
35 INTO
DETECTOR
STC l7
PHASE CONTROL 3“ INTJ
CIRCUIT
XIN 41 37 C1
XOUT 40 23 VREF/ 2
CHSl l9
CHSO 0
DECODER
VDD VSS VREF AGND 7
432101NTI
Analog Input F
TC5092AP
TC5092AP
TIMING CHART
PHASE 0 0' I II III IV 0
INTO VREF/Z
EOC f -
GCKO lllll ----------- I I
VINTI AGND VREF AIN AGND
T1 T2 T3(=T2) T4 AIN = VREF
---- AIN= VREF/2
-- AIN = AGND
FUNCTIONAL DESCRIPTION
(1) Conversion cycle
In the state of PHASE 0', the operation of L31 is at a stop and the integrating
amplifier performs as voltage follower. Under this condition the external capac-
tor (0.1uF across C1 and C2)
When STC is given, the offset voltage charged into external capacitors is applied
to non-inversion of the integrator, thus cancelling the offset volageequivalently.
In PHASE I, the integrator continues tointegrate AGND until its output reaches Vc,
In PHASE III the integrator integrates the analog input for the same period of
time as T2 after it has integrated VREF for a fixed period of time(T2) in PHASEII.
Finally, in PHASE IV the integrator continues to integrate AGND until its output
reaches VC.
" J- sl-rgi - - _ - "."
FUNCTIONAL DESCRIPTION
Let the time in PHASE IV be Ta. Then the
following equation is made (formed) by Voltage Follower PHASE 0
omitting error factors such as offset
drift. ' NO ®
VAIN = 2:: VREF (AGND=0v) ... (1) YES
Offset Correction PHASE O"
In case of this LSI, T2 is designed by _l" PHASE I
4096 x 2.T03C (TOSC denotes reference Calibration Cycle PHASE 11
clock synchronization). Therefore, the Analogilnput PHASE In
above formula letting 2'Tosc be T is Integration
changed as follows: I
Digital Conversion PHASE Ill
AIN - 4
-17i%7- _ 8192T .... ..... . ..... (2)
Thatis, 13-bit resolution A/D conversion
of FS (full scale)--- 8192 can be made by
Update Data
counting the period of T4 by use of a clock having T frequency.
However, it is recommended that RI and C1 composing the integrator be set to the
values close to lBOOO/fosc as possible after having satisfied the following
formula.
RICI > 13000 / fosc, R1 = 1 m 2MO is used. ........ (3)
Output data format
13-bit output data are output to 13 independent b-state data buses DBON D812.
Since 13-bit outputs can be independently placed on 3-state every group of High,
Medium and Low of 4 bits/4 bits/S bits from the higher order, it is easy to con-
nect the microcomputer to buses of 4, 8, 12 bits.
FUNCTIONAL DESCRIPTION
T05092AP
TRUTH TABLE
DATA OUTPUTS (DB)
LDEN MDEN HDEN Analog Input
2 3 4 5 6 7 8 9 10 ll 12
L L L Z
H L L D D D Z
L H L Z
H H L Don't Care D D D
L L H Z k Z D D D D
H L H D D D D D D D
L H H Z D D D D D D D
1/2LSBs3/2LSB L L L L L L L L
H H H ............ Straight Binary
"FS"-5/2LSBS"FS"-3/2LSB H H H H H H
"FS"-3/2 LSB < H H H H
Note : FS '.... Full Scale, 1 LSB --0IREF-AGND)/8l92, Z ... High Impedance
D ... "H" or "L" Level
(3) Basic clock
Since this LSI operates on the basis of the frequency given to XIN input, a
stable clock (Af< 0.005%) must be used for the clock to be given to XIN.
Therefore, it is proper that the oscillation circuit is configured as shown in
the following figure (a) by the use of externally mounted crystal becuase the
LSI has a built-in inverter for crystal oscillation.
XIN _Xo0T
-". 2.
External Clock
TC5092AP
FUNCTIONAL DESCRIPTION
(k) How to give STC input, Conversion time, and Sampling cycle
STC input is taken in with the reference clock of LSI, but the positive pulse
having the pulse width for at least two cycles is required for internal starting.
The conversion time of from the fall of STC input to the rise of EOC output.
Letting this time be Tc MAX(Maximum conversion time), then the following equation
is obtained.
TcMAx=41000xTOSC [s] ...... ........ ........... (4)
(where TOSC is oscillation cycle of basic clock.)
For example, when fcp=5MHz, TcMAX=8.2ms. For one-time sampling, an accurate
output can be obtained from the falling edge of STC input after the lapse of
TcMAX.
For consecutive sampling, however, STC input must be given after the lapse of a
given period of time (6ms) from the rise of EOC. This period (6ms) is the time
required for the recovery of LSI to normal state.
Therefore, the minimum sampling cycle TsMIN is as follows:
TsMIN = 41000 XTOSC~+ 0.006+tv(STC) [S] ........ (5)
Note: When power is set ON, following start-up procedure is required due to
indefinite state of internal circuitry.
1. Applying clock, STC is to be set high over lOms.
2. Complete at least one cycle as a dummy conversion cycle.
T smapling
EOC --'l
T conversion l 6ms
(5) Reference voltage
This LSI has three reference input voltage terminals of AGND’ s-iss, and'VREF.
Since analog input signal is quantized to 1/8192 in the range of AGND'VAREF for
digitization, stable voltages must be supplied to-%~VREF and VREF°
T§§992AP
FUNCTIONAL DESCRIPTION
EsPacially the value of %'VREF voltage has direct effects upon conversion ac-
curacy; therefore, it is recommonded that adjustment be made so as to agree out-
put data with analog input by actually making A/D convert by use of input volt-
age at FS (full scale) or 1/2FS level.
The left figure shows an example of re-
ference voltage supplying circuit.
C1 R, C3 are filter capacitors for pre-
venting reference voltage variations to
be caused by ripple or induction noise.
Generally the value of capacitor is
about 0.01’v0.1uF, though it varieswith
the system.
(6) BUS Interface
For connecting a microcomputer to BOS line, three independent enable terminals
are used. These three enable terminals permit the processing in the unit of k
bits (5 bits for the low order digit only). The microcomputer can be directly
connected to the BUS of 4ru12 bits easily by allocating proper address of micro-
computer to the TC5092AP.
(a)4Bit $$ r---o7
IInterface l
ETCASSSBP
(b) 8 Bit Interface (c) 12 Bit Interface
(h, Q1 Q2
LDEN MDEN LDEN MDEN
EDEN H EN
40 12 Ly-o
-0 F-o
o 10 lor-e
o --A9 .
r--4:)
4 Bit 8 Bit 2:8
12 Bit
TCSOQZAP
RECOMMENDED OPERATING CONDITION
ITEM SYMBOL MIN. TYP. MAX. UNIT
Supply Voltage VDD 4.5 5.0 5.5
Digital Input Voltage VIN 0 - VDD V
Analog Input Voltage VAIN AGND - VREF -
Reference Supplwaoltége VREF 4.0 - VDD ll
Analog Ground Voltage VAGND 0 0 0.5 v
ELECTRICAL CHARACTERISTICS (VDD= 5V k 10%, VSS= 0V, Ta= -40s850C)
ITEM SYMBOL TEST CONDITION VDD MIN. TYP. MAX. UNIT
Output High Voltage VOH IOH=-1uA,Digital output 5 4.9 5.0 - V
Output Low Voltage VOL 10L=luA, Digital output 5 - 0.0 0.1
DigitalInput except XIN 5 2.4 - -
Input High Voltage ll
IH XIN 5 4.5 - -
Digitallnput except XIN 5 - - 0.8
Input Low Voltage VIL
XIN 5 - - 0.5
Output High Current 10H 0H 2.4V 4.75 -1.0 - - mA
Digitaloutputexcept xOUT
O t ut Lo C ent I t VOL = 0.4V 4 75 l 6 - - atA
u p w urr 0L Digitaloutputexcept XOUT . .
Inn v03: 5.5V, DBirlsDB12 5.5 - 10-3 5
Output Disable Current IDL VOL: 0.0V, DBo‘JDBlz 5.5 - -10-3 -5
-- ,fi pA
1m VIN=5.5V,Digita1 input 5.5 - 10-5 1.0
Input Current _
11L VIL=O.0V,Digital input 5.5 - -1o-5 -1.0
AnalogSwitch Off-Leak IOFF Analog input/output 5.5 - 110-4 - HA
Analog Switch = - - ft
On Resistor RON RL 10kg 5
. ' VREF=V ',,,.., - -
Operating Consump- I Digital 'oolltput fCP SMHZ 5 2 mA
tion Current Digital open fcp=1MHz 5 - 1 -
input CND
TC5092AP
SWITCHING CHARACTERISTICS (vDo---5vh10ro, Vss==0v, Ta =25°c, CL=50PF)
ITEM SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Output Rise Time tTLH Digital output - 50 150
Output Fall Time tTHL Digital output - " 150
O t tE b1 Ti CZI, - 80 250
u pu na e 1me tZH LDEN
MDEN -DB Output ns
Output Disable Time tti HDEN - 280 500
Max. Clock Frequency fMAXqS XIN Duty 40~6OZ 5.0 - -
Min. Clock Frequency fMIN¢ XIN Duty 40-607, - - - MHz
CIN Digital input - 5 -
In ut Ca acit
p p y CIN Analog input - - - PF
3-State Output Capacity COUT DB Output - 8 -
SYSTEM CHARACTERISTICS (VDD= SViIOZ, Vss= 0V, Ta= 25°C)
ITEM SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Resolution n - 13 - Bit
fcp =TrTH, - - 8.2
Conversion Time Tc fCP = 1 MHz - - 41 ms
fCP = 5 MHz 14.2 - -
Sampling Cycle TSPL ms
fcp = 1 MHz 47 - -
Nonlinearity - ll
Zero Scale Error EZP - i2 LSB
Full Scale Error EFS VDD: VREF - (cl
STC Min. Pulse Width tw - - 2/fosc s
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