TC5048AP ,17-Stage High Speed Frequency DividerABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
CHRACTERISTIC SYMBOL RATING UNIT
VDDl v s -0.5ruv +10
..
TC5048P ,17-stage high speed frequency dividerCZMOS DIGITAL INTEGRATED CIRCUIT
SILICON M0N0LlTHIC
TC5036AP TC5048AP 17-STAGE HIGH SPEED FRE ..
TC5048P ,17-stage high speed frequency dividerABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
CHRACTERISTIC SYMBOL RATING UNIT
VDDl v s -0.5ruv +10
..
TC5070P ,C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHICABSOLUTE MAXIMUM RATINGS
CHARACTERISTIC SYMBOL RATING UNIT]
DC Supply Voltage VDD VSs-O.5-Vss+1 ..
TC5071P ,C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC555
BCD OUT SEGMENT OUT DIGIT OUT
(2°)(21)(22)(23) (MSD) (LSD)
ABCD abcdefg D6D5D4D3D2Dl
TC5072P ,C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC555
BCD OUT SEGMENT OUT DIGIT OUT
(2°)(21)(22)(23) (MSD) (LSD)
ABCD abcdefg D6D5D4D3D2Dl
TC7SZ34FE ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta = 25°C) Marking Product NameCharacteristics Symbol R ..
TC7SZ38FU ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta = 25°C) Pin Assignment (top view) Characteristics Symbol Rating Unit P ..
TC7SZ86F ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta=25°C) SSOP5-P-0.65A : 0.006 g (typ.) Characteristic Symbol Rating Unit ..
TC7SZ86FE ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta = 25°C) Marking Characteristics Symbol Rating UnitProduct Name Supply ..
TC7SZ86FU ,L-MOS SHS series (TC74LCX-equivalent)absolute maximum ratings. OUT Start of commercial production2002-06Note 3: V < GND OUT1 2014-03-0 ..
TC7SZU04AFE ,INVERTERElectrical Characteristics DC Characteristics Ta 25°C Ta 40~85°CTest Characteristics Symbol T ..
TC5048AP
17-Stage High Speed Frequency Divider
CZMOS DIGITAL INTEGRATED CIRCUIT
SILICON MONOLITHIC
mammmcamagfi;
TC5036AP TC5048AP 17-STAGE HIGH SPEED FREQUENCY DIVIDER
TCSO36AP and TCSOASAP are l7-stage ripple carry binary
counters equipped with Inverters for crystal
oscillators.
If il) input is opened (¢="L"), the inverted output of
9th stage appears on FC terminal. If i) input is set
to "H", 9 stages from 9th stage through 17th stage can
be also independently used having FC terminal as the
clock input.
Outputs can be derived arbitrarily from stages 4,12,
13, 14,15,16 and 17 of TC5036AP and stages h, 5,6,
7, 14,16 and 17 of TC5048AP.
DIP16(3D16A-P)
Both devicies are improved to
as same as others by changing
TC5036P and TC5048P to static
have 50% duty Q4 output
the divider stage of
type counter.
PIN ASSIGNMENT
ABSOLUTE MAXIMUM RATINGS
TGSOSGAP
CHRACTERISTIC SYMBOL RATING UNIT
V0131 v S -0.5mV +10 XT
DC Supply Voltage S 1 SSI V XT
VDDZ 1lss1-0.5'1plrimrH).5
XT V V -0.5n,V +0.5
Input Voltage IN SSI DD2 V Q12
¢, FC VIN VSSl-O'S NVDD1+0.5 Q13
Output Voltage VOUT 1rssr-0o5svmor'0.5 V 6
bc Input Current IIN :10 mA vssz
Power Dissipation PD 300 mw VSSI
Storage Temperature - 0 TOP VIEW
Range Tstg 65 m 150 C ( )
ead Temp./Time Tsol 260°C .10 sec T05048AP
TRUTH TABLE
INPUTS FUNCTION
RESET XT , FC (See Timing Chart)
OPEN H fQ4=fXT/2”
H n H * Q5le7="L" LEVEL
- f n=fXT/2n
L Cl OPEN Q9 n? 5 l 17
f =f /2n nt 5'm7
L f I H n Qn' XT ,
me=fFC/2(m 8) m; 12s17
* Don't Care (TOP VIEW)
Tim0ii!yu'.Htm048y'
BLOCK DIAGRAM
x-tlo--------; - Wm - $04 Wave rh'.
VDD2o----- Hy
xTe---- WT T-T OFT GM Q , T T T
K 5i fl
Irss2 t
RESET l f T T I f
o _ - _ - - -
R R R R R R
- T - T _T - T ...T -
%Q Q Q Q Q Q
TIMING CHART
XT(IN)
RESET(1N) I
(RESET: "L")
cuJ1fLrLfLrLrLrLrLrLr"LrLrLrLfulflr
Ig--- "H u .RESET = IILII)
TC5036AP, TC5048AP
RECOMMENDED OPERATING CONDITIONS (vss1=vss2=011)
CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNIT
V001 3 - 8
Supply Voltage VDD2 3 - VDDl V
Input Voltage VIN Except XT 0 - VDDl
Operating Temp. Topr -40 - 85 ' "c
ELECTRICAL CHARACTERISTICS (vssr--vss2=ov, VDD1=VD02)
-40°C 25°C 85°C
CHARACTERISTIC SYMBOL TEST CONDITION VDD UNIT
(V) MIN. MAX. MIN. TYP. MAX. MIN. MAX.
High Level Von IIOUT|
Output Voltage VIN=VDD’ vss 5 4.95 - 4.95 5.00 - 4.95 -
L L l I A
ow eve vor, I ourl<1y 5 - 0.05 - 0.00 0.05 - 0.05
Output Voltage VIN=VDD’ Vss
V =4.6V
High Level Q OH 5 -0.61 - -0.51 -1.0 - -0.42 -
Output VIN=VDD’ Vss
Output IOH
FC, VOH=4 .6V
Current - _ 5 0.025 - -0.02-0.06 - -0.015 -
XT VIN'VDD’ Vss mA
Q VOL=0.4V
Low Level 5 0.61 - 0.51 1.5 - 0.42 -
OUTPUT I VIN=VDD9 11SS
Output FC, 0L v0L=0.4v
Current - 5 0.10 - 0.08 0.25 - 0.06 -
XT VIN=VDD’ Vss
High Level _ V VOUT=0.5V, 4.5V
Input Voltage IH IIOUT|Low Level V VOUT=0.5V, 4.5V 5 l 2 2 _ _
Input Voltage IL [IOUT|High Level Input
Current IIH VIH=8V 8 - 0.2 - 10-5 0.2 - 1.0
(except XT, ')
Low Level Input
Current IIL VIL=OV 8 - -0.2 - -10-5 -0.2 - -1.0 PA
(except XT, b)
Quiescent I *
Device Current DDI VIN-VDD’ Irss 8 5 - 0.005 5 - 150
* All valid input combinations.
T65036AP, TC5048AP
SWITCHING CHARACTERISTICS
(VD01=VDD2, VSS1--VSS2---0V, Ta=25°C. CL=50pF)
CHARACTERISTIC SYMBOL TEST CONDITION 1131)) MIN. TYP. MAX. UNIT
o t t Rf Tf P t~LH
u pu lse 1me (a OUT UT) T 5 - 70 200 ns
Output Fall Time (Q OUTPUT) tTHL
Input Amp Vias Resistance Rf 8 0.6 1.6 3.0 M9
Propagation Delay Time (XT-Q4) tpLHstpHL 5 - 200 400 ns
Propagation Delay Time (XT-017) tpLHstpH1, 5 - 0.78 1.6 us
Propagation Delay Time (FC-RL?) tpLHstpHL 5 - 240 480 ns
Propagation Delay Time (FC-Ql7) tpLHstpHL 5 - 420 900 ns
Propagation Delay Time (RESET-Q) tpHL(RESET) 5 - 100 200 ns
Min. Pulse Width tw(RESET) 5 - 35 70 ns
Max. Clock Frequency fCL(XT) 5 10 20 - MH
Max. Clock Frequency fCL(FC) 5 8 l6 -
. R . T . t
Max Clock lse 1me rCL (XT) 5 No Limit
Max. Clock Fall Time thL
Max. Clock Rise Time trCL 5 20 - - us
Max. Clock Fall Time tfCL
Input Capacitance CIN except FC - 5 7.5 pF
100] TEST CIRCUIT
'li I l E l VDD=8V
t fi l
o-XT VDDl VDD2 FC,
VDD Or vss o- RESET
o- (Q5 'e' 97 Q14)
VSSl vss2 Q4 012 Q13 014 Q15 Q16 017
.‘NITCHING TIME TEST WAVEFORMS
TcsoseAP, T_C§048AP
I. fCL(XT)! tTLH, tTHL, tpLiO tpHL
2003 20ns
XT 50% F 50%
D 10% "
tTW Wm
90% 4'} 9096
Q4 50% 50%
10% ci.-.--..,
_ tTLH
tpLH -
Qn A- 10%
2. fCL(FC), tw(RESET), tpsa(RESET)
20:13 20mg
90 90% l N
FC 50% 50%
-a, 10% 's "
tWQRESET)
90% 90%
RESET 2 50% '
f 10% {10%
tTHL tTLH 2006 20ns
:2: 90
Q12 ,..-, Q17 10% 50% 50%
(p--- NH") JJ
tpHL tpLH tPHL
L, - I I
T 'PICAL APPLICATION
RESET gf V1302 VDDl
Tcso18APr"i1csos6AP) (05 06 £27 Q14)
XT Fr- vsse VSSl Q4 012 013 014 015 Q15 017 F0
J) DIVIDER OUTPUTS
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