TC5043P ,C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHICFEATURES:
. Wide time range of timer (5ms--1500Hr)
. Wide range of fine adjustment of oscilla ..
TC5048AP ,17-Stage High Speed Frequency DividerABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
CHRACTERISTIC SYMBOL RATING UNIT
VDDl v s -0.5ruv +10
..
TC5048P ,17-stage high speed frequency dividerCZMOS DIGITAL INTEGRATED CIRCUIT
SILICON M0N0LlTHIC
TC5036AP TC5048AP 17-STAGE HIGH SPEED FRE ..
TC5048P ,17-stage high speed frequency dividerABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
CHRACTERISTIC SYMBOL RATING UNIT
VDDl v s -0.5ruv +10
..
TC5070P ,C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHICABSOLUTE MAXIMUM RATINGS
CHARACTERISTIC SYMBOL RATING UNIT]
DC Supply Voltage VDD VSs-O.5-Vss+1 ..
TC5071P ,C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC555
BCD OUT SEGMENT OUT DIGIT OUT
(2°)(21)(22)(23) (MSD) (LSD)
ABCD abcdefg D6D5D4D3D2Dl
TC7SZ32FE ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta = 25°C) Marking Product NameCharacteristics Symbol Rating Unit Supply ..
TC7SZ32FU ,2 INPUT OR GATETC7SZ32F/FU'tq..--..-. '
TC7SZ34FE ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta = 25°C) Marking Product NameCharacteristics Symbol R ..
TC7SZ38FU ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta = 25°C) Pin Assignment (top view) Characteristics Symbol Rating Unit P ..
TC7SZ86F ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta=25°C) SSOP5-P-0.65A : 0.006 g (typ.) Characteristic Symbol Rating Unit ..
TC7SZ86FE ,L-MOS SHS series (TC74LCX-equivalent)Absolute Maximum Ratings (Ta = 25°C) Marking Characteristics Symbol Rating UnitProduct Name Supply ..
TC5043P
C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
CZMOS DIGITAL INTEGRATED CIRCUIT
SILICON MONOUTHm
TC5043P PROGRAMMABLE CR TIMER/DIVIDER
T05043P -_
TC5043P is an timer consisting of CR oscillation
circuit and frequency division circuit.
The oscillation circuit is made up by externally
installing one resistor and one capacitor, being able
to be set in a wide range of cycle. The frequency
division circuit consists of fixed stage of 1/1000
and variable stage of 1/1-l/600, being capable of
performing frequency division of 6 X 10 max.
Therefore, TC5043P can cover all the regions ranging
from conventional CR timers to motor timers.
This device is so designed that the external parts
required may be reduced to the minimum by means of
the built-in zener diode, auto reset circuit, and
pull-up/pull-down resistance.
FEATURES:
. Hide time range of timer (5ms--1500Hr)
. Hide range of fine adjustment of oscillation
DIPlei(CiDs6A-F)
PIN ASSIGNMENT
frequency (i502 or over) (TOP VIEW)
Low power consumption (2mu ..... Typ.)
. Little shpply voltage regulation of oscillation vss--1 ’\_/ 16- ZD
cycle (rg/v)
Narrow temperature variations of oscillation cycle ADJ--2 15-- VDD
(0.022/oc) OSCIN -T li.- Q/lO
. Internal auto reset function oscourr-it Ir-iT
Precision CR oscillation circuit TAD --,5 12__q
Internal zener diode ----
RESET _ 6 11_ S
Timer/Divider switchable '7 lo i',',"
Simple display of time elapsed of oscillation INHIBIT _ - l
Programmable frequency division ratio able to be ROUT-8 9-So
set in eight ways
APPLICATIONS:
Industrial timers
Timers for various commercial equipment
Low-frequency oscillators TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS TT m/D "fiisq OPERATION
CHARACTERISTIC SYMBOL RATING UNIT L m y. RESET
DC Supply Voltage VDD VSS-0.rs-VSs+12 H H H TIMER OPERATION
Input Voltage VIN VSS-0.r-vDD+0.5 H L H DIVIDER
TJi /10 _ “i2 V OPERATION
t t R V - . _ +
V31::ge 0E?’ Q VOUT SS 0 5 VSS H .8. L TEMPORARY STOP
Q,Q,OSCOUT VSS-0i-VDD+0.5 OF OPERATION
DC Input Current IIN ilO
mA til Don't Care
Zener Current Ig 10
Power Dissipation PD 300 mid
gperatlng Temperature Topr -40--85
ange 0
Storage Temperature W _ C
TC5043P
SYSTEM D I AGRAM
Internal
( Clock )
TIMER/BIVIDER INHIBIT So Si Se
o v s a e:
VDD VDD lOOWS
.24 A:
DECODER E Q (l
[7 V E -
OSCOUT i 2 Cl
m I JOSCILIATION FIXED FREQUEN CY "itftBpfiv7sri; R
j:' CIRCUIT DIVISION CIRCUIT CIRCUIT ii l,
C9 - 030w L I 4 I , 10
AUTO RESET V
VDD CIRCUIT V
0: CS 0 cs 0 9 CE
> ADJUST RESET ROUT * VDD ZD "DD
. Outputs marked with * are N-channel open drain structure.
TIMING DIAGRAM (1)
1. Timer operation, Programmable frequency division ratio 1/1
(T/D="H", W=”H", s0--Sr--s2----"H'')
RESET’ LI
080 --_------------ H
IN l VADJ v
I l I l l ss
OSCOUT l l l I I l ---l----'l_
._1 _ E
. For outputs marked with *, add pull-up resistance to VDD.
T05043P
TIMING DIAGRAM
2. Divider operation, Programmable frequency division ratio 1/1
(T/D="L", "tN1jrrCT---"H", S0=S1=S2--"L")
.J lOO'TOSC
l * - - -
10 - -
p____lOOO'TOSC ___4.___ 1000-TOSC ---
* Connect pull-up resistance to 10 output.
PIN FUNCTION
PIN NO. SYMBOL FUNCTION
1 Vss CND (0V) Pin
2 ADJUST Pin for fine adjustment for oscillation frequency.
Externally apply the voltage ranging from 0.2VDD to 0.55VDD.
3 OSCIN Oscillation circuit configuration pins t These pins start oscilla-
tion when resistor R is connected between OSCIN and OSCOUT and capa-
4 OSCOUT citor C between OSCIN and VSS, respectively. In case VADJ is 0.39Voq
oscillation cycle becomes almost TOSC=RC.
5 TIMER Timer/divider switching input.
IDIVIER At time of open (or "H" level), this device operates as a timer, and
at time of "L" level it operates as a divider.
All the counters are reset at "L" level. ht'the rising edge of this
input, the device begins to count.
When this pin is set at "L" level, the device keeps stopping oscilla-
7 INHIBIT tion during the period of "L" level state. The pin is used for tem-
porary stop of oscillation. f
Only at time of timer operation, reset signal is output. (At the
time when RESET = "L" and during the period of auto reset at the
rising time of power supply, output is off.)
For the divider mode, this pin should be open.
8 RESETOUT
SOWS3 are frequency division ratio switching inputs of the counter.
9 so Eight time intervals can be predetermined by combining pins, SO m S2.
( T = 1000 M
TC5043P
PIN NO. SYMBOL FUNCTION
S2 L H
SI L H L H
1 so L R L H L H L H
Time inter-,
vals oftime T 3T 6T 10T 60T 30T 300T 600T
11 S2 A In the divider operation mole, the above time intervals of timer
become half cycles of Q and Q.
12 Q Q and 6 are tine-up outputs. After the end of time intervals,
Q reaches "H" level and Q reaches "L" level. While the divider is
13 F operating, these outputs oscillate at double the cycle of time range
of timer.
Q Q/10 is a pin which outputs the elapsed time of timer, and outputs
14 - the pulse of 1/10 cycle of timer time.
10 . . .
This ls N-channel open drain output.
15 VDD Power supply pin
The cathode terminal of zener diode is put out of this pin. This pin
16 ZD . . . . .
IS used as a stabilized power supply by making the connectlon to VDD.
OPERATIONAL DESCRIPTION
C[F]).
1. Oscillation Circuit
0.2vnrrv0.55vmo.
The oscillation circuit can be made up by connect- 15
ing resistor R between OSCIN and OSCOUT and capacitor l VDD
C between OSCIN and VSS(GND) as shown in Fig. I. oscOUT 2
This IC has two levels of built-in reference m 3 OUTIN VR
voltage VH(0.62 von) and reference voltage VL(=VADJ) LD 1k VSS
externally supplied to ADJ pin, and performs osci11a- J; 1
tion in such a form as the charge and discharge wave ”L
of CR runs between these two levels.
Therefore, oscillation cycle can be adjusted by - = VDD
varying the voltage of ADJ pin. USCOUT
When VADJ% 0.39 VDD, the oscillation cycle is -:-vss
decided from the equation of TOSC=RC (T ' [S], R[Q],
VADJ should be used within the range of
Fig. 1 Oscillation Circuit
T650435
Counting circuit (Frequency dividing circuit)
This circuit consists of the fixed frequency dividing stage of 1/1000 and the
variable frequency dividing stage of 1/1 N 1/600.
Time intervals of timer can be predetermined in eight ways by combining three
inputs of SO W S2.
S2 L H Note 1.
Select SI L H L H T=1000'Tosc
so L H L H L H L H Note 2.
Time inter- "L" level
valsof Timer 3T 6T 10T 60T 30T 300T 600T may be open.
Reset operation
The internal counter is kept reset by the built-in
auto reset circuit until the power supply level reaches "ere-"-
. . 09%)
reset release voltage (VRD) at time of application of D
power. However, the power rising time of more than 500us VDD -lrm,
should be taken for abrupt rising edge of power supply - -CUVDD
because there may be no possibility of the internal
counter being reset. In case of the rising time of SOOus
or below, differentiation circuit is made up by adding BOUT
the capacitor to RESET terminal. (Refer to Fig. 2)
It is a matter of course that the internal circuit tr00PE
can be reset even by setting RESET input at "L" level.
When the reset operation is released, oscillating and
counting operations start. The reset signal is being
output to this IC. 1k
In case where this pin (ROUT) is internally reset,
it is off (at the rising time of power supply and during
"L" level of RESET); therefore, this pin can be used for
making the external circuit synchronize by use of pull-
up resistance or equivalent. While ROUT is not in use,
it should be kept set-open (or at "L" level).
Inhibit operation
Fig. 2 Auto Reset Circuit
Oscillation can be stopped by setting INHIBIT input at "L" level.
Normal operation can be performed by setting INHIBIT input open (or at "H" level).
Divider function
When the T/D pin is set open (or at "H" level), this device operates as a timer.
When this pin is set at "H" level, this divice can be used as a divider which continues
operating oscillation/counting without creating tine-up signal.
(Open or "L").
For the divider mode, however, ROUT cannot be used.
T05043P
RECOMMENDED OPERATING CONDITIONS (Vss=OV)
ITEM SYMBOL MIN. TYP. MAX. UNIT
Supply Voltage VDD 6.2 - 10 V
High Level Input Voltage VIH 0.8VDD - VDD
Low Level Input Voltage VIL O - 0.2VDD
External Resistor R 5K - 2M fl
External Capacity C 1000? - 5U F
'Output Voltage VOUT * Applcable to ROUT' 0./10 0 - 10 ll
ELECTRICAL CHARACTERISTICS (VSS=OV)
-hooc 25°C 85°C
ITEM SYMBOL TEST CONDITION VDD UNIT
(v) MIN. MAX. MIN. TYP. MAX. MIN. MAX.
' Iz=1mA 6.2 8.1 6.5 7.2 8.2 6.6 8.5
Zene V 1t e V - V
r o ag Z Iz=10mA 6.2 8.1 6.5 7.3 8.2 6.6 8.5
High Level I V0H=6V 7 -1.2 - -1.2 -2.5' - -1.0 -
Output Current OH VOH=3V -5.2 - -5.2 -9.0 - -4.0 -
Low Level I
7 1. - 1. 2.0 - 0.8 -
Output Current 0L voL=0.av 0 0
High Level V1H=10V,(Exclu- -3
Input Current IIH sive of 50m32) 10 - 5 - 10 5 - 5
Low Level 1'ur0v,(Exc1usive ll
I - 10 - -5 - - -3 - - -
Input Current IL of R‘INH-T/D) lO 5 5
Pull-up Resistance RPU R,TtTH','r/o Inputs - 7 50 10 20 50 10 75
Pull-down
R - 45 200 66 100 200 66 300
Resistance PO S0,SI,S2 Inputs
Output OFF Current IOFF vors1ov, Rour, 10 - 1.0 - 10-3 1.0 - 10.0 uA
Q/lO Outputs
Auto Reset Release V 2
Voltage RD - - - 2.6 - 5 - - V
Supply Current IDD C=0.luF, R=1MQ* 10 - - - 0.3 - - - mA
* All inputs and outputs are open.
EXAMPLES OF APPLIED CIRCUIT
T0?043P
o Timer Circuit I (Basic Type)
+ f AN ' .
O JVN EHSO‘SZ ----o
181588 d
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3515.3 x312.u 10 9
INPUT 1''F
, TCOO43P CUTPOT
n 1 2 3 4 t5 6 7 a
''I--liu-iC' 'tu'"
-o- "L " {RESET/START _o
(Time of timer can be varied to linear by using resistor R
deciding time constant with variable resistance.)
o Timer Circuit II (Elapsed Time Displaying Type)
15 E 14.B 12 2110 9 1615 " £512 2110S
INPUT T05043P TC1017BP
l 2 (S l 5 6 '7 8
l 2 3 l 5 6 7 8
TD62504P X 2
. ' j g f ' ' I OUIIUI
TIRlog X lo
7 181588
www.ic-phoenix.com
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