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TB3R1D
3.3V Quad PECL Receiver
• 3.5-ns Maximum Propagation Delay 40 kΩ that are
TB3R1 Provides 50-mV Hysteresisa logical high level input
• TB3R2 With -125-mV Threshold Offset forPreferred State Output• -0.5-Vto 5.2-V Common Mode Range Single 3.3V ±10% Supply Slew Rate Limited (0.5ns min 80%to 20%) TB3R2 Output Defaultsto Logic1 When
Left Openor Shortedto VCCor GND ESD Protection HBM>3 kV, CDM>2 kV Operating Temperature Range: -40°Cto Available SOIC (D) Package
APPLICATIONS Digital Dataor Clock Transmission Over
Balanced Lines
DESCRIPTIONThese quad differential receivers accept digital
over balanced transmission lines. They translate
differential input logic levels to TTL output BRF1A 2-kV CDMoffset, preferred and
