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TA8508AF
R/W IC FOR FLOPPY DISK DRIVE
TOSHIBA TA8508AF
TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA8508AF
R/W IC FOR FLOPPY DISK DRIVE
FEATURES
TA8508AF is a bipolar monolithic IC developed as a
read/write IC for perpendicular floppy disk drives (PFD).
TA8508AF consists of a floppy disk drive read circuit, a
write circuit, and various control circuits, all integrated on
a single chip to reduce disk drive size and power
consumption.
Power save function which reduces power dissipation (to
9mW typ.) during non-operation (not reading, writing, or .
erasing). Weight: : 0.56g(Typ.)
QFP44-P-1010-0.80B
5V single power supply (4.3V to 6.0V)
Incorporates a diode switch for switching between read and write heads. The differential voltage
gain of the read amp can be set to 200 times or 400 times using the gain select pin.
The write current can be set to a maximum of 25mADc using external resistance.
A built-in write current switching circuit allows the current value to be switched between outer and
inner tracks.
Read, write, and erase circuits are incorporated in a single chip and can be controlled independently
by W6 and E signals.
A built-in power monitor circuit prevents writing in error at such times as when the power is turned
on or abnormal voltage is applied.
Incorporates a time constant capacitor for the time domain filter. Time constants can be set using
an external resistor.
Incorporates a time constant switching circuit for the time domain filter. Time constants can be
switched between outer and inner tracks.
Incorporates a differentiator constant switching circuit. The differentiator frequency characteristics
can be switched.
1 2001-06-27
TOSHIBA
TA8508AF
PIN LAYOUT DIAGRAM/INTERNAL EQUIVALENT BLOCK DIAGRAM
@GAIN SEL A
@GAIN SEL 8
@GAIN SEL
@PRE OUT A
SPRE OUT B
@DIFF IN B
@DIFF INA
DIFF DAMPING CONTROL INPUT (DDCI)
@DIFF CONSTANT c (DCC)
@DIFF CONSTANT B (DCB)
l—QDIFF CONSTANT A (DCA)
HEAD o A (i2 E9 DIFF OUT B
8 PRE AMP DIFFERENTIATOR
HEAD 0 B Ci fE D DIFF OUT A
HEAD 1 A @ t D COMP IN A
HEAD CURRENT COMP IN B
HEAD 1 B Ci SWITCH SOURCE COMP D
5v SET (13 _r,'io,', MMVA COMP
AGND @ D POWER SAVE
WRITE DUMP A (iii Vcc D DGND
VOLTAGE 5 I
V - MONITOR 'g
WRITE DUMP B C/D, DD 't D MMVA
CMMON 1 (iii l fi' D MMVB
E o: - g
21 E y - 35 VDD
Vcc C E E I- Cii)
8 a CONTROL LOGIC
CMMON o Ci 5 Ci) MMVA CONTROL
t9 29 (29 Q9 © (29 2.9 Q9 Q9 (39 Q9
2 's E l 's E le le _ g ,
3 o p, m gl g g g E n: g
a 3 g m Lu G w
< ef. it up E r- m g 2
re - - g a.
w 3 E m = m 2
- it it
Take care when using pins 9, 11, 12, 13, 14, and 15, as the allowable overvoltage surge margin is
small (up to i100V).
TOSHIBA TA8508AF
EXTERNAL CONNECTION
I I PRE AMP DIFFERENTIATOR
HEAD MATRIX
HEAD CURRENT
SWITCH SOURCE
RMMVA COMP
18 v - 38
q Us CC VOLTAGE fr, 37L
, MONITOR -
tii? VDD- a g M
E RMMVA
cr, cis)-,,-:
2(1- o 36
sey a l fl RMMVB
g 5 - E
v 21 > - O—
5 -Ci E E F- 35
8 CI CONTROL LOGIC
E RAS E
NN', CO M P
3 2001-06-27
TOSHIBA
TA8508AF
PIN FUNCTION
PIN No. PIN NAME PIN FUNCTION
Differentiator constant select pin
1 'lit/ig?'?,),?,, Inputting low logic voltage selects pins 3 (DCB) and 4 (DCA);
inputting high logic voltage selects pins 2 (DCC) and 4 (DCA).
2 DIFF CONSTANT C Differentiator constant connecting pins
3 DIFF CONSTANT B These pins connect the differentiator constants between pins 4
4 DIFF CONSTANT A (DCA) and 2 (DCC), and between pins 4 (DCA) and 3 (DCB).
5 DIFF IN A Differentiator input pins.
These pins input a read signal from the pre-amp output pin to the
6 DIFF IN B differentiator via the filter circuit.
7 PRE OUT B Pre-amp output pins
These differential output pins output a read signal to the
8 PRE OUT A differentiator input pin via the filter circuit.
9 GAIN SEL Pre-amp gain select pins
10 GAIN SEL B AC coupling of pins 9 and 11 selects a 400-times pre-amp gain. AC
11 GAIN SEL A coupling of pins 10 and 11 selects a 200-times pre-amp gain.
12 HEAD 0 A Magnetic head 0 input/output pins
These pins connect the write/read magnetic head with a center tap,
13 HEAD 0 B and the damping resistor at a read.
14 HEAD 1 A Magnetic head 1 input/output pins
15 HEAD 1 B Another pair of input/output pins like those above.
V power select input pin
16 5V SET GEoCunding this pin selects Vcc=5V mode.
17 AGND Analog GND connecting pin
18 WRITE DUMP A Write dumping resistor connecting pins
The head dumping resistor is connected between these pins at a
19 WRITE DUMP B write.pin voltage at read and write.
Head 1 common driver connecting pin
20 COMMON 1 This pin connects to the center tap of magnetic head 1. It sets the
head 1 pin voltage at read and write.
21 VCC Analog power connecting pin
Head 0 common driver connecting pin
22 COMMON 0 This pin connects to the center tap of magnetic head 0. It sets the
head 0 pin voltage at read and write.
23 EGND Erase GND connecting pin
Erase current sink pin
24 ERASE OUTPUT Open collector pin for the erase current sink.
Connecting pin for write current compensation resistor
Between this pin and pin 26, connect a write current compensation
25 W/C COMP resistor RW COMP to set the write current increase (IWC).
. 1.3 - VWC
Equation 'WC- RW COMP(Q) x10(ADC)
Connecting pin for write current setting resistor
Between this pin and pin VDD 35, connect a write current setting
26 W/C SET resistor RW to set the write current value.
Equation IW-- Rw(Q) x10(ADc)
4 2001-06-27
TOSHIBA
TA8508AF
PIN No.
PIN NAME
PIN FUNCTION
WRITE CURRENT
Write current control pin (digital input)
When low logic voltage is input, the write current is defined as the
sum of IW and IWC. When high logic voltage is input, the write
current is IW only.
WRITE DATA
Write data input pin (Schmitt digital input)
The write data input pin is triggered when digital input goes from
high to low.
WRITE GATE
Write gate signal input pin (digital input)
Inputting low logic voltage activates the write.
ERASE GATE
Erase gate signal input pin (digital input)
Inputting low logic voltage activates the erase.
SIDE 1
Head side switching signal input pin (digital input)
Inputting low logic voltage activates head 1; inputting high logic
voltage activates head 0.
POWER ON
Voltage drop detection output pin
This open collector pin outputs low while at least one/both of the
VDD and VCC is/are below the specified value.
READ DATA
Read data output pin
This pin outputs the read data (totem pole type).
MMVA CONTROL
Time domain filter time constant switching signal input pin (digital
input)
Inputting low logic voltage narrows the output width of the first
monostable circuit.
Digital power connecting pin
Second monostable circuit R connecting pin for time domain filter
Connect the second monostable circuit time constant setting resistor
RMMVB. The following equation determines the second monostable
circuit's pulse width t2.
t2 = 27 X (RMMVB (k0) + 0.1) (ns)
First monostable circuit R connecting pin for time domain filter.
Connect the first monostable circuit time constant setting resistor
RMMVA. The following equation determines the first monostable
circuit's pulse width t1.
t1: 53.5x(RA (k0) +0.1) (ns)
Note: When MMVA CONTROL logic inEut voltage is high,
RA=RMMVA. When MMVA CONTROL logic input voltage is
high, RA = RMMVA/lRMMVA COMP.
Digital GND connecting pin
POWER SAVE
Power save mode select signal input pin (digital input)
Inputting low logic voltage selects power save mode, which reduces
R/W Ic power dissipation. During power save mode, read, write,
and erase operations are disabled.
(The power monitor circuit still functions.)
MMVA COMP
Resistor connecting pin for time domain filter time constant
switching. This open collector pin connects resistor RMMVA COMP
between this and pin 37 to compensate the output width of the
time domain filter's first monostable circuit.
COMP IN B
COMP IN A
Comparator input pins
A read signal is input to these two pins from the differentiator
output pins via the AC coupling capacitors.
DIFF OUT A
DIFF OUT B
Differentiator output pins
These two pins output a read signal to the comparator input pin via
the AC coupling capacitors.
5 2001-06-27
TOSHIBA
MAXIMUM RATINGS (Ta = 25°C)
TA8508AF
CHARACTERISTICS SYMBOL RATING UNIT
Power Supply Voltage VCC 7 V
Supply Voltage VDD 7 V
Digital Signal Input Voltage
- - . .%.. . V
(Note 1) 0 5 5 5
Voltage Applied to Power On 7 V
Pin (Note 2) -
Voltage Applied to Erase - 7 V
Output Pin (Note 3)
Voltage Applied to Head 0/1 - 7 mA
A/B Pins (Note 4)
Common Drive Source
Current ICOM 75 mA
Erase Drive Sink Current IE 50 mA
Write Drive Current
(Note 2) IW 25 mADC
Sink Current on Power On
. - 7 mA
Ambient Operating Ta - 20--75 "C
Temperature
Junction Operating Tj 150 "C
Temperature
Storage Temperature Tstg - 55~150 "C
Power Dissipation
(Ta =25°C for IC only) PD 0.75 W
(Note 5)
(Note1) The WRITE CURRENT, WRITE DATA, WRITE GATE, ERASE GATE, SIDE1,
MMVA CONTROL, POWER SAVE, DDCI signals are input to the 5V SET pin.
(Note2) Applies to POWER ON pin (pin 32).
(Note3) Applies to ERASE OUTPUT pin (pin 24).
(Note4) Applies to HEAD 0 A, HEAD 0 B, HEAD 1 A, and HEAD 1 B pins (pins 12, 13, 14,
and 15).
(Note5) For device usage conditions, see Figure 1 Power Dissipation (PN-Ambient
Tem peratu re (Ta).
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTICS CONDITIONS UNIT
Vcc, VDD supply voltage 4.3--6.0 V
Operating ambient o-tro ''C
temperature
6 2001-06-27
TOSHIBA TA8508AF
ELECTRICAL CHARACTERISTICS
(1) CURRENT DISSIPATION (Ta = 25°C, VCC = 5V, VDD = 5V)
CHARACTERISTICS SYMBOL CIR- TEST CONDITIONS MIN. TYP. MAX. UNIT
VDD Current Dissipation IDDR 1 - - 17.7 23.4 mA
In Read . . .
VCC Current Dissipation 'CCR 1 - - 7.5 8.6 mA
. VDD Current Dissipation IDDW 1 (Note 1) - 9.5 15.4 mA
In Write . . .
VCC Current Dissipation Iccw 1 - - 12.3 18.8 mA
In E VDD Current Dissipation IDDE 1 - - 9.4 13.9 mA
rase Vcc Current Dissipation ICCE 1 - - 12.6 19.2 mA
In write VDD Current Dissipation 'DDW+E 1 (Note 1) - 12.3 19.4 mA
+ Erase VCC Current Dissipation Iccw + E 1 - - 12.3 18.8 mA
In Power VDD Current ?.iss.ii_t.ion IDDPS 1 - - 1.35 2.7 mA
Save VCC Current Dissipation ICCPS 1 - - 0.27 0.4 mA
Total Power Dissipation PDPS 1 - - 8.1 15.5 mW
(Note 1) When Write Current lw--0
(2) POWER MONITOR (Ta =25°C, Vcc--ir-7v, VDD =0~7V)
CHARACTERISTICS SYMBOL CIR- TEST CONDITIONS MIN. TYP. MAX. UNIT
VDD, Vcc Positive Direction vT+ - - 4.0 4.2
Threshold - V
Voltage Negative Direction VT- - 3.6 4.0 -
Threshold Voltage Width VT+ -vr- - - - 150 - mV
Saturation Voltage When
Power On Pin (Pin 32) - - pe 13;: - - 0.4 v
Detection On SINK=
Leakage Current When PoweR
On Pin (Pin 32) Detection Off - - VDD>4.5V - - 10 pA
7 2001-06-27
TOSHIBA TA8508AF
(3) PRE-AMP, DIFFERENTIATOR, COMPARATOR (Ta =25°C, Vcc=5V, VDD=5V)
CHARACTERISTICS SYMBOL CIR- TEST CONDITIONS MIN. TYP. MAX. UNIT
Differential Voltage Gv1 2 Test Frequency f=1MHz 340 375 415 V/V
a. Gain GV2 2 Test Frequency f=1MHz 170 185 200
E Gain Attenuation
(0 F 2 - 8 12 - MH
ie Bandwidth (- 3dB) C z
b, COMMON MODE Input Sine Wave
2 Rejection Ratio CMRR - f=1MHz 200mVrms 50 - - dB
U . . . .
'ii Povyer Supply Rejection RSRR - Multiplexed sme wave 70 - - dB
m Ratio f=10kHz IVp-p
E Pff.trential Input RIN - f=62.5-625kHz 6.0 9.0 16.0 kn
I Resistance
Pffertntial Input CIN - f=250kHz - 24 - pF
Capacitance
Differential 1".ryt VIN - Atx 200 Gain 0.8 - 7.5 ml/p-p
Voltage Amplitude
Differential Output
V 2 - 2.0 3.0 - V -
Q Voltage Amplitude OUT p p
E Differential Out t
< pu I - - 3.0 4.0 5.0 mA -
ie Current Amplitude OUT p p
a.. . .
Differential Output
v - - - - 0.5 v
Offset Voltage OFS
Input Equivalent Noise Head Connected
Voltage EN 2 f=400Hz to 1MHz 4.0 6.0 pl/rms
Gain Attenuation
F - - 20 - - MH
Bandwidth (-3dB) CD Z
Differential Output
V - - - 2 - V -
s... Voltage Amplitude OUTD p p
i-' Differential Output
.9 v - - - 20 - mV
ts' Offset Voltage OFD
OJ . .
.52 Differential Input RIND - - 16 24 - k0
t5 Resistance
Differential Output
R - - - 200 - fl
Resistance OUTD
Sink Current
I - - 1.4 2.0 - mA
(Pins 2, 3, 4) SINKD
b- Maximum Differential
It Input Voltage VINC - - - 2 - Vp-p
a Amplitude
E Differential In
C) put R - - 20 32 - kn
U Resistance INC
8 2001-06-27
TOSHIBA TA8508AF
(4) TIME DOMAINNVAVEFORM SHAPING BLOCK(Ta=25°C, Vcc=5V, VDD=5V)
CHARACTERISTICS SYMBOL CIR- TEST CONDITIONS MIN. TYP. MAX. UNIT
Ir.st, Monostable Output Pulse t1 3 - 200 - 3000 ns
Second Monostable Output t2 3 - 100 - 1200 ns
Pulse Width
Saturation Voltage On MMVA
V - I =1 A - - V
COMP Pin MMC SINK Op 50 m
First Monostable Output Pulse
E 3 - - 18 - 18 "/
Width Precision TMI 0
Second Monostable Output
E 3 - -20 - 20 h'
Pulse Width Precision TM2 t)
Ir.st, Monostable Qutput P/se ETM1C 3 - -15 - 15 %
Width Compensation Precision
COMP Input
. f=62.5 to 500kHz
Peak Shift PS 3 Differential 1 A:
lnput=200mVp-p
Low Output Voltage VLOUT - IOL=2mA - - 0.5
. IOH = - 10PA 3.5 - -
a High Output Voltage VHOUT 10H = -0.4mA 2.8 - -
g Sink Current ISI RD - VOUT=0.8V 2 4 - mA
R Source Current Iso RD - VOUT=2.8V 0.4 1 - mA
g Rising Time tr At Read Output=0.5 to - - 25 ns
. . 3 2.2V With Load
Falling Time tf Capacitance Of 20pF - - 25 ns
TOSHIBA TA8508AF
(5) WRITE SYSTEM/ERASE SYSTEM (Ta =25°C, I/cc-IV, VDD=5V)
CHARACTERISTICS SYMBOL CIR- TEST CONDITIONS MIN. TYP. MAX. UNIT
Output voltage in write -
L selected VWCMH - lw=25mADC 4.4 - - V
q, . .
3 Output voltage In write
ts not-selected VWCML 0.2 V
C Output voltage in read
C) - -
E selected VRCMH 2.3 2.6 2.9 V
C) Output voltage in read
U - - - - .
not-selected VRCMH 0 2 V
Output current range ICOM - - - - 75 mA
" ERASE OUTPUT pin
(1) - = -
u?:': output saturation voltage VER IErase 50mA 0.2 0.5 V
ERASE OUTPUT pIn
l/l,?,: leakage current ILKER - - - - 15 pA
Ltd Erase current range IERASE - - - - 50 mA
Write current setting EW -8 - 8 0
. . - - A;
preasuon EWC - 10 - 10
erte current output DW - - - - 1 %
t, imbalance
.it Write current variable I - - - 20 mA
e, range (one side) W VDD = 5.0V, Ta = 25°C - - 28 DC
It". Write current
, compensation variable 'WC - - - - 5 mADC
range (one side)
W/C COMP pin
saturation voltage VWC - Isource =0.5mA - 50 300 mV
l-C. m Leakage Current ILKW - - - - 10 pA
ii?.'"; Saturation voltage VSAT - - - 2 - V
:t T"'"
605 Differential output
(y. fi capacitance COUT - - - 23 - pF
2: . .
- Differential output
0. - = - -
v resistance ROUT f 1MHz 280 kg
10 2001-06-27
TOSHIBA TA8508AF
(6) LOGIC INPUT/OUTPUT BLOCK (Ta = 25°C, VCC = 5V, VDD = 5V)
CHARACTERISTICS SYMBOL CIR- TEST CONDITIONS MIN. TYP. MAX. UNIT
Low Logic Input Voltage VLIN - - - - 0.8 V
+4 High Logic 1nput_1/oltage VHIN - - 2.0 - - V
D . PS Pin .
th. Lo Lo c - 0.4V A lied - - 50
E C: Cglrrent (Pin 39) ILIN ppll pA
Te Others - 0.4V Applied - - 250
9 High Logic Input Current .
I - 2.4V A I - - 1 A
C-,' (Pins 28, 29, 3o, 31) HIN1 pp ied 0 /1
e High Logic Input Current .
D - - -
E (Pin 27) IHINZ 2.4V Applied 130 pA
High Logic Input Current .
(Pin 34) IHIN3 - 2.4V Applied - - 80 pA
Negative Direction
73+, Threshold Voltage VLINS - - 0.8 1.0 - V
S?ia. (Input H -9 L)
DE Positive Direction
iii',:, Threshold Voltage VHINS - - - 1.6 2.0 V
fjia (Input L -9 H) V
Hysteresis Voltage Width (Ill'- - - 0.3 0.6 - V
w Write Data Maximum fIND - V|N=0.8~2.2V - - 12 MHz
t-f Input Frequency (50% Duty)
11 2001-06-27
TOSHIBA TA8508AF
(7) SWITCHING CHARACTERISTICS (Ta =25°C, Vcc=5V, VDD=5V)
CHARACTERISTICS SYMBOL CIR- TEST CONDITIONS MIN. TYP. MAX. UNIT
Recovery Time From p7; off-9DIFF Output 90 to
Power Save to Read - - - 1 2 ms
110% (Note 1)
SIDE1 50%-9Selected VCOM
Head Switching Time - - 90%, Head Pin and Common - - 4 ps
Pin Connected
Read to write mode - - i7i7iT" Off-9Selected VCOM 90% - - 1 ps
WD-Iw Delay - - W 50%-olw 50% - - 0.3 ps
Write Current Rise - - Lh =0mH - - 0.1 ps
rase o e to ea DIFF Output 90 to 110% ’1
w-ts E Off-s
. - - ' - 4
Read Recovery Time DIFF Output 90% 30 0 pS
Sink Current Rise and VDDC
Fall Time When Power . g
Monitor Detection - - Load (Pin 32) g E - - 100 ms
Turned Off or Off J; 3
Note 1 : When returning from power save to read mode, raise W6 and E to high level
10ps before P_S goes from low to high.
co When mounted on a 60x30x1.6mm
PCB (150°C/W)
© IC only (160°C/W)
PD MAX (W)
0 25 50 75 100 125 150 175
Ta (°C)
Fig.1 Power dissipation (PD) -
Ambient Temperature (Ta)
The TA8508AF maximum operating ambient temperature (Ta) is 75°C. However, refer to the above
graph when using, as the package's power dissipation (PD) varies according to the ambient
temperature.
TOSHIBA TA8508AF
TIMING CHART
Selected HEAD VCOM
RDT voltage
ACTIVE when low
HEADcurrent )()()()(
13 2001-06-27
TOSHIBA
TEST CIRCUIT
1. ICC, IDD
TA8508AF
HEAD 0, 1 A
. HEAD 0, 1 B r6
. 5V SET
"' . AGND DGND C 'TC-' o
. COMMON o, 1
Civ-- VCC VDD O-O) 5V
W/C W/C
E~OUT COMP SET w-ts E SIDE 1
A A A A A A
T , IT o
2. Gv. Fc. l/OUT, EN
MEASURE
V v v v
GAIN GAIN GAIN PRE PRE
SEL A SEL B SEL OUT A OUT B
-os1k'--() HEAD 0,1 A P. C)
._°/°_
-n-e, SW1 DGND C)
WWF O HEAD 0,1 B
J L. VDD C) 5V
-, gk) AGND
m COMMON o, 1
5V VCC
m E SIDE 1
(i) ? A
A pins or HEAD 0, 1 B pins, whichever pair is selected.
Note2 :
Turn SW1 off only when measuring EN.
When GV, FC, or VOUT is measured, the signal is input to either of the HEAD 0, 1
TOSHIBA TA8508AF
3. t1, t2, ETM1, ETM2, ETM1C, PS, tr, tf
COMP IN A
COMP IN B T'' c; _
-() 5V SET i,r,, .
MMVA COMP
-() AGND W VIN
sv-f) Vcc MMVA
MMVA CONT
WG E READ DATA
A r\ A
-MEASURE
VIN , 50%
Read data output 50%
Figure 3-1 t1, t2
(1) First and second monostable output pulse precision
Connect RMMVA to set t1 to lps and connect RMMVB to set t2 to 0.5ps. Observe t1 and t2 in
the read data output.
ETM1 and ETM2 are defined as: ETM1=(1-t1/1)x100(%)
STM2 =(1 -t2/0.5)x 100 (%) (t1 (ps), t2 (ps))
15 2001-06-27
TOSHIBA TA8508AF
(2) First monostable output pulse width compensation precision
Connect RMMVA, RMMVA COMP so that t1 to t'1 (the difference between t1 prior to pulse
width compensation and t'1 after pulse width compensation) is has.
Observe t'1 and t1 when 0.8V and 2.0V are applied to MMVA CONTROL.
EMT1C is defined as:
EMT1C: (1-(tl-t'1)/1) X 100 (%) (t1 (ps), t'1(ps))
(3) Peak shift
Read data output 50%
Figure3.2 P.S.
1 t -t
PS-- xl 1 2 |x100(%)
2 t1 +t2
(4) Read data output rise and fall times
Read data output
Figure3.3 tr and tf
16 2001-06-27
TOSHIBA
INTERNAL EQUIVALENT CIRCUITS
1. Pre-amp
TA8508AF
‘v’V‘.
SOO/JA
'I/VI/Ti:"-''" L mm
GND -H-GND
I ' Vcc
W. ms:
u," ","
_ " C)
GND l PRE
Cl . Cl .
ue. 'os
00:» 00:»
g lg C) " Q lg
-M- GND
GAIN SELECT
Differentiator
u-v--' a_J
DIFF IN DIFF CONST
TOSHIBA TA8508AF
w. Comparator
C0MPIN
GND-M T
GND-M M VDD
VDD(5V)
1 11kQ L
l Time domain
- I VDD as
m C) l M J l w
GND v. -r-M-UDD GND l it,
MMVA 1.
k COMP 'i,
MMVA CONTROL 1
<00 GND VDD
MMVA MMVB
RMMVA RMMUB
a 2001-06-27
TOSHIBA
5. W/C control
VDD(5V)
GND-M-M-VOD GND-M-M-VDD
W/C COMP WRITE CURR-ENT
Common driver output
Vcc(5V)
l Vcc(5V)
GND ++ VCC
GND-M-M-vc:
COMMON output
19 2001-06-27
TOSHIBA TA8508AF
7. WRITE GATE, ERASE GATE, SIDE1 interface pins
I i VDD (5V)
8. WRITE DATA interface pin
.r g. VDD (5V)
WRITE DATA o_,,Cirl
20 2001-06-27
TOSHIBA TA8508AF
9. Power monitor output 10. Erase output
ERASE OUT
POWER ON 0
GND -M-EGND
11. Read data output
I VDD(5V)
0 " F l"
o-), O READ DATA
TOSHIBA
TA8508AF
POWER SAVE interface pin
l VDD (5V)
“VV—iIL
POWER AVE
When the POWER SAVE pin is open or VLIN or less VLIN input,
power save mode is activated. Inputting more than VHIN deactivate;
power save mode.
22 2001-06-27
TOSHIBA TA8508AF
PACKAGE DIMENSIONS
QFP44-P-1010-0.8OB
Unit : mm
" 12.2i0.3
10.0i0.2
Weight .' 0.56g (Typ.)
TOSHIBA TA8508AF
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
24 2001-06-27
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