TA1303BFN ,MIXER / OSCILLATOR BUILT-IN FREQUENCY FOR VHF. CATV AND UHF BAND.TA1303BFNMIXER/OSCILLATOR BUILT-IN FREQUENCY SYNTHESIZER FOR VHF,The TA1303BFN is a single chip whi ..
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TA1303BFN
MIXER / OSCILLATOR BUILT-IN FREQUENCY FOR VHF. CATV AND UHF BAND.
TOSHIBA
TA1303BFN
TENTATIVE TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA1i303BFN
MIXER/OSCILLATOR BUILT-IN FREQUENCY SYNTHESIZER FOR VHF,
CATV AND UHF BAND.
The TA1303BFN is a single chip which integrates a PLL and a
MDCOSC for VHF, CATV and UHF band.
The control data conforms to 3-wire bus and " bus formats.
Bus-SW can be used to easily switch for easy tuner system
set-up.
Flat, compact package : SSOP30 (0.65 mm pitch)
FEATURES
MDCOSC block
It VHF-CATV bands : Mixer and Oscillator
o UHF bands : Mixer and Oscillator
o Built-in f amplifier
It Single f output terminal
PLL block
It Standard bi-directional " bus format control
3-wire bus format control
Tuning amplifier
4-bit bandswitch drive transistor
5-levels A/D converter (when " bus selected)
4 programmable chip addresses (when IZC bus selected)
0 Power on reset circuit
It 1/4 prescaler
SSOP30-P-300-0.65
Weight : 0.17g (Typ.)
18-bit and 19-bit automatical discrimination circuit (when 3-wire bus selected)
Frequency step : 31.25 kHz, 50 kHz and 62.5 kHz (at 4MHz X'tal used)
(Note) : These devices are easy to be damaged by high static voltage or electric fields.
In regard to this, please handle with care.
_. V B d
SCL/CL C [3) cc3< 8”)
oLocK—out
A/D-In
SDA/DA (n:
InterFace
Co m pa rator
ADR/EN @ _
Band‘l G:
BandZ (u:
Band3@ ®Vccz(digital)
Band4 6 ® IF OUT
MIX out1@ ®GNDB(digital)
®Vt—OUT
®X’tal
'is)"s'ir"'sr."p"i'(.
Band Driver
Programable
Divider
1/-:::Ci
UHF OSC
Base-Z
MIX outZ @ K
~ UHF OSC
_‘ Emitter—Z
ch (analog) (5;:
o/C, Band
N UHF OSC
Bus Selector IZC 3WIRE G ‘3 Emitter-1
a A UHF osc
GND1(ana|og)@ ‘0 Base—1
_‘ VHF OSC
VHF-in ‘
Q”: —I I °° Base
UHF-in1®
_. a _‘ VHF osc
UHF ”12 Q ‘7‘ Col lector
©GNDZ (ana log)
BLOCK DIAGRAM
TOSHIBA
TA1303BFN
TOSHIBA TA1303BFN
TERMINAL FUNCTION
PIN NAME FUNCTION INTERFACE
3-wire bus : clock data input i C?
Pc bus : serial clock data '
1 CL/SCL input . " I
Please refer the description 1kQ Cl
(Table. 1) on page 13. f
. i E GND3
jo VCCit
3-wire bus :data input .
IZC bus :serial data input/ I'
2 DA/SDA output t )s-l
Please refer the description (D- 209 lkQ g;
(Table. I) on a e 13. 'err
p g , >1 3
s, fl.
3-wire bus : enable data input E5 'ts
Pc : address select input
EN ADR . .
3 / Please refer the description 100Q -22t
(Table. I) on page 13. (g
This is power supply pin for (ii) .
30 VCC3 Band circuits. a Se VCC3
This can use, from 5V to 9V. tse :5:
Output can be controlled by . t
setting the band switch data. DATAI/F
Band1--Band4
U/V band can be switched by 5 0
setting the band switch data. ,
Please refer the description GND3
(Table. 5) on page 21.
‘4 0‘ Ln $>
3 2003-04-02
TOSHIBA TA1303BFN
['lll. PIN NAME FUNCTION INTERFACE
- cl c: Vcc1
1: 23:» $1.
8 The output terminal of MIXER. G) "-,,-i? 5’
MIX Output For tuning, connect a tank o-AAN-o
9 . . . Ci) .. »»
circuit between pms 8 and 9. v
T 7! K ()i- "st t'
I GND2
This is power supply pin for
10 VCC1 analog circuit -
A changeover switch of control
3-wine bus and standard " bus
11 BUS-SW are switches by the voltage
applied on this pin.
Please refer the description
(Table. 1, 2) on page 13 and 14.
- . GND3
12 GND1 This IS the ground pm for -
analog circuit.
13 VHF Input VHF-RF input. " m m
v GNDI
14 UHF-RF input. Ci? c; C}
15 UHF Input It is possible to input either m m
balanced or unbalanced circuit.
. ' Vcc1
VHF oscillator pins l G8 L
16 In case of production abnormal Ci?, O
. . . . i 18
18 VHF Oscillator osc1||at|on,‘connect a resistor LL E mfg
between pin1 and the external 1: g“ m w" a:
capacitor.
f GND2
17 GND2 This IS the ground pin for -
analog circuit.
4 2003-04-02
TOSHIBA
TA1303BFN
['lll. PIN NAME FUNCTION INTERFACE
. ' ' Vcc1
l l Sk i9; l
19 (i)) 2 5 Cia)
20 . UHF oscillator pins. (io) (i)
HF ll . . . .
21 U Osci ator They are colpitts oscillator. (ji; E
22 7: E O C) x x
23 GND2 This IS the ground pm for -
digital circuit.
- Vcc1
Output terminal of IF signal
24 IF -(i))
Output which output impedance, 75 n. Ci?
This is power supply pin for
25 VCC2 digital circuit. -
r tf) St fir: 9 12PF
Crystal oscillator input. (is) {AEK
26 X'tal At this block, the reference . -
signal is generated. 1:
. .. GND3
- VCC2
27 Charge Pump 1000 2009
Output C2rD-
Tuning voltage output terminal. "l
This LSI has a built-in tuning r cg
amplifier. Cl
_ S GND3
28 NF L
'- VCC2
TOSHIBA TA1303BFN
m,“ PIN NAME FUNCTION INTERFACE
At 3 wire bus mode : VCC2
this functions as lock detector. Cg g
If the PLL has locked, the 2m '- N li,
output becomes low. T 3
At IZC bus mode : 193:0
29 ADC/LOCK this functions as terminal of AD . I t
convertor.
This converts the input voltages
into proper digital data.
Please refer the description
(Table. 6) on page 21.
MAXIMUM RATINGS (Ta = 25°C)
CHARACTERISTIC SYMBOL RATING UNIT
MIX-OSC VCC1 6 V
Block fIN 120 dBpV
VCC2 6 V
PLL Block Vcc3 12 V
VBT 38 V
. . . 780 iIC only]
Power Dissipation PD (Note) mW
Operating Temperature Topr -20-85 ''C
Storage Temperature Tstg - 55~150 "C
(Note) When using the device at above Ta
for each increase of 1°C.
OPERATING CONDITION
= 25C°, decrease the power dissipation by 6.3 mW
PIN No. SYMBOL MIN. TYP. MAX. UNIT
10 MIX-OSC block VCC1 4.5 5 5.5 v
25 Vcc2 4.5 5 5.5 v
PLL I k
30 b oc Vccg VCC2 - 9.9 V
6 2003-04-02
TOSHIBA TA1303BFN
ELECTRICAL CHARACTERISTICS
PC CHARACTERISTICS (Unless otherwise specified, VCC1 = 5V, VCCZ = 5V, VCC3 = 9V, Ta = 25C°)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
CUIT BAND
Power Supply and Icc1-1 VHF - 24 32 40
Current 1 Icc1-2 UHF - 26 34 43
Power Supply and
Current 2 ICCZ - - 12 16 21
1 Band switch : 1 Band ON mA
ltX3-1 - IBD = 30 mA (LOAD) - 34 36
Power Supply and .
Current 3 Band switch : 2 Band ON
lcc3-2 - IBD = 40 mA (TOTAL - 48 52
7 2003-04-02
TOSHIBA TA1303BFN
ELECTRICAL CHARACTERISTICS
MIX.OSC block (Unless otherwise specified, VCC1 = 5V, VCC2 = 5V, VCC3 = 9V, Ta = 25C°)
CHARACTERISTIC SYMBOL TchgT TEST CONDITION (*) MIN. TYP. MAX. UNIT
CUIT BAND
VHF fRF = 55.25MHz 21 24 27
Conversion Gain CG 3 VHF fRF = 367.25 MHz 21 24 27 dB
(Note 1) UHF fRF = 373.25MHz 25 28 31
UHF fRF = 801.25MH2 25 28 31
VHF fRF = 55.25MHz - 11 13
Noise Figure NF 3 VHF fRF = 367.25 MHz - 11 13 dB
(Note 2) UHF fRF = 373.25MH2 - 8.5 11
UHF fRF = 801.25MHz - 9.5 12
VHF fRF = 55.25MHz 6 8.5 -
IF Out Power Level VHF f = 367.25 MHz 6 8.5 -
(Note 3) Tp 3 UHF 1:: = 373.25MHz 6 8.5 - BmW
UHF fRF = 801.25MH2 6 8.5 -
VHF fRF = 55.25MHz - - 10.5
Conversion Gain Shift VHF fRF = 367.25 MHz - - $0.5
C65 3 dB
(Note 4) UHF fRF = 373.25 MHz - - $0.5
UHF fRF = 801.25MH2 - - 10.5
. VHF fosc = 101MHz - - 1100
frequency s1ift (The PLL VHF fosc = 413 MHz - - 1150
IS not operat1ng()NOte 5) MB 3 UHF fosc = 419 MHz - - , 150 kHz
UHF fosc = 847 MHz - - 1150
. . . VHF fosc = 101MHz - - 1100
'jy.it.ching On Dlft (The VHF fosc = 413 MHz - - A200
PLL IS not "era)'),') 6) nfs 3 UHF fosc = 419 MHz - - 1150 kHz
o e UHF fosc = 847 MHz - - 1200
VHF fl) = 55.25 MHz 81 85 -
1% Cross Modulation VHF fo = 367.25 MHz 80 84 -
(Note 7) CM 3 UHF fD = 373.25 MHz 76 80 - dB/A/
UHF fD = 801.25 MHz 76 80 -
VHF f0 = 55.25 MHz 49 54 -
3rd Inter Modulation IM3 3 VHF fl) = 367.25 MHz 50 55 - dB
(Note 8) UHF f0 = 373.25 MHz 38 45 -
UHF fD = 801.25 MHz 38 45 -
6-ch Beat f = 83.25 MHz
(Note 9) B6 3 VHF i,','--" 87.75 MHz 49 50 - dB
fosc = 167 MHz (A-ch),
Prescaler Beat 173 MHz (B-ch),
(Note 10) Bpre 3 VHF 179 MHz(C-ch), - 13 18 dB/A/
185 MHz (D-ch)
(*) IF .' 45.75 MHz
8 2003-04-02
TOSHIBA TA1303BFN
PLL block (Unless otherwise specified, VCC1 = 5V, VCC2 = 5V, VCC3 = 9V, Ta = 25C°)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Bandswitch Drive IBD 1 Maximum drive current/1 port - - 30 mA
Current
Bandswitch Drive . .
Maximum LOAD IBDMAX 1 Maximum total drive current - - 50 mA
Bandswitch Drive VBD
Voltage Drop Sat 1 IBD - 30 mA - 0.15 0.2 V
Tuning Amplifier Output - -
Voltage (Close Loop) Vt Out - VBT - 33 V, RL - 33 [k0] 0.3 - 33 V
Tuning Amplifier -
Maximum Current Wt - VBT - 33V - - 3 mA
fttl Negative XtR 1 1 2.5 - kfl
Resistance
X'tal Operating Range OSC fin 1 - 3.2 - 4.5 MHz
X'tal External Input .
Level OSCm 2 - 100 - 1000 mup-p
Lock Output Low VLKL 1 (Lock mode, 3-wire bus mode) - - 0.4 V
Voltage
Lock Output High VLKH 1 (Unlock mode, 3-wire bus mode) 4.6 - - V
Voltage
Logic Input Low Voltage VBsL 1 Pins 1 to 3 -0.3 - 1.5
Logic Input High VBsH 1 Pins 1 to 3 3 - VCC2 v
Voltage +0.3
Logic Input Current Pin 1 -20 - 10
IBsL 1 .
(Low) Pin 3 -55 - -20 A
Logic Input Current IBsH 1 Pin 1, Pin 2 -10 - 20 ’1
(High) Pin 3 75 - 150
Bus-SW Low Input VBIL 1 - 0 - 0.8
Voltage V
Bus-SW High Input
Vlotage VBIH 1 - 4.2 - VCC2
Bus-SW Low Current
IBIL 1 - -2 - - A
(Low) 00 F‘
Bus-SW Low Current
(High) IBIH 1 - - - 200 pA
= + + +
Charge Pump Output Ichg 1 CP 101 A30 -60 -90 PA
Current CF: ' 1 J i 140 1280 1420
ACK Output Voltage VACK 1 'SINK = 3 mA (IZC-bus mode) - - 0.4 V
9 2003-04-02
TOSHIBA TA1303BFN
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN. TYP. MAX. UNIT
Set-up Time Ts 2 - -
Enable Hold Time TsL 2 - -
Next Enable Stop Time TNE 6 - -
Next Clock Stop Time TNC (3-wire bus mode) 6 - - #5
Clock Width Tc Refer to data timing chart 2 - -
Enable Set-up Time TL 10 - -
Data Hold Time TH 2 - -
SCL Clock Frequency fSCL 0 - 100 kHz
Bus Free Time Between
a STOP and START tBUF 4.7 - -
Condition
Hold Time (Repeated)
START Condition tHDiSTA 4.0 - -
Low Period of the SCL t - 4 7
Clock LOW . ps
High Period of the SCL
Clock tHIGH 2 4.0 - -
. (I C bus mode)
Set-up Time for a Refer to data timing chart
Repeated START tSU;STA 4.7 - -
Condition
Data Hold Time tHD;DAT 0 - -
Data Set-up Time tSU;DAT 250 - -
Rise Time of both SDA
and SCL Signals tR 000 ns
Fall Time of both SDA
and SCL Signals tF - - 300
Set-up Time for STOP
. . - - s
Condition tSU'STO 4 0 #
10 2003-04-02
TOSHIBA TA1303BFN
MSB MSB- 1
Data x CD LSB+1 x LSB )1
Clock I k g ' t,1 g t Vi'
‘Ts Tc TH
Enable
TL TSL TNE
Fig.1 3-wire bus data timing chart (Falling edge timing)
_i',',,i,/.,r, 11—\
Fig.2 " bus data timing chart (Rising edge timing)
1_______ _
I______l____l>_1_
tLow tR tF
. . . I
. tHD;STAI _) _ . _) l.-
tHD;DAT tHIGH tSU;DAT tSU;STA
u________
REFERENCE DATA (VCC1 = 5V, VCC2 = 5V, Vcc3 = 9V, Ta = 25C°)
CHARACTERISTIC SYMBOL Eli: BAND TEST CONDITION MIN. TYP. MAX. UNIT
VHF fosc = 101 MHz-Hex = 173 MHz - 40 -
Lock Up Time Lupt 3 VHF fosc = 179 MHz-Hex = 413 MHz - 60 - ms
UHF fosc = 419 MHz-Hose = 847 MHz - 30 -
f = 55.25 MHz(- 30dBmWhA)
VHF ig = 1 I] _ fref = 15.625 kHz) - 65 -
VHF fRF = 367.25 MHz(-30dBmWhh) - 60 -
Reference Leak fref 3 (CP = f 1 J _ fref = 15.625 kHz) dB
Suppression Level S/I UHF fRF = 373.25 MHz(-30dBmWhh) - 48 -
(CP = 1 l] _ fref = 15.625 kHz)
UHF fRF = 801.25 MHz(-30dBmWhh) - 53 -
(CP = 1 1 J _ fref = 15.625 kHz)
Local Oscillator Leak VHF fosc = 101 MHz--fosc = 173 MHz - -36 -
Level (To IF Output) LOIF 3 VHF fosc = 179MHz--fosc = 413 MHz - -36 - dBmW
[Worst Case] UHF fosc = 419 MHz--fosc = 847 MHz - -28 -
1 1 2003-04-02
TOSHIBA TA1303BFN
TEST CONDITIONS
(Note 1)
(Note 2)
(Note 3)
(Note 4)
(Note 5)
(Note 6)
(Note 7)
(Note 8)
(Note 9)
(Note 10)
Conversion Gain
fRF input level = -30dBmW
Noise Figure
Noise Figure meter used.
IF Out Power Level
Measure f output level when it is maximum level.
Conversion Gain Shift
The Conversion gain shift is defined as a change in conversion gain when supply
voltage varies from VCC = 5 to 4.5V or from VCC = 5 to 5.5V.
Frequency Shift (The PLL is not operating)
The frequency shift is defined as a change in oscillator frequency when supply voltage
varies from VCC = 5 to 4.5V or from VCC = 5 to 5.5 V.
Switching On Drift (The PLL is not operating)
Measure frequency change from 2 seconds after switching on to 3 minutes.
1% Cross Modulation
o fd = fp (deF input level = -30dBmW)
0 fud = fp + 12 MHz 100 kHz, 30%AM
Input two signals, and increase the fudRF input level.
Measure the fudRF input level when the suppression level reaches 56.5 dB.
3rd Inter Modulation
o fd = fp (deF input level = -30dBmW)
o fud = fp + 1 MHz (fudRF input level = -30dBmW)
Input two signals, measure the suppression level.
6-ch Beat
0 fp = 83.25 MHz (prF input level = -30dBmW)
0 fs = 87.75 MHz (stF input level = -30dBmW)
Input two signals, measure the suppression level IF output signal between below
signals.
fudif1 = (fp + fs) - fosc = (83.25 + 87.75) - 129 = 42 MHz
fudif2 = (2 x fs) - fosc = (2 x 87.75) - 129 = 46.5 MHz
Prescaler Beat
0 1/4fosc(A-ch)=1/4 x 167 = 41.75 MHz
0 1/4fosc(B-ch)=1/4 x 173 = 43.25 MHz
It 1/4fosc(C-ch)=1/4 x 179 = 44.75 MHz
0 1/4fosc(D-ch)=1/4 x 185 = 46.25 MHz
As for each channel, measure the level to IF output.
12 2003-04-02
TOSHIBA TA1303BFN
PLL BLOCK
Operation description
TA1303BFN can be controlled with either by 3-wire bus or standard " bus.
The 3-wire bus mode is eqvipped with an 18-bit/19-bit automatic selection circuit.
Frequency steps can be switched, depending on the voltage applied to the BUS-SW pin.
The IZC bus conforms to the standard IZC bus format. The bus supports two-way bus
communications control, consisting of WRITE mode where data are received and READ mode
where data are transmitted. In READ mode, the voltage applied on the A/D converter input pin
can be transmitted and output with 5-Ievel resolution. (This function is only valid when the "
bus is selected. When the 3-wire bus is selected, the A/D converter input pin functions as the
LEE output pin.)
Addresses can be set using the hardware bits. 4 programmable addresses are supported. 3-wire
bus and standard " bus are switched by the voltage applied on the BUS-SW pin.
When the supply voltage (VCCZ) is applied, the power-on reset circuit operates. Before data are
input, counter data are all initialized to l ol ; band switches are all initialized to off.
Function chart
Table. 1
PIN NAME 3-WIRE BUS " BUS
BUS-SW [OPEN] or lvccl (GND]
CL/SCL CLOCK INPUT SCL INPUT
DA/SDA DATA INPUT SDA IN/OUTPUT
EN/ADR ENABLE INPUT ADDRESS
[0ch / ADC EocE ADC
o 3-Wire bus communications control
The 3-wire bus uses normal 18-bit and 19-bit data (band switch information and programmable
divider information) and 27-bit test data (charge-pump current setting, tuning amplifier on/off,
reference frequency divider ratio setting, and testing item functions) are available.
The program frequency is sequentially calculated together with normal data and test data.
fosc = fr x 4 x N
fosc: Program frequency
fr : Phase comparator reference frequency
N : Divider ratio
13 2003-04-02
TOSHIBA TA1303BFN
(1) Normal data
Depending on the voltage (OPEN, VCC) applied on the BUS-SW pin and the transfer DATA bit
length, the X'tal divider ratio setting, phase comparator reference frequency, and step frequency
of the normal data are as shown in the table below.
Normal data function table
Table. 2
BUS-SW INPUT TRS'AVTSKER X'TAL RATIO Ji'?jljitfi, STEP FREQUENCY
[UCC] 18-bit Cannot be set - -
fvccj 19-bit 1/320 12.5 kHz 50 kHz
[OPEN] 18-bit 1/256 15.625 kHz 62.5 kHz
[OPEN] 19-bit 1/512 7.8125 kHz 31.25 kHz
(Note 1) The step frequency at 4MHz (X'tal used)
(Note 2) During OPEN, automatically set with transmitted bit length (18619 possible)
4-bit band
Invalid data I switch data 14-bit programmable counter data I Invalid data
4 3 2 1 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
Clock fl fl fl fl fl II fl fl fl fl II fl fl fl II II fl fl fl II
Enable _| l,
-Tirne 1
Fig.3 Normal data format (18-bit transmission)
4-bit band
Invalid data I switch data
4 3 2 1 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
15-bit programmable counter data 1 Invalid data
Clock II II fl II II II II II II II II fl fl II II II fl II II II fl
Enable -l l-.
-Tirne f
Fig.4 Normal data format (19-bit transmission)
14 2003-04-02
TOSHIBA TA1303BFN
18-bit DATA TRANSMISSION :
During a high level of the enable signal, the data is clocked into the register on the falling
edge of the clock.
Data are latched under the condition that the number of clocks while the enable signal is
high is 18bits (the number of clock rising edges is 18).
Data are latched on the falling edge of the enable signal.
At 18-bit data transfer, N14 of the program divider is always automatically set to ' ol , the
phase comparator reference frequency divider ratio is set to 1/256.
Please refer the description (Fig1. 3-wire bus data timing chart) on page 11.
19-bit DATA TRANSMISSION :
During a high level of the enable signal, the data is clocked into register on the falling edge
on the clock.
Data are latched under the condition that the number of clocks while the enable signal is
high is 19bits (the number of clock rising edges is 19).
Data are latched on the falling edge of the enable signal.
At 19-bit data transfer, depending on the BUS-SW, the phase comparator reference frequency
divider ratio is set to either 1/320 or 1/512.
Please refer the description (Fig1. 3-wire bus data timing chart) on page 11.
15 2003-04-02
TOSHIBA TA1303BFN
(2) TEST MODE
In the test mode, the settings can be changed and the function can be checked.
Change from the normal mode to the test mode with a 27-bit or more of clocks and data
transmission during a high level of the enable signal.
The data are latched at the 27th falling edge of the clock signal, validating the previous 27-bit
data. The latch timing is the same as normal data.
The 4-bit bandswitch data and the programmable divider data are latched at the 20th bit rising
edge of the clock signal, and the data is updated.
The test data are latched at the 27th bit falling edge of the clock signal, and the data is
updated.
When the mode is changed from test to normal, RSa changes depending on the data bit length
(18 or 19 bits, automatic discrim ination). The data set in RSb in test mode are retained (see the
table below).
REFERENCE FREQUENCY DATA SET REFERENCE
DIVIDER RATIO SETTING TRANSMISSION FREQUENCY DIVIDER
TEST MODE LENGTH RATIO
18-bit 1 /256
1/256 19-bit 1/512
18-bit 1 /320
1/320 19-bit 1/320
18-bit 1 /256
1/512 19-bit 1/512
4-bit band
Invalid data I switch data Counter I Control data I Invalid data
B4 B3 B2 B1 N14 - NO TO
Enable -(. Time f f t
Band SW Counter data latch Control data latch
data latch
Fig.5 Test data format
(*) The data timing is the same as normal data.
16 2003-04-02
TOSHIBA TA1303BFN
TEST DATA SPECIFICATIONS
o B4--1 : Band drive data
l ol : OFF
I 1 J : ON
When band drive data is ' 1 1 either Band 1 or Band 2, VHF mode.
When band drive data is [ol both Band 1 and Band 2, UHF mode.
It N14--NO : Programmable counter data
0 CP : Charge-pump output current
lol '. +-60PA (Typ.)
f Il 2 i280 pA (Typ.)
It T2, T1. T0 : Test bits
0 T2, T1, T0 : Test mode setting
CHARACTERISTIC T2 T1 T0 REMARKS
Normal Operation 0 0 x -
OFF 0 1 x Charge pump is "OFF" (Check output : NF)
Charge-Pump Sink 1 1 0 Only charge pump Sink current is "ON" (Check output : NF)
Source 1 1 1 Only charge pump Source current is "ON" (Check output : NF)
Reference Signal . -
Output 1 0 0 Reference signal output oc
1/2 Counter Divider 1 0 1 1/2 counter output : Ltock'
Output
x : Don't Care
(Note) When testing the counter divider output, programmable counter data input is necessary.
o Rsa, Rsb : Reference frequency divider ratio select bit.
It RSa, RSb : X'tal reference frequency divider ratio select bits.
DIVIDER RATIO RSa RSb
1 /256 1 1
1 /512 0 1
1 /320 x 0
x : Don't Care
(Note) When the mode is changed from test to normal, RSa changes depending on the data bit
length (18 or 19 bits, automatic discrimination). The data set in RSb in test mode are
retained.
0 OS , Tuning amplifier control bit
i011 : Tuning amp ON (Normal operation)
F 1 , : Tuning amp OFF (High impedance)
It x : Don't Care
17 2003-04-02
TOSHIBA TA1303BFN
" Bus communications control
The TA1303BFN conforms to standard " bus format.
The " bus mode enables two-way bus communications with the WRITE mode, which receives data,
and READ mode, which status data.
WRITE and READ modes are set using the last bit (R/W bit) of the address byte.
If the last address bit is set to ' ol ' WRITE mode is set ; if set to , 1 J ' READ mode is set.
Addresses can be set using the hardware bits. 4 programmable addresses can be programmed.
With this setting, multiple frequency synthesizers can be used in the same IZC bus line.
The address for the hardware bit setting can be selected by applying voltage to the address setting
pin (ADR : Pin 3).
An address is selected according to the set bits.
When the correct address byte is received, during acknowledgment, serial data (SDA) line is "Low".
If WRITE mode is set at this time, when the data byte is programmed, the serial data (SDA) line is
"Low" during the next acknowledgment. Please refer the description (Fig2. " bus data timing
chart) on page 11.
(1)WRITE mode (setting command)
When WRITE mode is segment, byte 1 segment the address data ; bytes 2 and 3 segment the
frequency data ; byte 4 segment the divider ratio setting and function setting data ; and byte 5
segment the output port data.
Data are latched and transferred at the end of, byte 3, byte 4, and byte 5.
Bytes 2 and 3 are latched and transferred is done with a two byte set (byte 2 + byte 3).
Once a correct address is received and acknowledged, the data type is determined according to
[ol mi ll set in the first bit of the next byte. That is, if the first bit is , ol ' the data are
frequency data ; if f 1 , ' function setting or output port data.
Until the IZC bus STOP CONDITION is detected, the additional data can be input without
transmitting the address again. (EX : Frequency sweep is possible with additional frequency
data.)
If data transmission is aborted, data programmed before the abort are valid.
Byte 1 can set the hardware bit with address data.
The hardware bit is set with voltage applied to the address setting pin (ADR : Pin 3).
18 2003-04-02
TOSHIBA TA1303BFN
Bytes 2 and 3 are stored in the 15-bit shift register with counter data for the frequency setting,
and control the 15-bit programmable counter ratio.
The Lock frequency can be calculated in the following formula :
fosc = fr x 4 x N
fosc : Program frequency
fr : Phase comparator reference frequency (Step frequency)
N : Counter total ratio
fr is calculated using the crystal oscillator frequency and the reference frequency divider ratio set
in byte 4 (control byte). (fr = X'tal oscillator frequency/reference frequency divider ratio)
The reference frequency divider ratio can be set to, 1/256, 1/512, and 1/320. When using a
4MHz crystal oscillator, fr = 15.625 kHz, 7.8125 kHz, and 12.5 kHz. The step frequency are 62.5
kHz, 31.25 kHz, and 50 kHz.
Byte 4 is a control byte used to set functions. Bit2 (CP) controls the output current of the
charge-pump circuit. When bit2 is set to ' ol ' the output current is set to -+60 pA , when set to
f 1 1 , $280 PA.
Bit3 (T2), bit4 (T1) and bit5 (T0) are used to set the test mode. They are used to set the charge-
pump test, phase comparator reference signal output, and counter divider 1/2 output.
Please refer the description (Table. 3) on page 21.
Bit6 (Rsa) and bit7 (Rsb) are used to set the X'tal reference frequency divider ratios.
Please refer the description (Table. 4) on page 21.
Bit8 (OS) is used to set the charge-pump drive amplifier output setting. When bit8 is set to
101 ' the output is ON (Normal use) ; when set to , 1 1 the output is OFF (High impedance).
Byte 5 is used to set and control the output port (Bands 1~4). Select [ol for OFF, and f 1 , for
ON. Please refer the description (Table. 5) on page 21.
When band switch data is F 1 , either Band 1 or Band 2, VHF mode.
When band switch data is 101] both Band 1 and Band 2, UHF mode.
Two output ports can be operation turned on, bat be sure to keep the total output current
under 50 mA.
(2) READ mode (status request)
When READ mode is set, power-on reset operation status, phase comparator lock detector output
status, and 5-Ievel A/D converter pin input voltage status are output to the master device.
Bit1 (POR) indicates the power-on reset operation status. When the power supply of VCC2 stops,
bit1 is set to , 1 , . The conditions for reset to f ol voltage supplied to VCC2 is 3 V or higher,
transmission is requested in READ mode, and the status is output. (When VCC2 is turned on, bit1
is also set to ' 1 l)
Bit2 (FL) indicates the phase comparator lock status. When locked, ' 1 l is output ; when
unlocked, lol is output.
Bits 6, 7, and 8 (A2, A1, A0) indicate the 5-level A/D converter status. The voltage applied to
the A/D converter input pin (pin 29) is output through a 5-Ievel resolution.
Please refer the description (Table. 6) on page 21.
(EX : The AFT output voltage data can be given to the master device.)
19 2003-04-02
TOSHIBA
DATA FORMAT
a) WRITE MODE
TA1303BFN
BYTE MSB LSB
1 Address Byte 1 1 0 0 0 MA1 MAO R/W=0 ACK
2 Divider Byte0) 0 N14 N13 N12 N11 N10 N9 N8 ACK
3 Divider Byte© N7 N6 N5 N4 N3 N2 N1 N0 ACK©
4 Control Byte 1 CP T2 T1 T0 RSa RSb os ACKCD
5 Band SW Byte x x x x B4 B3 B2 B1 ACKCD
x : DON'T Care
ACK : Acknowledged
© : Latch and transfer timing
b) READ MODE
BYTE MSB LSB
1 Address Byte 1 1 0 0 O MA1 MAO R/W=1 ACK
2 Status Byte POR FL 1 1 1 A2 A1 A0 -
DATE SPECIFICATIONS
o MA1, MAO : Programmable hardware address bits
ADDRESS PIN APPLIED VOLTAGE MA1 MAO
0~o.1 x VCC2 0 0
OPEN or 0.2 x Vccz~0.3 x VCC2 0 1
0.4 x Vccr-0.6 x VCC2 1 0
0.9 x Vcc2~VCC2 1 1
o N14--NO : Programmable counter data
It CP : Charge-pump output current setting
101 : iGOyA(Typ.)
1 1 , : i280/[1A (Typ.)
x : DON'T Care
ACK : Acknowledged
TOSHIBA TA1303BFN
Table. 3
0 T2, T1, T0 : Test mode setting
CHARACTERISTIC T2 T1 T0 REMARKS
Normal Operation 0 0 x -
OFF 0 1 x Charge-pump is "OFF" (Check output : NF)
Charge-Pump Sink 1 1 0 Only charge-pump Sink current is "ON" (Check output : NF)
Source 1 1 1 Only charge-pump Source current is "ON" (Check output : NF)
Reference Signal . .
Output 1 0 0 Reference signal output . ADC
1/2 Counter Divider 1 0 1 1/2 counter divider output : ADC
Output
x : DON'T Care
(Note) When testing the counter divider output, programmable counter data input is necessary.
Table. 4
o RSa, RSb : X'tal reference frequency divider ratio select bits.
RSa RSb DIVIDER RATIO
1 1 1/256
0 1 1/512
x 0 1/320
x .' DON'T Care
It OS : Tuning amplifier control setting.
lioj : Tuning amplifier ON (Normal operation)
' 1 , : Tuning amplifier OFF (High impedance)
Table. 5
o B4~B1 : BAND switch data
lioi : OFF When band drive data isf ll either Band1 or Band2, VHF mode.
' 1 J : ON When band drive data is , ol both Band1 and Band2, UHF mode.
It POR : Power-on reset flag
'O) : Normal operation
f 1 , : Reset operation
0 FL .' Lock detect flag
[ol : Unlocked
' 1 , : Locked
0 A2, A1, A0 : 5-level A/D converter status.
Table. 6
ADC PIN APPLIED VOLTAGE A2 A1 A0
0.60 x VCC2~VCC2
0.45 X Vcc2~0.50 X VCC2
0.30 x Vcc2-0.45 x VCC2
0.15 x Vcc2--0.30 x VCC2
0--0.15 xvcc2
OO—‘AO
O—‘O—IO
(*) Accuracy is i 0.03 x VCC2
21 2003-04-02
TOSHIBA TA1303BFN
" BUS CONTROL SUMMARY
The bus control format for TA1303BFN conforms to the Philips " bus control format.
Data transmission format tt
I S l Slave address l 0 l A I %'ta l A l Data l A l P l
I '' I
7-bit I 8-bit 8-bit
MSB MSB MSB
S : Start condition
P .' Stop condition
A : Acknowledge
(1) Start/stop conditions (2) Bit transfer
Cl, l-- n I I I I
Serial data i I . . Ll l " Serial data / E i X i E \
I I I I t I t I
I I I I I I I I
I I l I t I t t
-tl-i-, I C: t-tl-r,'- I I l I l
Serial clock I I I I Serial clock L/tci/ei-
I L1d L l I / I I I
Start condition Stop condition Serial data S'
must not be Serial data may be changed.
changed.
(3) Acknowledge (4) Slave addresses
Serial data from I- -II -
master E I :x , Highimpedance A6 A5 A4 A3 A2 A1 A0 R/W
I I 1 1 0 O 0 * * 0
a-'- . .
Serial data from High impedance N /
Purchase of TOSHIBA IZC components conveys a
license under the Philips " Patent Tights to use
Serial clock from N Cl "iv/fl/fl these components in an " system, provided that
master 2
the system conforms to the I C Standard
Specification as defined by Philips.
I--- ________
22 2003-04-02
TOSHIBA
TEST CIRCUIT 1
DC characteristics
Band vc (Vccg) VCC2 (5V)
Q ADC/Lock NF
. NC. 'i,) l N.C. i; N.C. NC. NC NC.
29 623 62 26 25 24 23
TA1303BFN
'li2cilsici)2ici?ici2iic,i/o'fi;
Divider
1/a-
Phase l
D Comparator Programable
3]: BUS-SW
SCL SDA ADR © lCC1
/CL IDA IEN
VCC1 (5 V)
TEST CIRCUIT 2
X'tal external input measurement
Input level measurement point
, 1 nF
X'talin @ . I-tia) External signal input
(Signal Generator)
L (82 tsH)
VCC? (ii) 5V
Divider
Data B1 E/V Band
Ii: SW
InterFace B2
VHF UHF
Band Driver MIX MIX
[i, "I Reg l-
1 2 'il t f Q9 if) f 13 14 15
cl c: c: 8 8 8
g g 8 1 2i 2; CD
F '- F _ N N
TOSHIBA
TEST CIRCUIT 3
AC characteristics
3.3 k0
TA1303BFN
1.2 k0
VBT (33 V) C N. 0.1 pF
47 k0, 2200 pF
VCC2 (5 V) s,, g 'k
lSV262 150 pF
Band N N K---"-,
VCC ADC/Lock IF OUT ti 'k' g ti
"1.. > > m.. "H-_-tttct
O ‘2 "d 0 0.5 pF 47 km
1%] u. I 7 pF 5V
u. g; I w
3 .- 47k0 FY
cr, LL '"" 'f'
_iirl,i. o' ',-,,,i t,'zi) 9.
'" m N N ts u, a LL.-
t" "ri=?ig cu 1 cis.., fir r?., 3--
.- I F m
er. C. O. m
ol 2 '','Jj,, sir''''''');";;-''''''''),
30 29 ® (ih J, 65 21 20 18 g 69
IADC Lock _ h H
I I I I
UHF VHF
Divider - OSC OSC
1/4 --<2 ,
Phase I
Comparator Programable
Divider
Data BI s/T, Band
InterFace iBz
VHF UHF
Band Driver MIX MIX
[1K 11': 17K "I Reg ,
0) C2) 3 (4) to C6) 7 Q9 15
0:) F.4 cr
crP o. o
O O O O O O O
SCL SDR ADR Band1 Band? Band3 Band4 O BUS-SW VHF UHF
/CL /DA /EN vcc1(5v) RF-IN RF-IN
LINE TURN NUMBER Band1/Band2=VHF-L or VHF-H
DIAMETER DIAMETER OF TURNS Band3/Band4=UHF or FMT
L1 0.3mm 2.0mm 7.5T
L2 0.3mm 2.0mm 2.5T
L3 0.3mm 2.5mm 2.5T
L4 : os trFi i 5%
TOSHIBA TA1303BFN
[REFERENCE DATA]
X'tal External Input Level
If it uses not only "TEST CIRCUIT 2" but "Fig.6", please refers to "Graph 1".
4MHz input level measurement point
I-Coy 4MHz in
1 nF (Signal Generator)
Fig.6 X'tal External Input Reference Application
Graph 1 Operating range of "Fig.6"
- . - . : 4.5 V
Pcl 900 : 5.0V
>c'x 800 - : 5.5V
Te 400
g 200 perating range
0 50 100
Temperature (°C)
25 2003-04-02
TOSHIBA TA1303BFN
HANDLING PRECAUTIONS
l. The device should not be inserted into or removed from the test jig while the voltage is being
applied: otherwise the device may be degraded or break down.
Do not abruptly increase or decrease the power supply to the device either. (See Figure 1.)
Overshoot or chattering of the power supply may cause the IC to be degraded.
To avoid this filters should be incorporated on the power supply line.
38V (6V) -...r-'"_
Power Supply Voltage
Figure 1
2. The peripheral circuits described in this datasheet are given only as system examples for
evaluating the device's performance. Toshiba intend neither to recommend the configuration or
related values of the peripheral circuits nor to manufacture such application systems in large
quantities.
Please note that high-frequency characteristics of the device may vary depending on the external
components, mounting method and other factors relating to the application design. Therefore,
the characteristics of application circuits must be evaluated at the responsibility of the users
incorporating the device into their design.
Toshiba only guarantee the quality and characteristics of the device as described in this datasheet
and do not assume any responsibility for the customers application design.
3. In order to better understand the quality and reliability of Toshiba semiconductor products and
to incorporate them into design in an appropriate manner, please refer to the latest
Semiconductor Reliability Handbook (Integrated Circuits) published by Toshiba Semiconductor
Company.
The handbook can also be viewed online at
http://docsemicon.toshiba.co.jp/noseek/us/sinrai/sinraifm.htm.
26 2003-04-02
TOSHIBA TA1303BFN
PACKAGE DIMENSIONS
SSOP30-P-300-0.65 Unit : mm
RflliRillilflRfllWlfl fl 'is"
5.6i0.2
7 GiO 3
(D .. ,
1HHH' 'H 1iljljllljl:ll.,...,,
0.3TYP o.22io.1 A
=c-a-h
1 0.2MAX
l” 9.7k0.2
g l l 0.45:0.2
Weight : 0.17g (Typ.)
27 2003-04-02
TOSHIBA TA1303BFN
RESTRICTIONS ON PRODUCT USE
000707EBA
OTOSHIBA is continually working to improve the quality and reliability of its products.
Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent
electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe
design for the entire system, and to avoid situations in which a malfunction or failure of such
TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please
keep in mind the precautions and conditions set forth in the "Handling Guide for
Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..
OThe TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor
warranted for usage in equipment that requires extraordinarily high quality and/or reliability or
a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended
Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA
products listed in this document shall be made at the customer's own risk.
0 The products described in this document are subject to the foreign exchange and foreign trade
OThe information contained herein is presented only as a guide for the applications of our
products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of
intellectual property or other rights of the third parties which may result from its use. No
license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
0 The information contained herein is subject to change without notice.
28 2003-04-02
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