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TA1226
Y LUMINANCE TRANSIENT IMPROVER IC
TOSHIBA TA1226N
TENTATIVE TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC
TA1226N
Y LUMINANCE TRANSIENT IMPROVER IC
TA1226N integrates Y luminance transient improver
circuits (black stretch, DC transfer ratio compensation,
super real transient, noise reduction) in a 20-pin shrink
DIP. TA1226N functions are controlled via IZC bus.
FEATURES
It Black stretch circuit
a DC transfer ratio compensation circuit
a Super real transient circuit (SRT) SDlP20-P-300-1.78
0 Noise reduction Weight : 1.02g (Typ.)
o 1-bit DAC output
0 Velocity modulation output
961001 EBA1
OTOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid
situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or
damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified
operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions
and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
OThe products described in this document are subject to foreign exchange and foreign trade control laws.
OThe information contained herein is presented only as a guide for the applications of our products. No responsibility
is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any intellectual
property or other rights of TOSHIBA CORPORATION or others.
OThe information contained herein is subject to change without notice.
1997-06-20 1/15
TOSHIBA
BLOCK DIAGRAM
"P-u/l.
Sand Castle Pulse
1Vp-p ard,-
TA1226N
2 3 19 10
Y input Black peak AAA S.C.P
ABL clamp detect "V VM amp decoder
1 .— 7
DC transfer
Pedestal Black stretch . ratio
. _ - y correction
smoothing compensation compensation
I pulse injection
6 GND CO-g
Cb, Black area Black area ASS I'
'Q) output detect I SRT ttrt w
- + 18 L _ J i?
" uminance ' -
f" transient Dynamic NR DL Itti 0,
Q1 Add control - (Noise Reduction) - APACON Irit Cy
12c b A t ti filt VCC 16
= us u oma 1c I er +
'l 'sl.?, decoder DAC output adjustment - OSC J I
l l l I
12 119T) :14)
SDA SCL 1
TERMINAL CONNECTION DIAGRAM
a (9) (9 O (ii) (is) ® Cs) (3 (D
Black VM Y Black VCC Automatic OSC Digital SDA SCL
area output area Our ut fil ter GND
output hold p adjustment
. T A 1 2 2 6 N
Black Black Black DC transfer
F Y stretch peak detect Analog .ABL ratio DACI DAC2 SCP
Input point hold level GND input compensation output output input
(.1.,JL2,J0,J0,Jti,J(.t.9L7.Jo,Je,J(1.9
1997-06-20 2/15
TOSHIBA
TERMINAL FUNCTION
TA1226N
PIN NAME
FUNCTION
INTERFACE
I/OSIGNAL
Y input
Luminance signal input pin. Input
luminance signal after
eliminating chrome signal via
capacitor. After luminance signal
is input to this pin, Y signal is
clamped to 4.5V pedestal level.
Standard input level is ll/p-p
(including sync signal).
iOO/IA
4.5V (Typical)
stretch
Used to set black stretch start
point using external resistance
(DC level).
Note that setting this pin to 1.5V
or below enters test mode.
Input level
4d) 4.5 5.0
Pin 2 voltage
5.5 (V)
3.5~7.0V
Black peak
Used to connect filter which
detects highest black level of
luminance signal. Voltage on this
pin determines black stretch gain.
3.8--5.2V
detect level
Used to control frequency (area)
of black level to be detected. Set
area to be detected using
external capacitance and internal
resistance. In application circuit
example, setting is made so that
frequency of black level to be
detected is 100kHz or less.
17t,,vw'''''''""L
4.5V (Typical)
1997-06-20 3/15
TOSHIBA
TA1226N
KILL“ PIN NAME FUNCTION INTERFACE I/O SIGNAL
Analog . .
5 GND GND for analog clrcult - -
Used to apply control current for
ABL and black level
compensation. 1:
li',; Ci)-
6 ABL input _'2 lkQ i -
'if/ii" x v
e, 0 10 20 30
Output current (PA)
Used to compensate DC transfer
ratio. Smaller Rx, larger
compensation amount. Injection
of R2 varies start point of DC
transfer ratio compensation. 7: Y o When pin 7 is
DC transfer ratio TDC (%) wt, open :
=5kQ/ 5kQ+Rx x30+100 BAAA _
DC transfer ( ) 17st,a,,,-,so,w'''1
7 ratio R1 sen -
compensatl - + Rx 4SV (Typical)
on Cx -
§ + Rx small/po Rz)
ii' g I Rx large (no Rz)
irii; ....... ...ci
m a .......
E .-" ..
8 R2 small APL(%)
DAC1 Open collector switches. DC
8 output Maximum, input current value : 1E
. . . . 80_ VCC or
9 DAC2 2mA (minimum, drive resistance 9 5009 GND
output value : 6kf2) I
SCP (Sand Castle Pulse) input pin. 6.9V
Typical thresholds for CP (Clamp 7: (Typical)
1O SCP input Pulse), HP (Horizontal Pulse), and ' rlu
VP (Vertical Pulse) are 6.9V, 3.1V, 30m c: (Typical)
. II g 1.3V
and 1.3V respectively. M m (Typical)
1997-06-20 4/15
TOSHIBA TA1226N
KILL“ PIN NAME FUNCTION INTERFACE l/O SIGNGAL
IZC bus SCL pin. Because surge 5V
breakdown voltage is low, take
11 SCL .
external countermeasure if
necessary. OV
" bus SDA pin. Because surge
breakdown voltage is low, take 5V
12 SDA external countermeasure if . 0.4V
necessary. When Vcc voltage IS / .
3.2V or more, power-on reset is ACK bit 0v
applied.
Digital . . . .
13 GND Logic circuit GND pin. - -
11.7V(Typical)
Used to connect filter for 420mV
obtaining 4MHz. Using 4-MHz . p-p
14 OSC . . . . (Typical)
oscillation, automatically adjusts
. . . (at 4MHz)
built-in delay line. Illlilllllllllll
Used to connect filter which
automatically adjusts delay time
Automatic f. IC built-in dtlay line.
15 filter Directly connecting external pull- Iki) 10m DC
adjustment up resistor Increases peak 5.9V (Typical)
frequency. l)
Pulling down decreases peak _
frequency.
1997-06-20 5/15
TOSHIBA
TA1226N
PIN NAMA
FUNCTION
INTERFACE
I/O SIGNAL
Vcc pin.
Connect 12V (typical).
Y output
Output pin for luminance signal
on which Y is processed.
Max. output current value : 2mA
(min. drive resistance value :
7.8V (Typical)
Black area
Used to connect filter which
detects black area of input
luminance signal.
Voltage changes depending on
black area of input signal pin.
Black area detection of bus
control can vary threshold of
black area detect.
0.2--6.7V
Y output
for VM
Y output pin for VM (Velocity
Modulation). Maximum output
current value : 2mA (minimum
drive resistance : 2.4k0.
3.75V (Typical)
Black area
output
Output pin for black area
detected by black area hold
circuit. Outputs DC current
depending on input black area.
Larger black area, higher pin
voltage. Control is possible using
output of this pin, depending on
input signal black area.
0.5-6.81/
1997-06-20 6/15
TOSHIBA
TA1226N
BUS CONTROL MAP
Y luminance transient improver IC
Slave address : 10111010 (BA(h))
SUB 7 6 5 4 3 2 1 o Jfttft,fihl,
ADDRESS MSB LSD MSB LSD
00 APAC Sharpness 0100 i 0000
01 Black area detect SRT level * YNR y correction 0000 E 1011
. Black Black E
02 DAC1 DAC2 VM gain y curve compensa SRT 0011 l 0011
stretch . I
-tion l
Frequency characteristics Luminance transient i
03 TEST compensation (RS) tracking (RTC) 1100 l 0100
(Note) * : Ignore data.
1997-06-20 7/15
TOSHIBA TA1226N
PRESET
FUNCTION CONTROL DATA CONTROL CONTENTS VALUE
APACON 0 .' ON Controls ON/OFF of DL (Delay Line) APACON in ON
1 : OFF micro signal amplitude (approx. 20m1/p-p) range. (0)
Center
Sharpness 7F ' MAX Controls both DL APACON and SRT. value
00 : MIN
Black area ll : 40 IRE IO : so IRE 5,2";m'23::1111I:3:'assabszitcigiaCSSJm in w IRE
detect OI : 20 IRE 00 : IO IRE p p (00)
20 output).
SRT level 11 : 28 IRE 10 : 14 IRE Controls signal amplitude at which SRT becomes 28 IRE
01 : 10 IRE 00 : 7 IRE valid. (00)
0 I ON OFF
YNR 1 : OFF Controls YNR ON/OFF. (1)
correction 11 : OFF 10 : 90 IRE Controls start point of y correction (broken line OFF
y 01 : 80 IRE oo : 70 IRE at one point) (11)
DAC1 0 : OPEN Controls 1-bit DAC (open collector transistor OPEN
1 : ON output) (0)
DAC2 0 : OPEN Controls 1-bit DAC (open collector transistor OPEN
1 : ON output) (0)
. 11 : OdB 10: -3dB . . OdB
VM gain 01 : -6dB 00 : OFF Controls gain between Y input and VM output. (00)
0 : ON OFF
Black stretch 1 : OFF Controls black stretch ON/OFF. (0)
c rve 0 -2.4dB Controls curve of y correction -2.4dB
y u 1 -1.6dB (broken line at one point) (0)
Controls automatic black level compensation
Black 0 : ON (may 7.51R1E). (_When black stretch gain IS ON
com ensation 1 . OFF maximum, if highest black level floats above (0)
p . pedestal level, DC-shifts maximum of 7.51RE
picture duration up to pedestal level.)
0 .' OFF ON
SRT 1 : ON Controls SRT ON/OFF. (1)
11 : Test3 10 : RTC . . . Test3
TEST 01 : SHR 00 : RS Controls pm 20 output signal In test mode. (11)
frequency 111 : MAX(+6dB) . OdB
characteristics 000 : MIN (OdB) Controls gain of DL APACON at 8MHz peak. (000)
compensation
Luminance Controls compensation ratio of SRT and DL Center
. 111 : MAX
transient OOO: MIN APACON. value
tracking ' (Controls SRT level to be added to DL APACON.) (100)
1997-06-20 8/15
TOSHIBA TA1226N
OVERVIEW OF " BUS CONTROL FORMAT
The bus control format for TA1226N conforms to the Philips standard.
Data transfer format
I S I Slaveaddress I 0 I A I Subaddress I A I Data 3 I A I P I
I 7-bit I 8-bit I 8-bit
M53 MSB MSB
s : Start condition
P : End condition
A : Acknowledgment
(1) Start and end conditions (2) Bit transfer
L--", r -n I l l I
SDA I t:,' l S I] I SDA /i IXI I\
I l I I I i 'I I
, l , l
SCL I S I\ C Cl I I P I SCL I/ \I I/ \I
L__J - - - -.1 l l I
Start condition End condition I / I I I
SDA must not be changed.
SDA may be changed.
(3) Acknowledgment (4) Slave addresses
mm master) l Highimpedance A6 A5 A4 A3 A2 A1 A0 R/W
SDA from slave I I High impedance 1_C"
SCL from master I I N /i-
I.- __l
Purchase of TOSHIBA pc components conveys a license under the Philips Pc Patent Rights
to use these components in an IZC system, provided that the system conforms to the "
Standard Specification as defined by Philips.
1997-06-20 9/15
TOSHIBA TA1226N
MAXIMUM RATINGS (Ta = 25 i YC)
CHARACTERISTIC SYMBOL RATING UNIT
Supply Voltage Vccmax 14 V
Input Pin Signal Voltage einmaX 12 Vp-p
Power Dissipation PD (Note 1) 1400 mW
Power Dissipation Decrease Ratio 1/Qjp -11.2 mW/°C
Operating Temperature Top, -20--65 ''C
Storage Temperature Tstg - 55--150 °C
(Note 1) See figure below.
(Note 2) Since the device is susceptible to surge voltage, take great care when handling.
-22.2mW/''C
Power dissipation Po (mV)
0 25 65 150
Ambient temperature Ta CC)
Figure Temperature decrease curve of power dissipation
1997-06-20 10/15
TOSHIBA TA1226N
RECOMMENDED SUPPLY VOLTAGE
m‘ PIN NAME MIN TYP MAX UNIT
16 Vcc 11.0 12.0 13.0 v
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, VCC =12V, Ta = 25 i 3°C)
DC characteristics
Supply voltage
CHARACTERISTIC SYMBOL MIN TYP MAX UNIT
Supply Voltage ICC 26.0 35.5 48.0 mA
Pin voltage
2f PIN NAME SYMBOL MIN TYP MAX UNIT REMARKS
1 Y input VI 4.20 4.50 4.80 . .
4 Black detect level v4 4.20 4.50 4.80 No input, SCP input
6 ABL input V6 2.00 2.50 2.90
7 DC transfer ratio V? 4.20 4.50 4.80 No input, Pin open, SCP input
compensation V
8 DAC1 output V8 11.5 11.9 12.0
9 DAC2 output V9 11.5 11.9 12.0 . .
17 Y output v17 7.45 7.80 8.15 No input, SCP input
19 VM Y output v19 3.30 3.75 4.20
AC characteristics (Unless otherwise specified, Vcc=12V, Ta =25 i3°C)
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP MAX UNIT
Y Input Pedestal Clamp Voltage V1 - (Note 1) 4.2 4.5 4.8 V
Pin 7 Output Impedance ZOUT7 - (Note 2) 4.3 5.5 6.7 kn
DC Transfer Ratio Compensation
. A - N .2 . 4 .4 -
Amp Gain V7 ( ote 3) 0 5 0 3 0 5
Dynamic ABL Maximum
. . . - N 4 .4 . V A
Sensitivity GV6 ( ote ) 3 5 6 6 m /p
BI k h A Ma _
'ill) Stretc mp xlmum GVBE - (Note 5) 1.30 1.40 1.50 -
Y Input Dynamic Range DR1 - (Note 6) 0.9 1.0 1.2 V
Lumlpance Transient Control Fp - (Note 7) 3.6 4 4.4 MHz
Peaking Frequency
- _ G 9 12 15
Luminance Transient Control SMAX - (Note 8) dB
Range GSMIN -12 -9 -6
Luminance Transient Control
. . - N 4 . 7 B
Center Characteristics GSCT ( ate 9) 5 5 d
. FPMAX 4.3 5.9 7.8
- Note 10 MH
Peaking Frequency Change Rang FPMIN ( ) 1.8 2.7 3.6 z
1997-06-20 11/15
TOSHIBA TA1226N
CHARACTERISTIC SYMBOL CIR- TEST CONDITION MIN TYP MAX UNIT
. SRTMAX 20 40 60
ie,':,,,'?? Transient 2T Pulse SRTCEN - (Note 11) 110 130 150 ns
p SRTMIN 170 190 210
Noise Reduce GNR - (Note 12) -15 -7 -1.0 dB
. VSTI 250 310 370
BI k h P - Note 13 mV
ac Stretc oint VST2 ( ) 340 430 520
Black Peak Detect On Voltage VBPON - (Note 14) 1.2 1.5 1.8 V
Black Detect Delay Time TEE; - (Note 15) O 50 170 ns
GUM00 - -4o -20
G - 7 - 6 - 5
VM Output Y Gain I/MOI - (Note 16) dB
GVM10 -4 -3 -2
GVM11 -1 0 1
vyoo 530 575 620
y Correction Point Vy01 - (Note 17) 600 645 690 mV
vym 620 665 710
G -3.2 -2.4 - 1.6
y Correction Curve 6:? - (Note 18) -2.4 - 1.6 -0.8 dB
Black Peak Detect Level VBp - (Note 19) 5 20 35 mV
DL APACON Limiter Range VAL - (Note 20) 20 45 70 mV
V3500 50 80 110
V3501 130 160 190
- Note 21 mV
Black Area Detected Level V3510 ( ) 200 230 260
VBS11 280 310 340
Black Area Hold Pin Voltage AVBSOO
. BS01 - (Note 22) -260 o 260 mV
Black Area Output Pin Voltage AVBS10
Difference AV3511
Black Area Output Pin Voltage AVZOOO
Change With Respect To Black szom - (Note 23) 410 500 610 mV
Area Hold Pin Voltage Change 2010
AV2011
Frequency fharacteristics FTMAX - (Note 24) 5 6 7 dB
Compensation FTMIN - 1.5 O - 1.5
Clamp Voltage On Voltage VCLON - (Note 25) 6.7 6.9 7.1 V
Horizontal Blanking On Voltage VHP - - 2.9 3.1 3.3 V
Vertical Blanking On Voltage VVp - - 1.1 1.3 1.5 V
OSC Oscillation Frequency FOSC - (Note 26) 3.9 4.0 4.1 MHz
1997-06-20 12/15
TEST CIRCUIT
217/01
TP19 TPZO
:idtit
Jrfuro
grf00t
SDA SCL
AMM/u‘g
1000pF
£77117
Black \IM Y
area output
output
Y stretch
input pomt
Black Y
:23: output
Black Black
peak detect
hold level
Automatic
filter
adjustment
TA1226N
Anatog
14 13 12 11
0 Dlgital
tra nsfer
com pensation output
DACZ SCP
output
DA SCL
”011‘:
ttl 010172
(5115 0st
U’IL'S
1$i1®®11
TC74HC123P/AP
4 ' 6 7
Q Q) ®
1000pF
UV 011's
0115 0115
NPN Tr‘ :
PNP Tr.
Mylar capacitor
23C1815Y
ZSA‘IO‘ISY
TOSHIBA
TA1226N
TOSHIBA TA1226N
APPLICATION CIRCUIT
Peak Frequency
* 39pF : 4.0MHz
33 F : 4.2MH
p Z Vcc
i u. _
u. rt, g 2 N
E cl a E cl g F ' N
F g' g .- g) o 'R t t >
'- '- LL '- c> ._ ._ . arc.
d, F o I m
S' C) a; m
20 19 18 17 16 15 14 13 12 11
Black Vl¥l l 2'3: Y VCC Au)ri1,atic OSC Digital SDA SCL
area ou u
output p hold output adjustment GND
i) TA1226N
1V - Black Black Black DC transfer
p p ' Y stretch peak detect Analog ABL ratio DAC1 DAC2 SCP
input point hold level GND input compensation output output input
3 4 5 6 7
sfi cl l;
10/1F q N' t, g c g
_ i E F o u. 'f,'
Yin f) Ss N_ 8 :5 u,
Ps td E NJ: on o
(O : Mylarcapacitor
1997-06-20 14/15
TOSHIBA TA1226N
OUTLINE DRAWING
SDlP20-P-300-1.78 Unit : mm
i-lr-nf-lr-lf-nr""")?""-??-""))-
>> ii.
|_lL_lL_JL_ll_J[_lLl|_l|_l|_l
0—1 5°
, 19.1 MAX "
18.6i0.2
c5 tr?
n tl El
_v_ mt', to
In. rei
1.299TYP - n _ " th46e0.1 th1 8
Weight : 1.029 (Typ.)
1997-06-20 15/15
www.ic-phoenix.com
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