T6668 ,-0.3 to +6.0V; V(in/out): -0.3 to +0.3V; CMOS LSI for voice recording and reproducing using the ADM systemELIE D " '3tP17iiYH1 DDELI‘ILIE Ell: .TOSB T6668_1||
TOSHIBA (UC/UP)
1. GENERAL
The T6668 is ..
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T6668
-0.3 to +6.0V; V(in/out): -0.3 to +0.3V; CMOS LSI for voice recording and reproducing using the ADM system
" l) © 90972“! UDEH‘ME su, L_JTOSB T6668-1
TOSHIBA (ucxup)
1. GENERAL
The T6668 is a single chip CMOS LSI for voice recording and reproducing using the ADM
(Adaptive Delta Modulation) system. When a dynamic RAM is used as a voice data memory and an
audio circuit including a microphone, speaker, amplifier, etc. is externally connected, tl voice
recording / reproducing system can be composed.
2. FEATURES
D A single chip LSI for voice recording / reproducing.
Cl D - RAM (Dynamic RAM) used as a voice data memory with the capacity up to 4pcs. of 64Kbit or
4pcs. of256Kbit.
Built - in counter to refresh D - RAMs.
Easy connection with CPU. Control by 9 kinds ofeommands.
Capable of recording/ reproducing ofmax. 16 phrases.
Selectable 4 kinds of bit rates (32k, 16k, 11k, 8kbps).
Recording tone of each phrase is variable (MAX. 128 sec. at 256KD - RAMX 4, bit rate 8kbps).
Built in microphone amplifier for sound recording and band path iiltcr for sound reproducing.
Built in 10 bit D - A converter, voltage follower output.
Built in oscillation circuit for ceramic resonator.
Single 5V power supply ................... Low power consumption by CMOS structure.
DEIDCIDDDDCID
60 pin mini flat package.
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T6668-2 '30??qu UUEH‘IHB H58 DTOSB
TOSHIBA (UC/UP)
BLOCK DIAGRAM
T6668 Block Diagram
RAS,CAS, E A0--A8 DIN,DOUT
e----.-,--.-!) MICIN
' b----- (5 MICOUT
D - RAM I IF
{J ADI
- Address counter - ADM analysis/ D/A
synthesize circuit 7 Converter -----ty DAO
voltage
follower
Stop address register -
Timing generator Band path ---h FlLlN
-» control circuit V filt
"N Index register i-' ’0 FILOUT
- Refresh counter CPU us = Status register
_ Cy V (i C- C.) 43
Von Vss1.Vssz EOS, M1, M2 Do~D 7tTi, TW, ih7rt CPUM,256K XIN XOUT
?Eli9 003999“ 399 CITOSB
ELIE I) © 909 T6668-3
TOSHIBA (UC/UP)
3.2 Block Diagram Description
(1) Address Counter
The 20 bit counter to show addresses of the external D - RAMs. Values can be set or read out by
commands under CPU control. (N ote 1)
(2) Stop Address Register
The 20 bit register to show addresses to stop recording I reproducing. Values can be set by
commands, but values can ant read out by commands under CPU control.
(3) Index Register
The register to show addresses of the index area on D - RAMs in the label index mode (refer to
6.5). User cannot directly operate this register.
(4) Refresh Counter
The 8 bitcounter to refresh the external D - RAMs.
(6) Status Register
The 8 bit register to show the status of T6668. The status outputs by setting ES to L level.
(6) CPU W
The interface circuit for the external microprocessor, etc. This circuit has also the chattering
preventing circuit in the manual control. (Note I)
This chattering preventing circuit acts on D4 and D5 terminals (start and stop inputs), and
chattering time is approx. 16 ms.
(7) Microphone Amplifier
The microphone amplifier for sound recording. Output of MICOUT terminal can be connected
directly with the ADI pins.
(8) Band - pass Filter
The band pass filter for sound reproducing. The lst stage high pass lilter and the 2nd stage low
pass filter are built in.
Note I. There are two controls available for the T6668; CPU control using a microcomputer, etc. and
the manual control using SW, etc.
T6668-4 Ial-IE D CI 90972'49 DUBLI9'45 225 DTOSB
TOSHIBA (UC/UP)
3.3 Example of Voice Recording / Reproducing LSI System Configuration
3.3.1 CPU Control
MIC AMP SP
K-g. 0.01 c, g l
lp ly 27 KT
+ + - l
MICINc1 C2MICOUTADI DAO HUN FILOUT
D0--D7 DOUT
DIN -'»
- A0'A8
= RD - DIN _ 64 K or 256 K
.. Wm T6668 Dom .._... D-RAM
a ---_ - ih7rtrtt" _ (MAX 4 PCS)
v L 'Note 2 aim RAMI RAM4
DD CPUM CAS1 , l
'Notel VDD - 256 K
or - MI A7iT
VSSI - M2 ire
XIN XOUT Vref Csref
655 k Hz
--.- == 220.1 (d
1100 pF x 2
. Note 1 , N ate 2 l For connections of256K , M1 M2 and CA§1~E3A§4, refer to 5.10 Connection
to D .. RAMs.
El MT?iiltln DUEH‘IHE lulu]: CJTOSEI
T6668-5
TOSHIBA (UC/UP) EHE 1)
3.3.2 Manual Control
MIC AMP SP
i 0.01 C.., l
y: 1 (d 1,t 27 K“
VDD + l
MICIN MICOUT DAO FILOUT
Phrase CI c2 ADI FILIN
selection -fu<4 DO~03 A0--A8
J? I Dom .-
bit rate "--1tso.?,c + D... _ D
" D7 Dour - RAM
R di gi' T6668 _ WRITE _ (MAX 4 PCS)
ecor mg I s. w
Reproducing'_o WR XNote 2 CAS RAS RAMI RAM4
Speak/ No -eiso-- CE -..-. r
sound CA_S1
*Note1 VDD ---256 K .
or CAS4
vss, t M1, M2 A7T
' CPUM WI?
XIN XOUT 7iti. Vref Csref
655 k Hz
_ D i + L--,.
== .e= r-r-c0.1 [1
100 pF M 2 - 1 ,1 I
Notel , Note2 : For connections of 256 k, M1 M2 and tWt-tWR, refer to 5.10 Connection to D -
IHIIIIIII
T6668-6 III ntpr?iiAn OUE'HLI? 0T6 DTOSB
TOSHIBA (UC/UP) bHE I)
4. PIN DESCRIPTION
4.1 Pin Assignments
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44 d3 42 dil 40 39 38 37 36 35 M 33 32 31
‘RTS th
DIN DI
Dow Do
A0 CPUM
A, 7itT
N. C N. C
VDD TOP VIEW V00
A2 ADI
At DAO
A4 FILIN
As FILOUT
At TSa
As MICIN
I3 14 15
MICOUT
y.f NC : NON - CONNECTION
EHE I) E3 9097299 UUEH9HB T3” EJTOSB
TOSHIBA (UC/UP)
Pin Description
T6668-7
Structure
Pin name Pin no. Manual control CPU control Functional explanation
Pull-up Pull- Pull - up Pull -
ll o down l/O down
CASI 1 Out - Out - Column address strobe output Used from t73T to that
CAS2 2 required corresponding to the number of D - RAMs.
CAS3 4
CAS4 5
EXT 6 Out - Out - Output pins for test circuit.
MI 7 In None In None Input pins for programming of the number of D - RAMs.
1 pcs 0 0
2 pcs 0 1
3 p (s 1 0 0= L level
4 pcs 1 1 1 = H level
V551 9 Power - Power - Power supply pin to be connected to minus. Vsst is for
VSS2 10 Supply Supply digital circuit and Vsst is for analog one.
Csref 11 Ito - 1/0 - Ptrts for connecting the decoupling capacitor to the
Vref 12 reference voltage circuit of the built - in ot' - AMP.
MICOUT 13 Out - Out - Output pin of built - in MIC. AMP. Output signal must be
oscillating signal centering around 1 /2 Moo.
C2 14 In None In None Pins for connecting the coupling capacitor of built - in MIC.
C1 15 Out _ Out - AMP.
MICIN 16 In None In None Input pin for built - in MIC. AMP.
MIC must be connected to this pin through capacitor.
TSI 17 In Pull - down In Pull - down Pins for test circuit.
TS2 18 Out - Out - Must be open.
“LOW 19 Out - Out - Output and input pins of built - in band pass filter (for
FILIN 20 In None In None reproducing)
DAO 21 Out - Out - Voice Output pin of voice synthesizing circuit. Voltage
follower output. Monitor output for input voice is
obtained during recording. Output signal must be
oscillating signal centenng around 1/2 V00
T6668-8 1:111: 1) © 913972149 unaueua TNI CCIT0S3
TOSHIBA (UC/UP)
Structure
Pin name Pin no. Manual control CPU control Functionalexplanation
Pull " up Pull- Pull - up Pull -
IIO down Ito down
ADI 22 In None In None Voice input pin of voice analyzing circuit. Input signal
must be oscillating signal centering around I I2 Von and
MAX. 1.6 Vp-p.
V00 23 I 53 Power - Power - Power supply pins ... + S V
Supply Supply
TRT. 25 In Pull .. up In Pull - up Input pin for reset signal.
CPLIM 26 In None In None Mode change pin. Must be fixed to low level under
manual control mode, fixed to high level under CPU
control mode.
DO 27 In PuIl-down II o None In the CPU control mode, these are bidirectional data bus
D1 28 for commands or data between CPU and T6568. In the
D2 29 manual control mode, these are used in such a way as
D3 31 shown below.
D4 32 (I) DO ._.. D3 inputs for phrase selection. MAX. I6 phrases
D5 33 can be selected by these 4-bit codes.
D6 34 (2) D4 STARTinput
D7 35 Recording or reproducing starts by setting this pin at
hughlevel.
(3) D5 STOPinput
Recording or reproducing starts by setting this pin at
highlevel.
(4) D6, D7 inputs for bit rate selection Usable bit rates are
as follows
8 Kbps 0 0
11 Kbps o 1
16 Kbps 1 0 0: L level
32 Kbps 1 1 l = H level
CE 37 In Pull - down In None Chip enable input pin under the CPU control mode. This
pin is used for inputting voice t no voice in the MANUAL
control mode. When the pin is set at high level under
reproducing, DAO output becomes no voice condition.
The pm must be put low level during recording.
ENE D © 909?BH9 UUEHHSU EHB EJTOSB
TOSHIBA (UC/UP)
T6668-9
Structure
Pin name Pin no. Manual control CPU control Functional explanation
Pull-up Pull- Pull-up Pull-
IIO down IIO down
Wk 39 In Pull - down In None Write pulse input pin under the CPU control mode. Under
the manual control mode, this pin is for selection of
recording I reproducing. High level to this pin makes
recording mode, respectively.
T6 40 In Pull - down In None Read pulse input pin under the CPU control mode.
EOS 41 Out - Out - Output of "End of Speech."
It becomes low level after the start of recording or
reproducing, and returns to high level after the stop of
those.
Xm 42 In None In None Input and output pins of oscillator circuit. 655 km ceramic
XouT 43 Out - Out _ oscillator and capacitors are connected.
TEST 44 In Pull . down In Pull - down Pin for test circuit.
Must be open.
256K 45 In None tn None Input pin for the selection of the type of D-RAW.
It must be set at low level for 64Kbit D - RAM and high
levet lor 256Kbit D - RAM.
W? 46 Out - Out - Write pulse output pin. Connect this to WRITE pins of D -
m 47 Out - Out - Low address strobe output. Connect this to V5 input pins
of D - RAMs.
tht: 48 In PuIl-up tn Pull -up Data input pin. Connect this to data input pins of D -
Dour 49 Out - Out - Data output pin. Connect this to data input pins of D "
A0 50 Out - Out - Address output.
A1 51 Connect this to address input pins of D - RAMs. Only A8 is
A2 54 not needed when 64Kbit D - RAMs are used.
T6668-1O ELIE D © Havana unauasm sea EITOSB
TOSHIBA (UC/UP)
5. SPECIFICATION
5.1 Recording / Reproducing
System ADM System
D IA Converter 10bit voltage type
Bitrate 32K/16K/11K/8Kbps
In manual control ... 16 phrases
Max. phrase number Label Index mode in CPU control ... 16 phrases
Direct mode in CPU control "No restriction
Address counter Built in counter to refresh D - RAMs
5.2 Others
Input Microphone amplifier Two - stage, gain TYP =46 dB
Output filter Built in 2nd stage low pass +1st stage high pass filter
RAM for storing voice data 64K or 256K D - RAM, maximum 4 pcs each
Oscillation frequency 655kHz (TYP.)
bHE I) © 9097303 0030953 HES EJTOSB
TOSHIBA (UC/UP)
5.3 Operational Description
T6668-1 1
When composing a voice recording / reproducing system by the T6668, there are CPU control
using a microcomputer, ete, and the manual control using external SW, etc.
Manual Control
Selection of Phrase
Using 4 input pins of DO-IN, the sound recording / reproducing of maximum 16 phrases can be
performed. Before starting the sound recording/ reproducing, phrase No. shall be specified in 4-bit
Phrase numbers are as follows, and can be selected at random. (Fig. 5.1)
Table 5.1 Phrase no.
Pin name
Phrase No. MSB D3
D2 D1 LSB DO
No.0 0
No.1 0
No.15 1
Phrase 0001 (No.1)
Recording
Reproducing
--------T-------
Phrase 0001 (No.1)
Phrase 1000 “No.8) Q
-------------F
co Phrase 0011 (No.3)
---------_
Phrase 1000
(No.8)
Phrase 0011 (No.3)
Fig.5.1 Example of phrase selection
5.4.2 Selection of Bit Rate
o = L level
1 = H level
Recording is made in
Order of Phrase
No.1-98-o3
Reproducing in Optional
order of phrase number;
e. g. ' Phrase No,8-o1-93
The T6668 can use 4 kinds of bit rates as shown in Table 5.2; 8k, 11k, 16k and 32kbps, which are
selected by D6 and D7. Since a bit rate is independently speeirsed for sound recording/reproducing, it
is possible to change reproduced voice to slow I fast speaking. However, the phrases are reproduced at
low tone when slowly spoken and at high tone when rapidly spoken. Bit rate should be specified prior
to recording/ reproducing.
ij6668-12 Ci HtlT7iytn 00214953 BTI EITOSB
TOSHIBA (UC/UP) bltE I)
Table 5.2 Bit rate selection
8 Kbps 0 D
11 Kbps tl 1
16 Kbps 1 0 O=L level
32 Kbps 1 1 1=H level
(Caution) Selection of phrase and bit rate is decided when D4 pin is set at"H" level (startinput).
Switching of Recording l Reproducing Mode
Switching ofrecording / reproducing of the T6668 is made by the WE pin.
"H" level is ready to accept the recording and "L" level is ready to accept the reproducing.
Recording Mode
The T6668 has the 20 bit address counter, and voice data is written into RAM from the address
designated by that value. When making the sound recording newly, first, reset the address counter
by the TRE input. Setting of the ITm pin to "W' level results in the recording waiting state.
When the D4 pin is set to "H" level (start input), the recording starts and the address counter is
added successively. When the D5 pin is set at "H" level (stop input) or when the value on the address
counter reaches the maximum address (see 5.7) of RAM, the sound recording is stopped.
Since this maximum address is changed when the 256K, M1 and M2 pins are set, the full capacity
of RAM can be effectively used, However, when the RAM's capacity is fully used, subsequent
recording is not allowed. Therefore, to make the recording newly, reset the address counter again of
the TRT, input.
In T6668, when the sound recording starts, a value of the address counter at time of the start (start
address) and when the sound recording ends, that at time of the stop (stop address) are automatically
written into a part of RAM, respectively. Further, it is possible to monitor synthesized voices from
input voices through analysis and synthesis during the recording.
Reproducing Mode
When the W pin is set at "L" level, the T6668 is placed in the sound reproducing waiting state.
When the D4 pin is set at"H" level at this times the T6668 starts the sound reproducing after loading
the start address and stop address, which have been written at time of the sound recording, into the
address counter and stop address register, respectively. The sound reproducing is terminated when
the D5 pin is set at "H" level or when the value of the address counter agrees with the stop address.
ELIE 1) I: acmeuq unauqsu 235 IZITOSEI T6668-13
TOSHIBA (UC/UP)
DO, D2, D6, D7 'lr.
(Phrase, Bit Rate)
DI, D3 L -
(Phrase) c- Chattering by SW, etc.
._._. H -
WR L - -.akll th
(Recording/
Reproducing)
D4 L -
(Start)
D5 L -
(Stop)
EOS L-
M------------- -------i
Recording Reproducing
Fig.5.2 Recording I reproducing at phrase No.5, bit rate 32 kbps
. Refer to 5.6 Recording/ Reproducing via Index Area for details of recording/ reproducing, addition
of phrases and change of phrase contents when many phrases are involved, and refer to 5.9
Operation of Address Counter for the address counter operation.
5.4.5 Start, Stop Input and Internal Status
Phrase No., bit rate and recording/ reproducing status are all held at the leading edge ofinternal
start pulse. Further, external start input and internal start pulses are at the timings shown in Fig.
Start D4
i ) -Ttst.o _-.-...- (In case of no chattering by SW, etc.)
---e _--
Internal start pulse 1 +
Internal phrase, X X 16 msS tSADS 32 ms
bit rate, recording/ fosc = at 655 kHz
regroducing status F-rs-a-rc-sri-ar,-
Data holding
Fig.5.3 Start input and internal status
(il T6668-14 HE J) Cl 90'3729‘1 UUEH‘ISS 17q IZITOSB
TOSHIBA (UC/UP)
From Fig. 5.3, it is possible to input externally given IN-m (Phrase), INF-DT (bit rate), W
(recording I reproducing), D4 (start) and D5 (stop) as shown Pig. 5.4.
simultaneous input is possible.
00:03., D6, D7, 'ih7E
Internal start gulse Fl ll
Internal stag gulse ll n
EOS ll
In case of no chattering by SW, etc. EEE Don't care
Fig.5.4 How to give start input and stop input
5.4.6 Chattering Preventing Circuit
In the manual control mode, the chattering preventing circuit is actuated to prevent malfunction
by chattering of the switches connected to the D4 pin (start input) and D5 pin (stop input).
_._.v/i/""""'""'""''"""-"""""it
tch 1 ton I tch I toff
ton it 16 ms toff kt 16ms
Fig.5.5 Chattering preventing circuit
In case ofoperating in manual mode, start and stop inputs should be set. to min, 16ms.
III cuy3'7iill DUBLHSI: [IUD EITOSB T6668-15
TOSHIBA (UC/UP) HE l)'
5.5 CPU Control
In the CPU control, the operation ofT6668 is controlled by 9 kinds of commands. In addition, the
T6668 has a 8 bit status register and the external CPU is able to read the status of T6668 at any time.
In addition, the T6668 has the address overflow detector (Note 1) and the address comparator flip-
flop (Note 2), which control the sound recording and reproducing operations,
(Note 1) Address overflow detector ........... (Refer to 5.5.5)
(Note 2) Address comparator flip-flop ......... (Refer to 5.5.6)
5.5.1 How to Write CPU Command
As shown Fig, 5.6, using co tt7f pulse, read data from LSI and cheek BUSY bit. If not in © BUSY
state, after setting up command data in D0--D7, write a command usingiR- pulse. In case of such 3
byte commands as ADLDl, ADLD2, etc., after rechecking BUSY bit by © m5 pulse, write the co 2nd
and 3rd byte bits. After the 1st and 2nd byte bits ofa 3 byte command, other command bits cannot be
written.
Denotes LSI in output
state.
a l /t, / N, /-N, T'ss, /
sz-y-L_,,?" LV \._./
\_/ \Take into inside Nv/r"-"""
BUSY bit check
Command
fill,,,, check
Fig.5.6 How to write command
- -t-=Si--=leet- - ._ -
T6668-1 6
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TOSHIBA (UC/UP)
5.5.2 Commands ofT6668
0 = L tel
1 = H eve
(1) NOP MSit LSB x = Don'tCare
(lbyte) 0i0i0i0 XIXIXIX
N o operation. In the sound recording mode, this command is set in the sound reproducing mode
In addition, this command is used to reset ERR and OVR (refer to 5.2.3) in the status register.
MSB LSB
(2) START 0
(lbyte) IOIOI1XIX
This command is used to Mart the sound recording or reproducing in the direct mode from the
RAM address shown by the contents of the address counter.
(3) STOP M58
(lbyte) oIOI‘ILo XIXIXIX
This command is used to stop the sound recording or reproducing. If this command is given
during the sound recording by the LABEL command, the contents of the address counter at time of
stop are written into the index area ofRAM.
MSB LSB
(4)ADLDI 0 1 1 A19 A18 A17 A16
(3 bytes) I I I I
This command is used to set address in the address counter together with 2 bytes following that
address. When the 64Kbit RAM is specified, A19 and A18 are made to "OO" by force.
(5) ADLD2 MSB
A 7 A16
(3bytes) 0l1|010 A19'A1311 I
This command is used to Set address in the stop address register together with 2 bytes following
that address. When the 64Kbit RAM is specified, A19 and A18 are made to "oo" by force.
(6) CNDT
X SL BR1BRO
(lbyte) 0111011 I I I
(For SL, BRI, BRO, refer to the command list)
This command specifies a bit rate and silent state. When the silent state is specified, the DA0
pin is forced to become 1/2Nmo level. The silent state should not be specified at time of sound
recording.
© ''l0T?i?qn unauasa “163 EITosa - T6668-17
TOSHIBA (UC/UP) ELIE Di;
(7)LABEL MSB LSB (F L83 LB2 L81 dLBO f t th a d
or t ' ,an ,reero ecomman
(lbyte) Ol 14 1 l 0 LB3ILBZILB1ILBO list)
This command specirses phase No. (0--16) and starts the sound recording / reproducing.
When this command is given in the sound recording mode, the contents of the address counter is
written into the index area ofRAM and then, the sound recording is started. In case of the sound
reproducing mode, start address, stop address, and bit rate are read from the index area and
then, the sound reproducing is started.
(8) ADRD MSB LSB
(lbyte) 0L1I1I1XIXIXIX
This command is used to read out the contents of the address counter. By successive 3 times
of read access, high order 4bits, middle order 8 bits, and low order 8bits are output to D0--D7 in
that order. Ifnext command is given without performing 3 times of read access, the ADRD code
interrupted and the next command process is started, e.nablin g read out of the status register.
(9) REC MSB LSB
(lhyte) 1l0l0l0 XIXIXIX
This command is used to set the T6668 to the sound recording mode when it is in the sound
reproducing mode. The T6668 is returned to the sound reproducing mode by N OP command,
(Caution) During the sound recording / reproducing (that is, when the EOS pin or EOS bit of the
status register is 0), do not give any command other than STOP.
T6668-1 8
ENE D E3
TOSHIBA (UC/UP)
Table 5.3 Command list
90972”? UUEHHS: 6LT EJTOSB
Command 1st byte 2nd byte 3nd byte
Input Pin D7 -_--.------ D0 D7 —~—————— DO D7 T--------------- D0
NOP 0 0 0 0 X X X X - -
START 0 0 01 X X X X - -
STOP 0 010 X X X X - -
ADLD1 00.1 1 A19A18A17A16 A15A14A13A12A11A10A9A8 A7A6A5A4A3A2AIA0
ADLD2 0100 A19A18A17A16 A15A14A13A12A11A10A9A8 A7A6A5A4A3A2A1A0
L0101XSL BRI BRO
S L Bit Rate BRI BRO
Sound 0 r 8 K 0 0
Silent 1 11 K 0 1
16 K 1 0
32 K 1 1
LABEL 1.0.11_9__L_B_B__L_B_z_L_I11_L_§9_l ______________ : ______________ l _____________ : _''-"---.'.----"
MSB L53
L83 L82 L81 LBO = Phrase No (0-15)
ADRD 10_1vA...ic.p...t._l, ______________ T.' ______________ 1 _____________ : ______________
Read Output Data
1st 0 0 O 0 A19 A18 A17 A16
2nd A15 A14 A13 A12 A11 A10 A9 A8
3rd A7 A6 A5 A4 A3 A2 A1 A0
1000X X X X
© anwaus DDEH‘IEU 531. EJTOSB T6668-19
TOSHIBA (UC/UP) EHE 1)
5.5.3 Status Register
The status register consists of8 bits. When the R_D pin is set to L level (read access) under CPU
control, data of the status register is output to DO-D'? and the internal operating status of the T6668
can be checked. Each bit of the status register is explained in the following. (Table 6.4)
(1) BUSY
When this bit is 1, it indicates that the T6668 is in reset state or processing a command
internally. Do not give any command from CPU. If the command is given, the internal status
may possible becomes uncertainty.
(2) EOS
This bit becomes 1 during the not sound recording / reproducing and 0 when the sound
recording/ reproducing is started. This value is the same as the value. that is output at the EOS
(3) ERR
Command error. This bit becomes 1 when any undefined is given to the T6668. This bit is
reset by NOP command.
(4) OVR
Address over. It is indicated that the sound recording ends as the address counter exceeded
max. address (refer to 5.3) of RAM during the sound recording by LEBEL command. This status
bit is reset by NOP command.
(6) M2, MI
values of these bits are the same as those set at pin M2 and M1.
Table 5.4 Status register
Terminal Name D7 D6 D5 D4 D3 D2 D1 D0
Status Register BUSY EOS ERR OVR M2 M1 0 0
0 = L Level Ira H Level
5.5.4 Busy Bit
Conditions for setting BUSY bit of the status register to 1 are broadly classified into the following
3 conditions. That is, BUSY bit is set to 1 during the reset period of T6668, during the process of
command given externally, and during the process after stop of the sound recording due to address
overflow, (Table 5.5)
(1) Reset Process
When the EOE pin becomes L level, BUSY bit becomes L When the ACL pin returns to H level
again, the internal state ofT6668 is initialized and after all are completed, BUSY bit becomes 0.
T6668-20
TOSHIBA (UC/UP)
(2) Command Process
t3 e595é49 DDBHHEL H76 EJTosa
When it is detected that both of the CE and TTOT pins have become L level in the CPU control,
BUSY bit become I. When the process of all command is completed, BUSY bit returns to 0 again.
The command process is actually started after return of the least either one of the CT? or W pin to
H level has been detected. (The table shown below also indicates times for BUSY bit to become 0
after the CE MW pin returned to "H"level0
(3) Address overflow process
When the address counter is overflow during the sound recording in the label index mode, the
T6668 automatically stops the sound recording. During this period, BUSY bit also becomes 1.
Table 5.5 BUSY generating length
BUSY Generating Conditions t.enti'/'ig1x)
Reset process (after KIT) 3 t ,
NOP, START, CNDT, REC Command 3 t s)
1st byte 4 t f
ADLDI, ADL02 Command
2nd,3rd byte 3tis
ADRDCommand 4tg
Sound recording mode 35tp
ADLD1, ADLD2 Command .
Sound reproducing mode 67 t f
During sound recording in label inclexmode 40 t f
STOP Command
Others 3 t ti
Add ress Overflow Process 34 t f
t , $5.3 ps @ fCLK = 655 kHz
Address Overflow Detector
When the address counter exceeds maximum address that is determined by the pin 256K, M2 and
MI, it is detected by this detector. When the LABEL command is given in the sound recording mode,
it becomes valid and is kept until the NOP command is given. When the address overflow is detected,
the sound recording is stopped, a value of the maximum address is written into the index area as the
stop address and then, the address counter is preset at address 00400H. In addition, the OVR bit of
status register is set.
During this period of processing, BUSY bit of the status register also become l,
© 3097mm unaueba 3IW IZITOSB T6668-21
TOSHIBA (UC/UP) EL”; 1) _
5.5.6 Address Comparator Flip - Flop
The sound recording / reproducing is stopped if the contents of the address counter agrees with
those of the stop address register when this flip .. flop has been set. When it has been reset, the sound
recording / reproducing is not stopped until the STOP command is given. (Exception: Address
overflow in the preceding item)
This flip - flop is set when the ADLD2 command is given or when the LABEL command is given in
the sound reproducing mode, and is reset when the ADLDl command is given or when the LABEL
command is given in the sound recording mode.
5.5.7 Modes in CPU Control
There are two ways about both recording and reproducing ofT6668 when it is under CPU control.
That is, one is the Direct mode and another is Label / Index mode, The former is the way to write start
address, stop address and bit rate of each phrase by command, and the latter is to designate phrase
number so that T6668 write the above mentioned parameters into the certain part of RAM.
So, at the Label / Index mode, the certain part of RAM (s) is used for Index area. On the contrary
at the direct mode, such a part can used for data area (Fig. 5-7).
00000H
RAMI ) Index area-aCan be used for data area
00400H -------
3FFFFH
7FFFFH RAM3 Data area
BFFFFH
FFFFFH RAM4
256 K D-RAM
Fig.5] Memory map at direct mode
* Refer to 5.6 RECORDING VIA INDEX AREA for details of recording I reproducing, addition of
phrases and change of phrase contents many phrases are involved, and 5.9 OPERATION OF
ADDRESS COUNTER for address counter operation.
T6668-22 Cl ''itlcr7iy+cl Cll3iillla3 ELM] EITOSB
TOSHIBA (UC/UIS; - ”ME 1)
5.5.8 The Flowchart of Recording / Reproducing in Label Index Mode
(1) Recording
A L = L ......._...r....... Reset the address counter of T6668
ATI = H ........................ Release
In case of Input of REC r
changing bit command '.rCt...0..rcq..F...r.q. Be ready for recording
rate '
r --------.---q.._ -
I Input of CNDT ........................ Setting the bit rate
command -
- Setting of phrase.
Input of LABEL ...i.g..r_.B.e.. Recording starts immediately after
command
br- command process
f Checking if recording length exceeds the
L RAM (s) capacity.
Decide to stop the recording or not.
Input of STOP
command
..................... To stop recording
Continue next
other phrase? ......-........ I Decide to continue next other phrase.
Fig.5.8 Recording in label / index mode
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T6668-23
TOSHIBA (UC/UP)
(2) Reproducing
1e:,ttlte'' ........................... [Be ready for reproducing
Input of LABEL Setting of_phrase. . .
............r-............. Reproducing starts immediately after command
command [ process .
.b...............r....... [ Checking if reproduction of one phrase terminate
.._.....-.... I: Decide to reproduce other phrase
Note: In CPU control mode, bit rate is that settled previously at the recording and fast / slow
speaking cannot be specified as in manual control mode.
Fig.5.9 Reproducing in labellindex mode
T6668-24
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TOSHIBA (UC/UP) -,
5.5.9 The Flowchart of Recording /Reproducing AT "DIRECT MODE"
(1) Recording
Input of REC
command
In case of
changiryh.tt.s.ilt.s
----- o-
Input of CNDT
command
Input of ADLD1
command
...o..r_........ f Reset the address counter of T6668
(Note 1)
Input of ADLD2
command
Input of START
command
state.
Release
Be ready for recording
Setting the bit rate
Designation of start address
. Designation of end address
. Start recording
. Checking if EOS is "I " or "o"
Decide to continue at other or same address
If ADLD2 command is not designated, recording become endless
In this case, recording should be terminated by using STOP
command
Fig.5.10 Recording in direct mode
EHE 1) Dfm'awua UUEH‘lbb TST EITOSB T6668-25
TOSHIBA (UC/UP)
(2) Reproducing
Input of NOP
In case of command
changing bit
...................... [ Be ready for reproducing
Input of CNDT
command
Input of ADLD1 _....................... L Designation of start address
command
(Note 2) -
Input of ADLD2 ........................ Designation of end address
command
Input of START ........................ Start reproducing
command L
........................ I: Checking if EOS is "1" or "O"
Reproduction?
"""""""""""" l: Decide to reproduce other or same address
Note2 :When ADLD2 is used as the maximum address of RAM during recording and omitted
during reproducing, endless speaking becomes possible. STOP command is used to
terminate it.
Fig.5.11 Reproducing in direct mode
T6668-26 1) El 'NTi'iill DDELICHJ? 9% EITOSB
TOSHIBA (UC/UP) bug
5.6 Recording / Reproducing Via Index Area
The recording/ reproducing methods by the manual control of the T6668 and the label index mode
in CPU control are described here. In the manual control (LABEL command under CPU control), the
recording/ reproducing is indirectly performed as the T6668 writes start addresses, stop address and
bit rate of each phrase into a part of RAM and selects phrase number. The memory maps of RAMs in
the label index mode are as follows.
OOOOOH OOOOOH
RAM1 Index area RAM1 ) Index area
00400H _-..--...-...-.- , 00400H _-----.--.-,
RAM1 RAMI
OFFFFH 3FFFFH
RAM2 RAM2
IFFFFH F Data area 7FFFFH L Data area
RAM3 RAM3
2FFFFH BFFFFH
RAM4 RAM4
3FFFFH y FFFFFH A
64K 256K
Fig.5.12 Memory map in level index mode
Maximum number of addresses that can be used varies depending upon type and number of
externally connected D - RAM. In may case, addresses 00000H-003FFII are used as the index area,
and the succeeding address 00400H and up become the voice data area.
Start address, stop address,' and bit rate are recorded in the index area by the T6668 at time of
sound recording, and data read out from this area are loaded on the address counter, etc. at time of
sound reproducing.
5.6.1 Recording of Phrase
In performing the recording newly, F1rst reset the T6668 by the TOT, input. The internal address
counter is preset to 004000H at this time.
Then, when the start signal is input by specifying a bit rate and phrase No., the recording starts.
After the contents of the address counter at this time; that is, start address is written into the index
area of RAM, actual recording is started. During the recording, the contents of the address counter
are added successively.
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TOSHIBA (UC/UP) -
When the stop signal is input during the recording, the recording ends, The contents of the address
counter at the time; that is, the end address and bit rate are written into the index area of RAM, Thereafter, the
contents of the address counter are added with one (+ 1) and preparation for next recording is performed.
To perform the recording with other phrase successively, Phrase No, is newly designated and the
start signal is input (Fig. 5.19).
c.Index area l Data area ,
I rl‘ I
l i o Current address counter
E E Phrase1 Phrase2 Unused i
l I "l h l
00400H (" ( oPhrase 2 end
oPgrase 1 end address
a dress a Phrase 2 start address
. Phrase 1 start address (Phrase 1end address + 1)
Fig.5.13 In case of recording phrase 2
5.6.2 Reproducing of Phrase
If any already recorded phrase No. is selected and start input is give, voice corresponding to that
phrase No. is reproduced. Phrase No. at this time can be designated irrespective of sequence of the
recording. Further, it is also possible to stop speaking by giving the stop input in the middle of the
reproducing. Thereafter, when the start input is given again using the same phrase No., the
reproducing is performed from the beginning of that phrase, If the reproducing is started by
designating phrase No. that was not used for the recording, what sound is reproduced is uncertain.
However, it is possible to stop the sound reproducing by giving stop input, The reproducing is started
after the start address, end address and bit rate are set in the T6668 from the index area. When the
start input signal is given by specifying next phrase No. during the reproducing in the manual
control mode, this next phrase is spoken successively after end of the preceding phrase generation,
because T6668 has a buffer for phrase No. When the start input signal is given several times during
speaking of one phrase, the last phrase speeifieMion remains in the buffer. As the bit rate has no
buffer, however, the bit rate of a phrase during the reproducing becomes the bit rate of next phrase in
change the phrases with differentbit rates.
5.6.3 Addition of Phrase
First, reproduce the last phrase at the recording to the last in the reproducing mode. At this time,
the address counter stops while indicating address next to the end address of the last phrase. Change
the reproducing mode to the recording mode. Do not reset the T6668 at this time. When the
recording is made by designating any unrecorded phrase No., phrase can be added.
T6668-28 ELIE D CCI ''liy'r?iytn UEIEHHE‘J '?ian EITOSB
TOSHIBA (UC/UP)
5.6.4 Change of Phrase Contents
To change the contents of phrases that have been once recorded, reprod use a phrase preceding the
phrase that is to be changed to have the address counter indicate the start address of the phrase to be
changed. (For example, when Phrase No. has been recorded in order of 5-7-3-6 and the contents of
phrase No. 3 are to be changed, reproduce phrase No. 7 to the last.) Do not reset the T6668 at this
stage. When the recording is made by designating phrase No. that is to be changed successively, the
contents of that phrase are changed to the new contents. At this time, if the recording time of the
changed phrase is longer than that of the phrase before changed, the first part of next phrase may be
changed. When the changed phrase is reproduced under this state, the new contents are spoken
properly but when it is tried to reproduce next phrase, the reproducing is started at the middle of the
changed phrase and when the reproducing ends, sound is produced successively from the middle of
next phrase. This is phenomenon that is taken place as the start address of next phrase written in the
index area remains unchanged from the previous address. On the contrary, when the recording time
of the changed phrase is shorter than that before change, the latter part data of the phrase before
change is left. When this part is reproduced, the last speaking of the changed phrase stops. Needless
to say, next phase is also properly reproduced.
Under this state, a RAM for the part between the end address of the changed phrase and the start
address of next phrase is not used. (Fig. 5.20)
Phrase to be changed
Index area C-
l 1 Phrase 5 Phrase 7 Phrase 3 Phrase 6
00400H Phrase 7
°When the recording time of érepro -
the change phrase is shorter ucing) Phrase3
-------v
than that before change. (recording)
Phrase 3
-.-----r-t
(reproducing Phrase 6
(reproducing)
°When the recording time of Phrase 3
the change phrase is longer (recording) (even
than that before change. Phrase 3
Phrase 6
(reproducing
‘ F-t r
(reproducing) Reproduce the content of phrase 3.
Fig.5.14 Change of phrase contents
El “£0922”? UDEH‘H‘U [+81] DTOSB
T6668-29
TOSHIBA (UC/UP)
EHE p 'u
(D The contents of the index
register are loaded on the
address counter of D - RAM
by the start signal.
© Values ofthe address
counter of the T6668 are
written into the index
counter. (Start address)
© Values of the address
counter of the T6668 are
loaded on the address
counter of D - RAM
Voice is anal zed (recorded)
by ADM ana yzing and
synthesizing device and
voice data is written into
the data area.
The address counter is
counted up and steps ©
and © are repeated, (1
cycle of Wt? = Bit rate)
© The contents of the index
resist are loaded on the
address'counter of D - RAM
by the stop signal.
© The value of bit rate is
written into the index area.
© The value of the address
counter of T6668 is written
into the area.
(9 The address counter of
T6668 is counted up and
the recording end.
5.6.5 Address and Data in Label Index Mode
The operations of the T6668 and D - RAM in the label index mode are described in the following.
(1) At time recording
Start Index register Address
signal A0-A8 Countor
------- w -et
"i:',: Jd (D A0-A8 t
f? w'i Index area
it Ti Address (SDIN Douro
f, jk' countor Data area
E E DOUT 2) DIN
o >, l T
< m Stop address
register
W T6668 ! I D-RAM (256K)
tte Index register Address
A0..A8 countor
ADI '0 8 G t.--"-tt.,
g 'r, t3 AO-Atl t
Record m 43 +1 (S) Index area
-mg E m
s)., .5 Address 00m DomcL
g 17, countor Data area
4 E ' Voice data ,‘DouT EO DIN”
"t a g, n: r
W < Vt Stop address
Monitor register
(DAO) I I
S.top ttt Index register Address
signal p, g AtP-A8 countor
m > _ ft
tn '8 © A0~A8T t
E m ol C)') Index area
E a Address l, D
G IN oum
g fl counter f Data area
0 i D D
< m Stop address OUT IN
register
Bitrate th
Fig.5.15 Access to memory in recording
T6668-30
ELIE D E! '3Cl'T?iiy4n iriiyFih" 32b? CITOSB
TOSHIBA (UC/UP)
(2) At time of reproducing
:itghtal Index register Address
N coun er
_, U 8 A0 A8 /
g "ii (i) A0--A8 t
i? g I d ©
- 5, Address / n ex area
3. y.';.. counter /dir-i-"-ou-ris'
il x t:' Stop address Dour Dm Data area
< i? register 0 0 (3
Bit rate
Index register Address
MV-MN © counter
.0 8 t Y--
g .; A0~A8 i ©
tpp-tl “W
.E 0, ©
s'?, .'-,iil Address A__@___( Index area
zepro- 'i' ',i? counter
ucmg g E , " Data area
‘4 4 ip Stop address tr 0
W ( register
Fig.5.16 Access to memory in reproducing
The contents of the index
register are loaded on the
address counter of D - RAM by
the start signal.
Start address is loaded to the
address counter of T6668 and
end address as well as bit rate
are loaded to the stop address
register, respectively, from the
index area.
Values of the address counter
of the T6668 are loaded on
the address counter of D -
Voice data is out into ADM
analyzing and synthesizing
device to reproduce voice
waveform.
The address counter of the
T6668 is counted up.
The address counter and the
sto address register of the
T6 68 are compared and
when they agree with each
other, the reproducing stop at .
next address.
if not, steps C3)- © are
repeated.
CCI émvaue [mauve 253 IZITOSEI T6668-31
TOSHIBA (UC/UP) [:HE I) a
5.7 Maximum Address of RAM
When the contents of the address counter reach the maximum address during the recording in the
label index mode at the manual and CPU controls, the T6668 stops the recording automatically. In
this case, the maximum address is stored as the the end address of a phrase at that time. Further, the
address counter is preset at 00400H address and stops there.
Therefore, in the recording I reproducing of the one phrase only, the stop switch (D5) becomes
unnecessary. In other words, when a certain time has passed after starting the recording (when the
recording is made to the last of RAM), the recording ends and also, the reproducing stops after the
contents of RAMwere spoken to the last.
This maximum address changes according to the settings of the pin 266 K, M1 and M2 of the
TMM, These pins shall be set according to kind and quantity of externally connected RAM. (Table
Table 5.6 External RAMs and maximum addresses
External RAM 256 K M2 M1 Maximum Address
64K D - RAM 1 pc. Pte 0 o FFFFH
64K D - RAM 2 pcs. 0 0 1 1FFFFH
64K D - RAM 3 pcs. 0 1 0 2FFFFH
64K D - RAM 4 pcs. 0 1 1 3FFFFH HEX
256K D - RAM 1 pc. 1 0 O 3FFFFH
256K D - RAM 2 pcs. 1 0 1 7FFFFH
256K D - RAM 3 pcs. 1 1 0 BFFFFH * Note
0 = L level
256K D .. RAM 4 pcs. 1 1 1 FFFFFH 1 = H level
T666333 ENE J) © qnqvaua 0029973 -riiri::r//ij-:hr"---
. . TOSHIBA (UC/UP)
5.8 Reset Operation
5.8.1 The Status during Reset Operation
Low level to "A-cr," pin causes the reset to T6668 in both of the manual control and CPU control, and
all operations such as recording / reproducing stop. However, the refresh counter continues to operate
and therefore, the data stored in D - RAM(s) remain unchanged. Further, BUSY bit of status register
becomes 1 during this period and therefore, recording / reproducing start inputs under the manual
control mode and command input under CPU control mode should not be given,
5.8.2 The Status after Reset Operation
When ACL pin becomes from L to H level, the internal state of T6668 is initialized as shown
below.
(1) In CPU control mode, it becomes reproducing mode.
(2) Address counter and stop address register are preset to 00400H.
(3) Address overflow detector and address comparator flip - flop are reset.
(4) In CPU control mode, bit rate becomes 8Kbps, and "Silence Status" is released.
(ti) ERR and OVR bits in status register are reset.
After terminating the above completely, BUSY hit in status register is set to "O".
5.8.3 Reset Processing after Power ON
After Power ON, the following items become instable;
(1) Change - over of recording / reproducing modes
(2) Address counter
(3) ADM arithmetic system
(4) Other processing registers such as start and stop processing
Therefore, to initialize this instable condition and assure proper operations, apply ACL signal.
(System reset)
EITOSEI
© 905172”? UDEH‘I?“ DEE: T6668-33
TOSHIBA (UC/UP) InHE D
TRT, signal to be given after power ON and its pulse width are shown in Fig.5.13.
A-tT. If- 1.56 ps (MIN.)
lnstable )
Internal"BUSY" bit - 45.8 ps (MAX.)
(Refer to 5.5.4)
Fig.5.17 MI pulse width
However, if width of tDA after power ON is long, the instable status lasts and causes malfunction
(start of recording / reproducing, etc.) in Fig.5.18. So, in [10] Application Circuit in the manual
control mode, an automatic clear circuit is configured to input integral waveform by time constant of
a pull-up resistor (7 k--20 kn) housed in the r0T, pin by attaching a 1,111“ capacitor to the ECE pin,
making the system initialization possible immediately after power ON as illustrated in Fig.5.18.
7itTL R (7 k-20 kn)
lpf rt C
Fig.5.18 Circuit for power on reset
1(ti.,I
TRTL VlL I E
+: 'el-tAcc (determined by time constant of CR-R =7 kn 6.7 ms/hr)
i XNote
Internal"BUSY" bit --t E taY'
i-----'"--------',
Fig.5.19 ACL input at power on reset
T6668-34 _ -_ but» i: qdénua 003mm TEE EITosa
TOSHIBX , UC/UP)
However, the power on reset is effective only for a step power rise and when power rise is gentle,
no system initialization is performed. (Fig.5.20)
Power source _.----'''''"''"'"'""
Mr. n..--.--"''--'"'""""""''-''" VIL
VIL cannot be detected and system
initialization is not possible.
Fig.5.20 In case power rise is gentle
Further, if the ACL pin can be controlled under CPU control mode regardless of power ON / OFF
atT6668 side, the system initialization can be applied as shown in Fig.5.21.
Power source _.._.,/''"
(Varying depending upon stable status of power
-r,' - rise,several ms are required.)
t' 1 *Note
Internal "BUSY" bit ---- ...' f t tBY' I
Fig.5.21 System initialization by CPU control
* Note tuyv is a time from power ON till oscillation is stabilized and varies depending on an
external oscillator. (Several ms in case if CSB655)
ELIE I) III 909721“? MiiA'3'?la Tl'H IZITOSB
TOSHIBA (UC/UP) c,
5.9 Operation of Address Counter
T6668-35 ill
The operation of address counter of the T6668 and the memory map of the index area are described
_R-A-S- I----.---,
A0--A8 iiiiiEEEEy ROVXDDRESSX COLUMNADDRESS (Ei5bti5EEE
2%Egg Refresh address
Pin name -ims A1 5A8 A1
COLUMN ROW
Designate 256 K A17 _____...___ A9 A8 A0
address
64 K A15 ---------A8 -ttt-----tstt-
Fig.5.22 Address output
IWIIWUIN\lWWWWWWWIWWWWWNW"WWIWW
T6668-36VIQE nil: Vfiuvauq Gievrri, 335 ©TOS3
TOSHIBA (UC/UPI‘
Ji.10 Connection to D - RAMS
The T6668 needs outer D - RAMs (dynamic RAMs) for the storage ofrecorded voice data.
Maximum four 64K D - RAMs or four 256K D - RAMs are directly connected to the T6668. But is
impossible to connect 64K D - RAMs and 256K D - RAMs at the same time.
* A8 is not used for
64K D - RAM
V551 (GND)
Fig.5.23 Connection with D - RAM
Fig. 5.23 shows the connection with D - RAM. In case of two or more D - RAMs, tThTrl pin T6668
must be connected to the tTh-g pin of Ist D - RAM, the tThi pin ofT6668 to the tis pin of 2nd D -
RAM and so on. That is, -ChW1utA-S4 pins must be connected to the cis pin of D .. RAMs,
respectively. Other pins about D - RAM of T6668 may be connected in parallel to every D - RAMs.
(See 3.3 "Example of Voice Recording / Reproducing LST System Configuration". ) Some pins of
T6668 must be settled high or low according to the type and number of outer D - RAMs. Table 5.7
shows the setting conditions. These conditions shown in Table must not be changed during recording
or reproducing operation. .
511E 1) 1:1 Quanta nuauava 771 DTOSEI T6668-37
TOSHIBA (UC/UP)
Table 5.7 Pin setting according to type and number of D - RAMs
Pinname Pinname 2:-
Type 256K Numbe M2 M1
ofD-RAM ofD-RAM
256K 1 1 pc 0 0
64K 0 2 pcs 0 1
3 pcs 1 0 = L level
4pcs 1 1 1 = H level
5.11 Analog Function
The T6668 has built in microphone amplifier and 2nd stage low pass-l-lst stage high pass filter,
Therefore, voice recording I reproducing system is easily available by connecting input to MIC and
output to audio Amplifier circuit. .
5.11.1 Microphone Amplifier
FILOUT
H Cl MIC
MICOUT
Fig.5.24 Connection of MIC
Note:Be careful for wiring. The signal from microphone is so small that noise from surroundings
tends to have influence.
T6668-38 ENE I) © 90973'49 0039979 [:06 Iz1T0S5l
?EMBITUC/UP)
There are two MIC, AMP. s.
co betweenMICIN and C1 ................... Gainis about26 dB
© between C2 and MICOUT ................. Grain is about 20 dB
So, there are three ways co, © and C) +O, One is selected by the type ofMIC. CI or MICOUT pin
must be connected to ADI pin at the case ofCD or © and co -rC0, respectively.
102 103 104 (Hz)
Fig.5.25 Frequency characteristics of MIC. AMP.
This characteristics is between MICIN and MICOUT with couplings C1 and C2. Further, when
MIC Amp is not used, it is possible to input voice directly input ADI. In this case, however, the input
level should be max. 1.6 Vp-p, centering around 1/2 VDD.
ELIE I) [II '30T?iilqn UDEHHBU BET DTOSS T6668-39l]
TOSHIBA (UC/UP) '
5.11.2 Filter
DAO w, t ft
FlLIN -__1"_]
FILOUT
T52 - !
TSI - P" 68k Vno
SP(8 m
rr TA7368P
Fig.5.26 Connection of audio amp.
(dB) 0
102 103 104 (Hz)
Fig.5.27 Frequency characteristics of band pass filter
This characteristic is between FILIN and FILOUT.
T6668-40 ELIE I) © ''itl'T7i?ttt'l DUELIQBJ. aw: Enos:
TOSHIBA (UC/UP)
5.11.3 Equivalent Circuits
600 kn 300 kn
_ 'tl,
1pF 7.348 pF
t'f c2 Cl-Nh-, ----Cl MIC
---r--- Cl
30 kn Cl 30 kn OUT
MICAMP
23.18 Mil
3.37 pF 3.37 pF
ll II II
II II ll
11.45 pF -
Cl-sth-- - 23.1mm - 23.1mm -
m 11.458 pF um -2-u'/ffr- + m,
IN + + + OUT
23.18 Mil
l 4.7IBpF
Vref BPF
Fig.5.28 Equivalent circuits of analog circuits
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TOSHIBA (UC/UP) - - J-
5.12 Precautions
(1) Under manual and CPU control mode
During recording or reproducing operation, pins of MI, M2 and 256K must not be changed.
During the reset, the address counter, flag, etc. only are reset and oscillation does not stop; that
is, the refresh of D - RAM is performed.
(2) Under manual control mode
The conditions of phrase, bit rate and recording / reproducing are kept held by START input
and not changed until next START input is given. That is, T6668 does not care those
conditions after START operation has done.
During recording, START input is not accepted. This is to protect RAM data in the index area
from being destructed when phrase number etc. are changed by START input during
recording.
During reproducing, START input is accepted as the buffer function is available.
In this case, the operation must not be started with W placed in H level (recording mode).
RAM data change and the reproducing is not properly performed.
The START input during the recording is inhibited at address over condition (when the
maximum RAM capacity is already used.). Resets address by ACL for recording.
(3) Under CPU control mode
During recording / reproducing, do not give any other commands other than STOP command.
When other commands are input to the T6668, the operation becomes unstable.
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6. ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Rating
SYMBOL ITEM RATING UNIT
l/oo Supply Voltage - 0.3 ' 6.0 V
VIN Input Voltage - 0.3 - Vpo + 0.3 V
VOUT Output Voltage - 0.3 -- VDD + 0.3 V
TSTG StorageTemperature - 55 -- 125 "c
6.2 Recommended Operating Condition
ITEM SYMBOL RATING UNIT
SupplyVoltage VDD 4.5 ~ 5.5 V
Input Voltage VIN O 'VDD V
Output Voltage VOUT 0 - VDD V
Oscillation Frequency fCLK 640 _ 1000 KHz
Operating Temperature Top, - 10 .- 70 "C
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T6668-43
DC Characteristics (VDD = 5 V i 10 %, Ta = 25 "C)
SYMBOL ITEM CONDITION MIN. TYP, MAX. UNIT
Input Current - - .
IIH (Dir-Dr, TEST, tTE", TW, 7im) 1hy - VDD, CPUM - L 20 100 500
lm InputCurrent1DlN) Vm =0 50 100 350 PA
|le Input Current 2 (RI) VIN = 0 250 500 700
lirk Input Leak Current VIN = o-von, CPUM = H - - f.: 10
VIH” High Level Input Voltage1 DO--D7, tTit, RD, WR DIN 2.4 - -
Vlle High Level Input Voltage2 Except above 4.1 - - V
Ihr, Low Level Input Voltage! D0~D7, t1Tf, R_D, WR, DIN - - 0.8
Vle Low Level Input Voltage2 Except above - - 0.4
lor, High Level Output Current Vom = 2.4 V 0.5 - -
lor Low Level Output Current Vout = 0.8 V 0.5 - - mA
Iss1 SupplyCurrent1(Vss1) Under no signal, lour=0 mA - 1.0 3.0
lssz Supply Current 2 Nssa) Under no signal, IQUT = 0 mA - 1.0 3.0
NotezEach TYP.va1ue is under VDD =5.0 V, Ta = 25 t
MIN. and MAX, values are defined by their absolute values,
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TOSHIBA (UC/hp)
6.4 AC Characteristics (VDD ti'.'.' 5 V i 10%, Ta = 25 "C, chK =_655 kHz, CL = 50 pF)
6.4.1 For Data Read (Status Reading)
SYMBOL ITEM MIN. TYP. MAX. UNIT
tRD Read Disable Time (ADRD Command) 21 - - [IS
tAcc Read Access Time - - 300
too Output Disable Time - - 150 ns
Data Read (1)
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tAcc -
Data Read (2)
a l st-----''"'----"':..-.,.....,
FE §§§§§§§§k dEEEits,
D?SUPS tacc VALID tor,
5::s? Don't Care
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TOSHIBA (UC/UP)
6.4.2 For Data Write (Command Write)
SYMBOL ITEM MIN. TYP. MAX. UNIT
tog Data Set Up Time 500 - - ns
tDH Data Hold Time 0 - - ns
twnp WTi Pulse Width 300 - - ns
Data Write (1)
Data Write (2)
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6.4.3 For Voice Analysis (At Recording)
SYMBOL ITEM MIN. TYP. MAX. UNIT
tASR Low Address Set - up Time 150 - -
tRAH Low Address Hold Time 500 - - ns
tRAs RAS Pulse Width - 4.58 - ps
tAsc Column Address Set - up Time 150 - -
tCAH Column Address Hold Time 500 - - ns
tCAS CAS Pulse Width - 3.05 - p5
twcs Write Command Set - up Time q - 1.53 -
twiys WE Pulse Width - 3.05 - ps
tows Data Output Set - up Time 500 - -
tDWH Data Output Hold Time 500 - - ns
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- tcas
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CAS1-CAS4 k
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ROW COLUMN
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DOUT VALID
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6.4.4 For Voice Synthesis (At Reproducing)
SYMBOL ITEM MIN. TYP. MAX UNIT
tocs Data Input Set - up Time 500 - - ns
chH Data Input Hold Time 0 - - ns
, 1MS ‘I
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tcas -
CAS1-CAS4 - /
tAsn tRAH ttssc tom
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COLUMN
tDCS inc”
VALI D
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T6668-48
TOSHIBA (UC/UP)
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6.5 Characteristics of Analog Function
6.5.1 Micamp. (V551: V552 = ov, VDD = S V, Ta = 25 °C, fin = 1 kHz, UNLESS OTHERWISE SPECIFIED)
SYMBOL ITEM PIN NAME CONDITION MIN. TYP. MAX. UNIT
VlN1 MICIN MICAMP“) + (2) - 6 8
I/ea Allowable Input MICIN MICAMP (1) only - 60 80 mvp_p
Voltage Range
ViN3 C2 MICAMP (2) only - 120 160
Gul -M|COUT - 46 -
G . MICIN VIN = 6mVp--p - 26 -..
V2 Pass Band Gain -C1 “N = 100 Hz ~10 kHz d8
GV3 -MICOUT - 20 -
THD Total Harmonic MICIN Vm = 6 mVp - p - - 2 o
Distortion -MICOUT M = 100 Hz - 10 kHz '4
RIM l tR . t MICIN 20 30 40
R|N2 npu esns ance C2 20 30 40
Roun O t tR . C1 - 1 -
u U eslstance - KO
Roun p MICOUT - 1 -
65.2 Band Pass Filter(D|TTO)
SYMBOL ITEM PIN NAME CONDITION MIN. TYP. MAX. UNIT
Allowable Input
vm Voltage Range FILIN - - 2.4 2.6 Vp-p
. FILIN Vm = 1.0Vp-p -
GIt Pass Band Gain -FlLOUT fm = 100 Hz - 10 kHz - 27 - 1 d3
Total Harmonic FILIN I/tN = 1.0 Vp - p -
THD Distortion -FILOUT hs = 100 Hz -- 10 kHz - 4 5h
Rm Input Resistance FILIN - 5 14 20 Mn
Rom Output Resistance FILOUT - - 1 - kn
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T6668-49
TOSHIBA (UC/UP)
6.5.3 Audio In (DITTO)
SYMBOL ITEM PIN NAME CONDITION MIN. TYP. MAX. UNIT
Allowable In ut
VIN Voltage Range ADI - - 1.2 1.6 Vp- p
Rm Input Resistance ADI - 1 - - Mn
6.5.4 Audio Out (DITTO)
SYMBOL ITEM PIN NAME CONDITION MIN. TYP. MAX. UNIT
ROUT Output Resistance DAO - 5
Note :Values centering around 1/ 2 VDD are used in allowable input voltage range.
TOSHIBA (uffup)
6.5.5 Measuring Circuit
(VIN, Gy, THD)
Refer to [4] Pin Connections for pin name.
VDD 5V
TOP VIEW
OUTPUT(FILOUT)
r-tNttt
0.1 x 2
GND A OUTPUT (MICOUT)
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TOSHIBA (UC/UP).
7. OUTLINE DRAWINGS
60 PIN MINI FLAT PACKAGE
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0.8PITCH nit
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(17.6i:0.3) ,
(0.15 Ji',) -------.._.._.....--._._ I -.------- 1.91-02 2.25MAX
, pgitszz,,
1.54c.0.2 I 045:0.1
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APPLICATION CIRCUIT
Manual control
---4y-0-o ' " 68k
II 100;:
------oGND
l Digital ground MIC
l, Analog ground
BIT RATE (
PHRASE
5 liitiliilihse
* 0.1 A' capacitor is needed between
Vcc and of D " RAMs.
TMM41256
6 Vss t:7's-
RAM, RAM:
www.ic-phoenix.com
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