STWD100NYWY3F ,WatchdogFeatures Current consumption 13 μA typ. Available watchdog timeout periods are 3.4 ms, 6.3 ms, 10 ..
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STWD100NPWY3F-STWD100NYWY3F
Watchdog
March 2014 DocID014134 Rev 8 1/25
STWD100Watchdog timer circuit
Datasheet - production data
Features Current consumption 13 μA typ. Available watchdog timeout periods are
3.4 ms, 6.3 ms, 102 ms and 1.6 s Chip enable input Open drain or push-pull WDO output Operating temperature range: –40 to +125 °C Package SOT23-5, SC70-5 (SOT323-5) ESD performance HBM: 2000 V RCDM: 1000 V
Applications Telecommunications Alarm systems Industrial equipment Networking Medical equipment UPS (uninterruptible power supply)
Table 1. Device summary
Order code Temperature
range Package Packing Topside
markingSTWD100NWWY3F -40/+125 °C SOT23-5L Tape and reel WNW
STWD100YNWWY3F(1) -40/+125 °C SOT23-5L (automotive grade) Tape and reel WYNW
STWD100NYWY3F -40/+125 °C SOT23-5L Tape and reel WNY
STWD100YNYWY3F(1) Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 and Q002 or equivalent
-40/+125 °C SOT23-5L (automotive grade) Tape and reel WYNY
STWD100NPWY3F -40/+125 °C SOT23-5L Tape and reel WNP
STWD100YNPWY3F(1) -40/+125 °C SOT23-5L (automotive grade) Tape and reel WYNP
STWD100PYW83F -40/+125 °C SOT323-5L Tape and reel WPY
Contents STWD1002/25 DocID014134 Rev 8
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Watchdog input (WDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Watchdog output (WDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Chip enable input (EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DocID014134 Rev 8 3/25
STWD100 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2. SOT23-5 and SC70-5 (SOT323-5) pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 4. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 5. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 6. SOT23-5 - 5-lead small outline transistor package mechanical data . . . . . . . . . . . . . . . . .19
Table 7. SC70 (SOT323-5) – 5-lead small outline transistor package mechanical data . . . . . . . . .21
Table 8. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 9. Device versions with marking descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 10. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
List of figures STWD100
4/25 DocID014134 Rev 8
List of figures
Figure 1. SOT23-5 and SC70-5 (SOT323-5) package connections . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. Open drain WDO output connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 5. Interfacing to microprocessors with bidirectional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 6. Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 7. Normal triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8. Timeout without re-trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 9. Trigger after timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 10. Enable pin, EN, triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 11. SOT23-5 - 5-lead small outline transistor package outline . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 12. SC70 (SOT323-5) - 5-lead small outline transistor package outline. . . . . . . . . . . . . . . . . .20
DocID014134 Rev 8 5/25
STWD100 Description
1 Description
The STWD100 watchdog timer circuits are self-contained devices which prevent system
failures that are caused by certain types of hardware errors (non-responding peripherals,
bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).
The STWD100 watchdog timer has an input, WDI, and an output, WDO. The input is used to
clear the internal watchdog timer periodically within the specified timeout period, twd. While
the system is operating correctly, it periodically toggles the watchdog input, WDI. If the
system fails, the watchdog timer is not reset, a system alert is generated and the watchdog
output, WDO, is asserted.
The STWD100 circuit also has an enable pin, EN, which can enable or disable the
watchdog functionality. The EN pin is connected to the internal pull-down resistor. The
device is enabled if the EN pin is left floating.
Figure 1. SOT23-5 and SC70-5 (SOT323-5) package connections
Table 2. SOT23-5 and SC70-5 (SOT323-5) pin description
Pin number Name Description WDO Watchdog output GND Ground EN Enable pin WDI Watchdog input
5VCC Supply voltage
Description STWD100
6/25 DocID014134 Rev 8
Figure 2. Logic diagram
Note: WDO output is available in open drain or push-pull configuration.
Figure 3. Block diagram
Note: Positive pulse on enable pin EN longer than 1 μs resets the watchdog timer.
DocID014134 Rev 8 7/25
STWD100 Operation
2 Operation
The STWD100 device is used to detect an out-of-control MCU. The user has to ensure
watchdog reset within the watchdog timeout period, otherwise the watchdog output is
asserted and MCU is restarted. The STWD100 can be also enabled or disabled by the
chip enable pin.
2.1 Watchdog input (WDI)
The WDI input has to be toggled within the watchdog timeout period, tWD, otherwise the
watchdog output, WDO, is asserted. The internal watchdog timer, which counts the tWD
period, is cleared either: by a transition on watchdog output, WDO (see Figure 8 on page 12) or
2. by a pulse on enable pin, EN (see Figure 10 on page 14) or
3. by toggling WDI input (low-to-high on all versions and high-to-low on STWD100xW,
STWD100xX and STWD100xY only).
The pulses on WDI input with a duration of at least 1 μs are detected and glitches shorter
than 100 ns are ignored.
If WDI is permanently tied high or low and EN is tied low, the WDO toggles every 3.4 ms
(tWD) on STWD100xP and every tWD and tPW on STWD100xW, STWD100xX and
STWD100xY (see Figure 8 on page 12).
2.2 Watchdog output (WDO)
When the VCC exceeds the timer startup voltage VSTART after power-up, the internal
watchdog timer starts counting. If the timer is not cleared within the tWD, the WDO will go
low (see Figure 6).
After exceeding the tWD, the WDO is asserted for tPW on STWD100xW, STWD100xX and
STWD100xY regardless of possible WDI transitions (see Figure 9 on page 13). On
STWD100xP WDO is asserted for a minimum of 10 μs and a maximum of tWD after
exceeding the tWD period (see Figure 8 on page 12 and Figure 9 on page 13).
The STWD100 has an active low open drain or push-pull output. An external pull-up resistor
connected to any supply voltage up to 6 V is required in case of open drain WDO output
(see Figure 4). Select a resistor value large enough to register a logic low, and small enough
to register a logic high while supplying all input current and leakage paths connected to the
reset output line. A 10 k pull-up resistor is sufficient in most applications.
Operation STWD100
8/25 DocID014134 Rev 8
Figure 4. Open drain WDO output connection
2.3 Chip enable input (EN)
All states mentioned in Section 2.1: Watchdog input (WDI) and Section 2.2: Watchdog
output (WDO) are valid under the condition that EN is in logical low state.
The behavior of EN is common to all versions (i.e. STWD100xP , STWD100xW,
STWD100xX and STWD100xY).
If the EN goes high after power-up in less than tWD from the moment that VCC exceeds the
timer startup voltage, VSTART, the WDO will stay high for the same time period as EN, plus
tWD (see Figure 10 on page 14).
If the EN goes high anytime during normal operation, the WDO will go high as well, but the
minimum possible WDO pulse width is 10 μs (see Figure 10 on page 14).
The pulses on the EN pin with a duration of at least 1 μs are detected and glitches shorter
than 100 ns are ignored.
2.4 Applications information
Interfacing to microprocessors with bidirectional reset pins
Microprocessors with bidirectional reset pins can contend with the STWD100 watchdog
output, WDO. For example, if the WDO output is driven high and the micro wants to pull it
low, signal contention will result. To prevent this from occurring, connect a 4.7 k resistor
between the WDO output and the microprocessors reset I/O as in Figure 5.
DocID014134 Rev 8 9/25
STWD100 Operation
Figure 5. Interfacing to microprocessors with bidirectional reset I/O
Watchdog timing STWD100
10/25 DocID014134 Rev 8
3 Watchdog timing
Figure 6. Power-up
DocID014134 Rev 8 11/25
STWD100 Watchdog timing
Figure 7. Normal triggering
Watchdog timing STWD100
12/25 DocID014134 Rev 8
Figure 8. Timeout without re-trigger
DocID014134 Rev 8 13/25
STWD100 Watchdog timing
Figure 9. Trigger after timeout
