STW5094T ,18 BIT 8KHZ TO 48KHZ LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODECBLOCK DIAGRAMNOTE: This diagram shows the functionality of the device and of some register bits but ..
STW5094T ,18 BIT 8KHZ TO 48KHZ LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODECGENERAL DESCRIPTIONIn addition to the Stereo Audio DAC andSTw5094 is a low power Stereo Audio DAC d ..
STW5098 , Dual low power asynchronous stereo audio Codec with integrated power amplifiers
STW50N10 ,OLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-INSTW50N10N - CHANNEL ENHANCEMENT MODEPOWER MOS TRANSISTORTYPE V R IDSS DS(on) DSTW50N10 100 V < 0.03 ..
STW50NB20 ,NSTW50NB20®N - CHANNEL 200V - 0.047Ω - 50A - TO-247PowerMESH™ MOSFETTYPE V R IDSS DS(on) DSTW50NB2 ..
STW52NK25Z ,N-CHANNEL 250V-0.033Ohm-52A TO-247 Zener-Protected SuperMESH™MOSFETFeatures Figure 1: PackageTYPE V R I PwDSS DS(on) DSTW52NK25Z 250 V < 0.045 Ω 52 A 300 W
STW5094-STW5094T
18 BIT 8KHZ TO 48KHZ LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODEC
1/37
STw5094November 2003
FEATURES:
Complete STEREO AUDIO DAC and FILTERS
including: 18 BIT DIGITAL TO ANALOG CONVERTERS. LINEAR PHASE DIGITAL FILTERS. ACTIVE LINEAR PHASE SMOOTHING
FILTER. 30Ω LOAD STEREO HEADPHONES
DRIVERS, 8Ω LOAD MONO LOUDSPEAKER
DRIVER FOR GROUP LISTENING.
Stereo Audio DAC Features: MULTIBIT ΣΔ MODULATOR WITH DATA
WEIGHTED AVERAGING DAC. 92 dB DYNAMIC RANGE, 0.01% THD OVER 30Ω LOAD PERFORMANCE. SUPPORTS ALL THE MPEG 1 & 2 SAMPLING
FREQUENCIES AND THE EXTENSION TO
MPEG 2.5: 8, 11.025, 12, 16, 22.05, 24, 32,
44.1, 48 kHz. TONES FROM TONE GENERATOR CAN BE
INJECTED IN THE AUDIO PATHS.
Stereo Headphones and Loudspeaker/Earpiece
Power Amplifiers features and Stereo Input for
FM Radio Features: 20kHz BANDWIDTH STEREO HEADPHONES
OUTPUTS. DRIVING CAPABILITY: 20mW
(TYP. 0.1% T.H.D) OVER 30Ω WITH 40 dB
RANGE PROGRAMMABLE GAIN. BALANCED EARPIECE⁄ LOUDSPEAKER
OUTPUT. DRIVING CAPABILITY: 190mW
(TYP. 0.1% T.H.D) OVER 8Ω WITH 30dB
RANGE PROGRAMMABLE GAIN. ANALOG STEREO INPUT FOR FM RADIO
WITH 38 dB RANGE PROGRAMMABLE GAIN.
Complete CODEC and FILTER system including: 14 BIT LINEAR ADC AND DAC. 8 BIT COMPANDED ADC AND DAC A-LAW
OR μ-LAW. TRANSMIT AND RECEIVE DIGITAL
BAND-PASS FILTERS. ACTIVE ANTIALIAS AND SMOOTHING
FILTERS. 8Ω LOAD EARPIECE/LOUDSPEAKER
DRIVER, 30Ω LOAD AUXILIARY DRIVER.
Voice CODEC Features: SUPPORT BOTH 8kHz AND 16kHz
SAMPLING RATE. ONE MICROPHONE BIASING OUTPUT. REMOTE CONTROL FUNCTION. ONE LINE INPUT AND TWO SWITCHABLE
MICROPHONE AMPLIFIER INPUTS. 42.5dB
RANGE PROGRAMMABLE GAIN. TRANSIENT SUPRESSION DURING POWER
UP AND POWER DOWN. INTERNAL PROGRAMMABLE SIDETONE
CIRCUIT. INTERNAL RING, TONE AND DTMF
GENERATOR. PROGRAMMABLE PWM BUZZER DRIVER.
General Features: SINGLE 2.7V to 3.3V SUPPLY. EXTENDED TEMPERATURE RANGE
OPERATION (*) -40°C to 85°C. 1 μW STANDBY POWER (TYP. AT 2.7V). 13 mW OPERATING POWER IN AUDIO
LISTENING MODE (TYP. AT 2.7V). 11 mW OPERATING POWER IN VOICE
CODEC MODE (TYP. AT 2.7V). 1.8V TO 3.3V CMOS COMPATIBLE DIGITAL
INTERFACES. PROGRAMMABLE PCM INTERFACE.I2 C COMPATIBLE CONTROL INTERFACE. PROGRAMMABLE SERIAL AUDIO DATA
INPUT INTERFACE (I2 S AND OTHER
FORMATS).
(*) Functionality guaranteed in the range - 40°C to +85°C; Timing
and Electrical Specifications are guaranteed in the range - 30°C
to +85°C.
18 BIT 8kHz TO 48kHz LOW POWER STEREO AUDIO DAC
WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODEC
STw5094 2/37
APPLICATIONS: CDMA,GSM,DCS1800,PCS1900,JDC DIGITAL
CELLULAR TELEPHONES WITH MP3 AND
FM RADIO STEREO LISTENING FUNCTIONS. PORTABLE DEVICES WITH A STEREO
DIGITAL AUDIO SOURCE AND FM RADIO
LISTENING FUNCTION.
GENERAL DESCRIPTIONSTw5094 is a low power Stereo Audio DAC device
with Headphones Amplifiers for high quality MP3 and
FM radio listening. The STw5094 includes also an
high performance low power combined PCM
CODEC⁄ FILTER tailored to implement the audio
front-end functions required by low voltage
low power consumption digital cellular terminals with
added MP3 and FM radio listening.
STw5094 offers a number of programmable functions
accessed through an I2 C-bus compatible interface.
The STw5094 Stereo Audio DAC section is suited for
MP3, or any other audio stereo source, listening. It
supports all the MP3 rates from 8kHz to 48kHz. The
audio data serial interface is I2 S compatible and can
be programmed to handle 16 to 24 bit word length in-
put data. The internal D to A converters work with 18
bit input resolution.
The Stereo Headphones drivers can also be used for
FM Radio listening via an auxiliary stereo analog in-
put. A Loudspeaker driver can also be used for mono-
phonic group listening.
The STw5094 Voice Codec section can be configured
either as a 14-bit linear or as an 8-bit companded
PCM coder. The Frame Synchronism frequency of
the Voice Codec can be either the standard 8kHz val-
ue or the extended 16kHz one.
In addition to the Stereo Audio DAC and
CODEC⁄ FILTER functions, STw5094 includes a
Tone⁄ Ring⁄ DTMF generator that can be used both
in Audio Listening mode and in Voice Codec mode, a
sidetone generation, a buzzer driver output and a re-
mote control function tailored to handle an external
on-hook off-hook button.
STw5094 Voice Codec fulfills and exceeds D3⁄D4
and CCITT recommendations and ETSI requirements
for digital handset terminals. The Stereo Audio DAC
part fulfills and exceeds the requirements for MP3
quality and FM radio quality listening. Main applica-
tions include digital mobile phones, as cellular and
cordless phones, with added low-power high-quality
MP3 and⁄ or FM radio listening features, or any bat-
tery powered equipment that requires Stereo Audio
DAC with Headphones drivers operating at low single
supply voltage.
PIN CONNECTIONS (Top view)
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STw5094
FUNCTIONAL BLOCK DIAGRAMNOTE: This diagram shows the functionality of the device and of some register bits but it does not necessarily reflect the exact
STw5094 4/37
PIN FUNCTION
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STw5094
Type definitions: AI - Analog input, AO - Analog Output, DI - Digital Input, DO - Digital output, DOT - Digital Output Tristate,
DIO - Digital Input Output Open Drain, P - Power Supply or Ground.
PIN FUNCTION (continued)
STw5094 6/37
FUNCTIONAL DESCRIPTIONI DEVICE MODES
STw5094 can work in 4 different modes, selected by bits MD in Control Register 18 (CR18). Depending on the
mode different data interfaces, clock inputs, and internal blocks are selected. A built-in power consumption
management function keeps in power down the blocks that are not needed by the selected operating mode. In
all the modes the Output Drivers can be activated in all the combinations allowed by bits OS in CR6 (in case of
stereo input and LSP⁄
N driver selected the Left channel is sent to this driver, while in case of voice input and
HPL+
HPR drivers selected the same signal is sent to both drivers).I.1 Audio Mode:
In Audio mode the path from the I2S I⁄ F to the output drivers is active to allow the Stereo Audio DAC function.
The I2S I⁄ F is active while the PCM I⁄ F is inactive.
The master clock of the device is OCK. The OCK frequency must be 256 times the sampling frequency for the
MPEG1 and MPEG2 sampling frequencies and 512 times for the MPEG2.5 sampling frequencies.
The sampling frequency (LRCK frequency) can be selected with bits LAY and AFS in REG6.
Since the OCK clock is used directly in all the Audio blocks, its jitter and spectral properties must be adequate
to the desired Audio quality.
The Tone⁄ Ring⁄ DTMF generator can be activated if needed. The FM preamplifiers are in power down.
I.2 Voice Mode:
In Voice mode the TX path from microphone or line input to DX and the RX path from DR to the output drivers
are active to allow the PCM CODEC function. The PCM I⁄ F is active while the I2S I⁄ F is inactive.
The master clock of the device is MCLK, the frequency of the clock can be selected with bits F in CR0.
The FM preamplifiers are in power down.
I.3 Tone Only Mode:
In Tone Only mode the path from the Tone generator to the output Drivers and to the Buzzer is active to allow
Tones or Ringer listening only. Both I2S I⁄ F and PCM I⁄ F are inactive, as all the Audio and Voice converters
functions.
The master clock of the device can be selected to be AUXCLK, MCLK or OCK (bits CFM in CR18).
The Tone⁄ Ring⁄ DTMF generator can be activated if needed. The FM preamplifiers are in power down.
I.4 FM Mode:
In FM mode the path from FML and FMR analog inputs to the output Drivers is active to allow FM Stereo Radio
listening. Both I2S I⁄ F and PCM I⁄ F are inactive, as all the Audio and Voice converters functions.
The master clock of the device can be selected to be AUXCLK, MCLK or OCK (bits CFM in CR18).
The Tone⁄ Ring⁄ DTMF generator is in power down.
II DEVICE OPERATION
II.1 Power on initialization and Software Reset:
When power is first applied, power on reset circuitry initializes STw5094 and puts it into the power down state.
All the Registers are initialized as indicated in the Control Register description section. All the functions are
disabled.
The registers can be initialized also writing bit SRS (software reset) in CR18.
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STw5094II.2 Power up⁄
down control: It is recommended that all programmable functions (excluding the gain controls) are set while the device is
powered down. Power state control can then be included in the last programming instruction (the power up bit
PU is located in the last address register (CR18) so that the multi-byte mode of the control interface can beeasily used to program all the required functions before power up).
When a power up command is given, all the circuits needed for the selected mode are activated (in Voice mode
the DX output will remain in the high impedance state until the second FS pulse after power up arrives). A built-in
power consumption management function keeps in power down the blocks that are not needed by the selected
operating mode.
II.3 Power down state:
Following a period of activity, power down state may be reentered by writing 0 in bit PU in CR18. All the Control
Registers remain in their current state and can be changed by I2 C control interface.
In addition to the power down instruction, the detection of absence of the current Master Clock (no transition
detected) automatically puts the device in power down state without setting bit PU. If transitions on the master
clock are detected the device is put again in power up.
II.4 Voice Transmit section:
This section is active in Voice Mode. Voice Transmit analog preamplifier gain is designed in two stages to
enable gains up to 42.5 dB. Stage 1 provides a selectable 0 or 20 dB gain via bit PG in CR4. Stage 2 is a
programmable gain amplifier which provides from 0 to 22.5 dB of additional gain in 1.5dB step. It can be
programmed with bits TXA in CR4. Two differential microphone inputs (MIC1P⁄
N, MIC2P⁄
N) and one singleended line input (MIC3) are provided. The line input MIC3 can only be used with preamplifier gain set to 0dB in
both stages. The microphone input or Transmit Mute is selected with bits MS in CR4. In the Mute case, the
analog transmit signal is grounded. A separate MBIAS output can be used to bias a microphone (bit MB in CR4).
An active anti-alias filter then precedes the single bit ΣΔ analog to digital converter that is followed by an 8th
order IIR digital TX channel filter. The TX channel filter is band-pass if the FS frequency is 8kHz and low-pass
if the FS frequency is 16kHz (bit VFS in CR0). A precision on chip voltage reference ensures accurate and highly
stable transmission levels. Any offset voltage arising in the analog blocks is cancelled by an internal autozero
circuit. Voice data is sent to the PCM I⁄ F to be serially sent to DX output.
II.5 Voice Receive section:
This section is active in Voice Mode. Voice Data coming from PCM I⁄ F DR pin is sent to the 8th order digital
IIR RX channel filter. The filter can be selected to be band-pass or low-pass, with bit HPB in CR5, when FS
frequency is 8kHz, while it is always low-pass when FS frequency is 16kHz. The filter is followed by a ΣΔ digital
to analog converter and a 3rd order switched-capacitor reconstruction filter. The Sidetone can be summed to
the received signal (bit SI in CR5) and its amplitude can be programmed with bits SA in CR5.
II.6 Stereo Audio DAC section:
This section is active in Audio Mode. The Left and Right Audio samples coming from the I2 S Interface are
interpolated with an FIR filter in order to feed the oversampled multi-bit ΣΔ modulator, the digital to analog
converter is followed by a 3rd order switched-capacitor reconstruction filter.
II.7 Output Drivers section:
There are 3 Analog Output Drivers. The LSP⁄
N differential driver delivers 190mW typical power with 0.1%T.H.D. (140mW minimum undistorted) on a 8Ω earpiece⁄ loudspeaker (piezoceramic loads up to 50nF can also
be driven, with a series resistor), it has a 30dB range gain control (bits LSA in CR7). The 2 single ended drivers
(HPL and HPR) deliver 20mW typical power with 0.1% T.H.D. (16.5mW minimum undistorted) on 30Ω stereo
headphones, they have a 40dB range gain control (CR8 for HPL and CR9 for HPR). It is possible to put all the
drivers in power-down, enable the
LSP⁄
N one, enable the
HPL one or enable
HPL and HPR together
STw5094
8/37
programming bits OS in CR6. These settings are not dependent from the selected operative Mode. If HPL and
HPR are enabled together in Voice Mode or Tone Only Mode the same signal is sent to both Drivers. The active
Drivers can be muted (keeping them in power-up state) using bit MUT in CR7. At power-up or after a change in
OS bits the outputs are muted for 10 ms to avoid unwanted noise. The transient suppression filter is used to
avoid clicks when the gain value is changed.
II.8 Tone Generator:
The Tone Generator can be activated (writing CR12) in all the Stw5094 operating modes except FM mode. In
Voice and Audio modes the tones are summed to the signal. It is possible to generate 1 or 2 summed waveforms
(either sinusoidal or square wave), their frequencies can be set in CR13 for the first one (f1) and in CR14 for the
second one (f2) accordingly to the values listed in Table 1. The amplitude of the generated waveform can be
regulated in CR12 over a 33dB range. When both f1 and f2 are selected the amplitude of f1 and f2 are lowered
by 5dB and 7dB respectively with respect to the amplitude of a single waveform. In this way the amplitude of
the summed waveforms does not overload and there is a 2dB difference between f1 and f2 amplitude as
required for DTMF generation. The Tone Generator output can be sent to the Voice Transmit section (in Voice
Mode), to the Power amplifiers, possibly mixed with audio or voice, (in all the modes except FM mode) and to
the buzzer output BZ (in all the modes except FM mode).
II.9 Buzzer Output:
The output BZ is intended to drive a Buzzer, via an external BJT, with a squarewave pulse width modulated
(PWM) signal. The frequency of the signal is stored in CR13 (see Table1 for frequency values). For some
applications it is also possible to multiply this PWM signal with a squarewave signal having a frequency stored
in CR14. The duty cycle of the buzzer output can be varied in CR15 in order to change the buzzer volume.
Maximum load for BZ is 5kΩ and 50pF.
II.10 Voice Data Interface (PCM I⁄ F):
The PCM I⁄ F is used to exchange the Voice data in both TX and RX direction, it can be programmed for linear
format data or companded A-law or μ-law format (see Fig.1, 2 and 3).
Frame Sync input FS determines the beginning of frame. It may have any duration from a single cycle of MCLK
to a squarewave. Three different relationships may be established between the Frame Sync input and the first
time slot of the frame by setting bits DM in CR1. In non delayed normal and reverse data mode (long frame
timing) the first time slot starts at the rising edge of FS. In delayed data mode (short frame sync timing) FS input
must be high for at least a half cycle of MCLK before the frame start.
When linear code is selected (bit CM =0 in CR0) the MSB is transmitted and received first, the word length is
16 bit. When companded code is selected (bit CM =1 in CR0) a time slot assignment may be used in all timing
modes (bit TS in CR1), that allows connection to one of the two B1 and B2 voice data channels. Two data
formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles that immediately follow the
rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles that immediately follow time slot B1. In
Format 2, time slot B1 is identical to Format 1 while time slot B2 appears two bit slots after time slot B1. This
two bits space is left available for insertion of the D channel data. Data format is selected by bit FF in CR0.
Bit EN in CR1 enables or disables data transfer on DX and DR.
Outside the selected time slot DX is in the high impedance condition. During the selected time slot the DX output
and the DR input are synchronized as follow:
-If delayed or non-delayed modes are selected the transmit voice data is sent to DX output on the rising edges
of MCLK and receive voice data is read at DR input on the falling edges of MCLK.
-If non-delayed reverse mode is selected the transmit voice data register is sent to DX output on the falling
edges of MCLK and receive voice data is read at DR input on the rising edges of MCLK.
When 16kHz Frame Sync frequency is selected (bit VFS in CR0) the RX and TX filters are both low-pass and
their cutoff frequencies are doubled.
It is possible to access the B channel data when companded A-law or μ-law formats are used (bits MX and MR
in CR1). A byte written into CR3 will be sent to DX output in place of the transmit channel PCM data. A byte
written in CR2 will be sent to the receive path. The current byte received on DR input can be read in CR2.
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STw5094
II.11 Audio Data Interface (I2S I⁄ F):
The I2S I⁄ F is used to receive the Left and Right channel Audio data (see Fig. 4 and 5). The interface is I2S
compatible and can be configured in other different modes writing CR16.
When the I2S I⁄ F is active (Audio mode) the Master Clock of the device is OCK. The frequency of OCK is 256
times the sampling frequency (LRCK frequency) when the sampling frequency is between 16kHz and 48kHz
(LAY(1) =0 in CR6), and 512 times when the sampling frequency is between 8kHz and 12kHz (LAY= 10 in
CR6). The polarity of OCK can be selected.
SCK frequency is 32 times the LRCK one in case of 16bit Data word and 64 times in case of 18bit to 24bit Data
word. Left channel data are always received first, the polarity of LRCK can be selected.
The first 35 Data frames after power up are discarded while the interpolation filters data memory is cleared.
II.12 Control Interface (I2C I⁄ F):
The I2C I⁄ F is used to program the device by writing and reading the control registers (see Fig 6 and 7). The
interface is I2C bus compatible, being the STw5094 a Slave device. SDA is the bidirectional open-drain data pin
and SCL is the input clock pin. The Device Address is E2 hex. for writing and E3 hex. for reading.
The interface has an internal address register that keeps the current address of the control register to be read
or written. At each write access of the interface the address register is loaded with the data of the register
address field. The value in the address register is increased after each data byte read or write. It is possible to
access the interface in 2 modes: single-byte mode in which the address and data of a single register are
specified, and multi-byte mode in which the address of the first register to be written or read is specified and all
the following bytes exchanged are the data of successive address registers starting from the one specified (in
multi-byte mode the internal address counter restart from register 0 after the last register 18). Using the
multi-byte mode it is possible to write or read all the registers with a single access to the device on the I2C bus.
The Control interface can be used both in power-up and power-down state.
II.13 Master Clock in FM mode and Tone Only modes:
In FM mode and in Tone Only mode the Master Clock of the device can be selected to be AUXCLK, MCLK or
OCK writing bits CFM in CR18. The Auxiliary clock AUXCLK can be used when the Audio mode clock OCK
and the Voice mode clock MCLK are not available. AUXCLK and MCLK frequency selection is done with bits
F in CR0.
II.14 REMOCON function:
The REMOCON (Remote Control) function can be used to detect the status of an headset button. The
REMOCON function is enabled by setting bit REN in CR17. If enabled, this function is active also when the
STw5094 is in power-down state.
A High level at REMIN input is detected as a non pressed button, while a low level is detected as a pressed
button. The "Pressed Button" information can be treated in 2 ways depending on bit RLM in CR17:
- if RLM= 0 (Transparent mode) the information at REMIN is seen at REMOUT after a debounce time of 50ms
maximum;
- if RLM= 1 (Latched Mode) the information stored in bit RDL in CR17 is seen at REMOUT. RDL is set after a
debounce time of 50ms maximum when a low level at REMIN is detected. RDL is reset with power on
initialization and can also be reset writing 0 in bit RDL.
The REMOUT output polarity can be inverted setting bit ROI in CR17: the pressed button information is
presented at REMOUT output as a logic 1 if bit ROI= 0. If ROI= 1 the polarity is inverted.
STw5094
10/37
III PROGRAMMABLE REGISTERS
Control Register CR0 Functions (Address: 0x00)
(1): significant in companded mode only
*: state at power on initialization
Control Register CR1 Functions (Address: 0x01)
(1) significant in companded mode only
*: state at power on initialization
X: reserved: write 0
11/37
STw5094
Control Register CR2 Functions (Address: 0x02)
(1) Significant in companded mode only.
Control Register CR3 Functions (Address: 0x03)
(1) Significant in companded mode only.
Control Register CR4 Functions (Address: 0x04)
*: state at power on initialization
(1) When the single ended line input MIC3 is selected, microphone gain must be set to 0dB (PG=1, TXA=0000).
Control Register CR5 Functions (Address: 0x05)
*: state at power on initialization
X: reserved: write 0
(1): Valid only when Voice Data Fs=8kHz (VFS=0). When Voice data Fs=16kHz (VFS=1) The High Pass Filter is always disabled.
STw5094
12/37
Control Register CR6 Functions (Address: 0x06)
(1): OCK frequency must be 256 times Audio Data Fs frequency.
(2): OCK frequency must be 512 times Audio Data Fs frequency.
*: state at power on initialization
X: reserved: write 0
Control Register CR7 Functions (Address: 0x07)
*: state at power on initialization
X: reserved: write 0
Control Register CR8 Functions (Address: 0x08)
*: state at power on initialization
X: reserved: write 0
13/37
STw5094
Control Register CR9 Functions (Address: 0x09)
*: state at power on initialization
X: write 0
Control Register CR10 Functions (Address: 0x0A)
*: state at power on initialization
X: reserved: write 0
Control Register CR11 Functions (Address: 0x0B)
*: state at power on initialization
X: reserved: write 0
STw5094
14/37
Control Register CR12 Functions (Address: 0x0C)
*: state at power on initialization
X: reserved write 0
Control Register CR13 Functions (Address: 0x0D)
Control Register CR14 Functions (Address: 0x0E)
Control Register CR15 Functions (Address: 0x0F)
* state at power on initialization
15/37
STw5094
Control Register CR16 Functions (Address: 0x10)
(1) significant in 18⁄20⁄ 24 bit per word mode only
(2) Left Channel data is always received first.
(3) First bit delay, in 18⁄20⁄ 24 bit per word mode, is applied only if word is left justified.
*: state at power on initialization
Control Register CR17 Functions (Address: 0x11)
*: state at power on initialization
X: reserved write 0
STw5094
16/37
Control Register CR18 Functions (Address: 0x12)
*: state at power on initialization
X: reserved write 0
17/37
STw5094
Table 1. Tone Generator frequency versus CR13 CR14 register value correspondence table
STw5094
18/37
TIMING DIAGRAM
Figure 1. Voice Interface (PCM I/F) Non Delayed Data Timing Mode (*)
Figure 2. Voice Interface (PCM I/F) Delayed Data Timing Mode (*)
(*) In the case of companded code the timing is applied to 8 bits instead of 16 bits.
19/37
STw5094
TIMING DIAGRAM
Figure 3. Voice Interface (PCM I/F) Non Delayed Reverse Data Timing Mode (*)
(*) In the case of companded code the timing is applied to 8 bits instead of 16 bits.
Figure 4. Audio Interface (I2 S I/F) Timing
