STW5093CYLT ,2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-ENDapplications (see STw5093 Power Supply Notes).11 MIC2+ Second Positive high impedance input to tran ..
STW5094 ,18 BIT 8kHz TO 48kHz LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODECFeatures: (TYP. 0.1% T.H.D) OVER 30Ω WITH 40 dB ■ SINGLE 2.7V to 3.3V SUPPLY.RANGE PROGRAMMABLE GAI ..
STW5094ADT/LF , 18-bit Low Power Asynchronous Stereo Audio DAC with Integrated Power Amplifiers and Voice Codec
STW5094ADT/LF , 18-bit Low Power Asynchronous Stereo Audio DAC with Integrated Power Amplifiers and Voice Codec
STW5094T ,18 BIT 8KHZ TO 48KHZ LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODECBLOCK DIAGRAMNOTE: This diagram shows the functionality of the device and of some register bits but ..
STW5094T ,18 BIT 8KHZ TO 48KHZ LOW POWER STEREO AUDIO DAC WITH INTEGRATED POWER AMPLIFIERS AND VOICE CODECGENERAL DESCRIPTIONIn addition to the Stereo Audio DAC andSTw5094 is a low power Stereo Audio DAC d ..
T7NS1D4-48 , Miniature Power PCB Relay T7N / T7N-WG
T7NV5D4-24-WG-A , Miniature Power PCB Relay
T8003 , COMMON MODE CHOKE CATALOG Suited for LAN and Telecom Applications
T8008 , COMMON MODE CHOKE CATALOG Suited for LAN and Telecom Applications
T810 ,8A TRIACSABSOLUTE MAXIMUM RATINGSSymbol Parameter Value Unit²I RMS on-state current (full sine wave)T(RMS) D ..
T810-600B ,8A TRIACSFEATURES:A2A2 A2Symbol Value UnitGI8AT(RMS) A1A1A2A2A1GGV /V600 and 800 VDRM RRM2DPAK D PAK(T8-B) ( ..
STW5093CYL-STW5093CYLT
2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
1/34
STw5093March 2004
FEATURES:
Complete CODEC and FILTER system including: 14 BIT LINEAR ANALOG TO DIGITAL AND
DIGITAL TO ANALOG CONVERTERS. 8 BIT COMPANDED ANALOG TO DIGITAL
AND DIGITAL TO ANALOG CONVERTERS A-
LAW OR µ-LAW. TRANSMIT AND RECEIVE BAND-PASS
FILTERS ACTIVE ANTIALIAS NOISE FILTER.
Phone Features: ONE MICROPHONE BIASING OUTPUT REMOTE CONTROL (REMOCON) FUNCTION THREE SWITCHABLE MICROPHONE
AMPLIFIER INPUTS. GAIN
PROGRAMMABLE:0 . . 42.5 dB AMPLIFIER,
1.5 dB STEPS (+ MUTE). EARPIECE AUDIO OUTPUT. ATTENUATION
PROGRAMMABLE: 0 . . 30 dB, 2 dB STEPS. EXTERNAL AUDIO OUTPUT. ATTENUATION
PROGRAMMABLE: 0 . . 30 dB, 2 dB STEPS. DRIVING CAPABILITY: 140mW OVER 8Ω TRANSIENT SUPRESSION SIGNAL DURING
POWER ON AND DURING AMPLIFIER
SWITCHING. INTERNAL PROGRAMMABLE SIDETONE
CIRCUIT. ATTENUATION PROGRAMMABLE:
16 dB RANGE, 1 dB STEP. INTERNAL RING, TONE AND DTMF
GENERATOR, SINEWAVE OR
SQUAREWAVE WAVEFORMS.
ATTENUATION PROGRAMMABLE: 27dB
RANGE, 3dB STEP. THREE FREQUENCY
RANGES:
a) 3.9Hz . . . . 996Hz, 3.9Hz STEP
b) 7.8Hz . . . . 1992Hz, 7.8Hz STEP
c) 15.6Hz . . . . 3984Hz, 15.6Hz STEP PROGRAMMABLE PULSE WIDTH
MODULATED BUZZER DRIVER OUTPUT.
General Features: SINGLE 2.7V to 3.3V SUPPLY EXTENDED TEMPERATURE RANGE
OPERATION (*) -40°C to 85°C. 1.0µW STANDBY POWER (TYP. AT 2.7V). 13mW OPERATING POWER (TYP. AT 2.7V).
1.8V TO 3.3V CMOS COMPATIBLE DIGITAL
INTERFACES. PROGRAMMABLE PCM AND CONTROL
INTERFACE MICROWIRE COMPATIBLE.
APPLICATIONS: GSM/DCS1800/PCS1900/JDC DIGITAL
CELLULAR TELEPHONES. CDMA CELLULAR TELEPHONES. DECT/CT2/PHS DIGITAL CORDLESS
TELEPHONES. BATTERY OPERATED AUDIO FRONT-ENDS
FOR DSPs.
(*) Functionality guaranteed in the range - 40°C to +85°C; Timing
and Electrical Specifications are guaranteed in the range - 30°C
to +85°C.
GENERAL DESCRIPTIONSTw5093 is a high performance low power combined
PCM CODEC/FILTER device tailored to implement the
audio front-end functions required by low voltage/low
power consumption digital cellular terminals. STw5093
offers a number of programmable functions accessed
through a serial control channel that easily interfaces to
any classical microcontroller. The PCM interface sup-
ports both non-delayed (normal and reverse) and de-
layed frame synchronization modes.
STw5093 can be configurated either as a 14-bit lin-
ear or as an 8-bit companded PCM coder.
Additionally to the CODEC/FILTER function, STw5093
includes a Tone/Ring/DTMF generator, a sidetone gen-
eration, and a buzzer driver output.STw5093 fulfills and
exceeds D3/D4 and CCITT recommendations and ETSI
requirements for digital handset terminals.
Main applications include digital mobile phones, as
cellular and cordless phones, or any battery powered
equipment that requires audio codecs operating at
low single supply voltages.
2.7V SUPPLY 14-BIT LINEAR CODEC WITH
HIGH-PERFORMANCE AUDIO FRONT-END
STw5093
PIN CONNECTIONS (Top view)
BLOCK DIAGRAM
3/34
STW5093
PIN FUNCTION
STw5093
PIN FUNCTION (continued)
5/34
STW5093
1.0 FUNCTIONAL DESCRIPTION
1.1 DEVICE OPERATION
1.1.1 Power on initialization:When power is first applied, power on reset circuitry initializes STw5093 and puts it into the power down state.
Gain Control Registers for the various programmable gain amplifiers and programmable switches are initialized
as indicated in the Control Register description section. All CODEC functions are disabled.
The desired selection for all programmable functions may be intialized prior to a power up command using the
MICROWIRE control channel.
Note: after register programming, a subsequent activation of the internal Power on Reset can be detected by
programming to 1 the DO bit in the CR1 register; this sets to the logic level 0 the LO output. If an internal Power
on Reset occurs, LO automatically switches to logic level 1.
1.1.2 Power up/down control:Following power-on initialization, power up and power down control may be accomplished by writing any of the
control instructions listed in Table 1 into STw5093 with "P" bit set to 0 for power up or 1 for power down.
Normally, it is recommended that all programmable functions be initially programmed while the device is pow-
ered down. Power state control can then be included with the last programming instruction or in a separate sin-
gle byte instruction.
Any of the programmable registers may also be modified while STw5093 is powered up or down by setting "P"
bit as indicated. When power up or down control is entered as a single byte instruction, bit 1 must be set to a 0.
When a power up command is given, all de-activated circuits are activated, but output DX will remain in the high
impedance state until the second Fs pulse after power up.
1.1.3 Power down state:Following a period of activity, power down state may be reentered by writing a power down instruction.
Control Registers remain in their current state and can be changed by MICROWIRE control interface.
In addition to the power down instruction, detection of loss MCLK (no transition detected) automatically enters
the device in "reset" power down state with DX output in the high impedance state.
1.1.4 Transmit section:Transmit analog interface is designed in two stages to enable gains up to 42.5 dB to be realized. Stage 1 is a
low noise differential amplifier providing a selectable 0 or 20 dB gain via bit 1 (PG) of register CR4. A microphone
may be capacitevely connected to MIC1+, MIC1- inputs, while the MIC2+ MIC2Ä and MIC3+ MIC3- inputs may
be used to capacitively connect a second microphone or a third microphone respectively or an auxiliary audio
circuit. MIC1 or MIC2 or MC3 or transmit mute is selected with bits 6 and 7 of register CR4.
In the mute case, the analog transmit signal is grounded and the sidetone path is also disabled. Following the
first stage is a programmable gain amplifier which provides from 0 to 22.5 dB of additional gain in 1.5dB step.
The total transmit gain should be adjusted so that, at reference point A, see Block Diagram description, the in-
ternal 0 dBm0 voltage is 0.49 Vrms (overload level is 0.7 Vrms). Second stage amplifier gain can be pro-
grammed with bits 4 to 7 of CR5.
An active RC prefilter then precedes the 8th order band pass switched capacitor filter. A/D converter can be
either a 14-bit linear (bit CM = 0 in register CR0) or can have a compressing characteristics (bit CM = 1 in reg-
ister CR0) according to CCITT A or MU255 coding laws. A precision on chip voltage reference ensures accurate
and highly stable transmission levels.
Any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an internal au-
tozero circuit.
Each encode cycle begins immediatly at the beginning of the selected Transmit time slot. The total signal delay
referenced to the start of the time slot is approximatively 195 µs (due to the transmit filter) plus 125 µs (due to
encoding delay), which totals 320 µs. Voice data is shifted out on DX during the selected time slot on the trans-
STw5093 mit rising edges of MCLK in delayed or non-delayed normal mode or on the falling edges of MCLK in non-de-
layed reverse mode.A separate MBIAS output can be used to bias a microphone (bit MB = 1 in register CR10)
1.1.5 Receive section:Voice Data is shifted into the decoder's Receive voice data Register via the DR pin during the selected time slot
on the falling edges of MCLK in delayed or non-delayed normal mode or on the rising edges of MCLK in non-
delayed reverse mode.
The decoder consists of either a 14-bit linear or an expanding DAC with A or MU255 law decoding characteristic.
Following the Decoder is a 3400 Hz 8th order band-pass switched capacitor filter with integral Sin X/X correction
for the 8 kHz sample and hold.
0 dBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A transcient suppress-
ing circuitry ensure interference noise suppression at power up.
The analog speech signal output can be routedeither to earpiece (VFR output) or to an extra analog output (VLr+,
VLr- outputs) by setting bits OE1, OE2, and SE (4, 3, and 0 of CR4).
Total signal delay is approximatively 190µs (filter plus decoding delay) plus 62.5µs (1/2 frame) which gives ap-
proximatively 252µs.
Output VFR is intended to directly drive an earpiece. Preceding the outputs is a programmable attenuation am-
plifier, which must be set by writing to bits 4 to 7 in register CR6. Attenuations in the range 0 to -30 dB relative
to the maximum level in 2 dB step can be programmed. The input of this programmable amplifier is the sum of
several signals which can be selected by writing to register CR4.:
- Receive speech signal which has been decoded and filtered,
- Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 of register CR7),
- Sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register CR5
VFr is capable of driving output power levels up to 16.5mW into a 30Ω load impedance capacitively connected
between VFr+ and GND. Piezoceramic receivers up to 50nF can also be driven.
Differential outputs VLr+,VLr- are intended to directly drive an extra output. Preceding the outputs is a program-
mable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuations in the range
0 to -30 dB relative to the maximum level in 2.0 dB step can be programmed. The input of this programmable
amplifier can be the sum of signals which can be selected by writing to register CR4:
- Receive speech signal which has been decoded and filtered,
- Internally generated tone signal, (Tone amplitude is programmed with bits 4 to 7 of register CR7),
- Sidetone signal, the amplitude of which is programmed with bits 0 to 3 of register CR5.
VLr+ and VLr- outputs are capable of driving output power level up to140mW into differentially connected load
impedance of 8 Ω. Piezoceramic receivers up to 50nF can also be driven.
BUZZER OUTPUT:
Single ended output BZ is intended to drive a buzzer, via an external BJT, with a squarewave pulse width mod-
ulated (PWM) signal the frequency of which is stored into register CR8.
For some applications it is also possible to amplitude modulate this PWM signal with a squarewave signal hav-
ing a frequency stored in register CR9.
Maximum load for BZ is 5kΩ and 50pF.
1.1.6 Digital Interface (Fig. 1)FS Frame Sync input determines the beginning of frame. It may have any duration from a single cycle of MCLK
to a squarewave. Three different relationships may be established between the Frame Sync input and the first
time slot of frame by setting bits DM1 and DM0 in register CR1. In non delayed data mode (long frame timing)
the first time slot begins nominally coincident with the rising edge of FS. Alternative is to use delayed data mode
(short frame sync timing) in which FS input must be high at least a half cycle of MCLK earlier the frame beginning
In the case of linear code (bit CM = 0 in register CR0) the MSB is the first bit that is transmitted and received.
7/34
STW5093In the case of companded code only (bit CM = 1 in register CR0) a time slot assignment circuit on chip may be
used with all timing modes, allowing connection to one of the two B1 and B2 voice data channels.
Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles following immedi-
ately the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles following immediately time slot
B1.
In Format 2, time slot B1 is identical to Format 1. Time slot B2 appears two bit slots after time slot B1. This two
bits space is left available for insertion of the D channel data.
Data format is selected by bit FF (2) in register CR0. Time slot B1 or B2 is selected by bit TS (1) in Control Reg-
ister CR1.
Bit EN (2) in control register CR1 enables or disables the voice data transfer on DX and DR as appropriate. Dur-
ing the assigned time slot, DX output shifts data out from the voice data register on the rising edges of MCLK
in the case of delayed and non-delayed normal modes or on the falling edges of MCLK in the case of non-de-
layed reverse mode. Serial voice data is shifted into DR input during the same time slot on the falling edges of
MCLK in the case of delayed and non-delayed normal modes or on the rising edges of MCLK in the case of non-
delayed reverse mode.
DX is in the high impedance Tristate condition when in the non selected time slots.
Figure 1. Digital Interface Format (significant only for companded code)
1.1.7 Control Interface:Control information or data is written into or read-back from STw5093 via the serial control port consisting of
control clock CCLK, serial data input CI and output CO, and Chip Select input, CS-. All control instructions re-
quire 2 bytes as listed in Table 1, with the exception of a single byte power-up/down command.
To shift control data into STw5093, CCLK must be pulsed high 8 times while CS- is low. Data on CI input is
shifted into the serial input register on the rising edge of each CCLK pulse. After all data is shifted in, the content
of the input shift register is decoded, and may indicate that a 2nd byte of control data will follow. This second
byte may either be defined by a second byte-wide CS- pulse or may follow the first contiguously, i.e. it is not
mandatory for CS- to return high in between the first and second control bytes. At the end of the 2nd control
byte, data is loaded into the appropriate programmable register. CS- must return high at the end of the 2nd byte.
STw5093 To read-back status information from STw5093, the first byte of the appropriate instruction is strobed in during
the first CS- pulse, as defined in Table 1. CS- must be set low for a further 8 CCLK cycles, during which data is
shifted out of the CO pin on the falling edges of CCLK.
When CS- is high, CO pin is in the high impedance Tri-state, enabling CO pins of several devices to be multi-
plexed together.
Thus, to summarise, 2 byte READ and WRITE instructions may use either two 8-bit wide CS- pulses or a single
16 bit wide CS- pulse.
1.1.8 Control channel access to PCM interface:It is possible to access the B channel previously selected in Register CR1 in the case of companded code only.
A byte written into Control Register CR3 will be automatically transmitted from DX output in the following frame
in place of the transmit PCM data.
A byte written into Control Register CR2 will beautomatically sent through the receive path to the Receive am-
plifiers.
In order to implement a continuous data flow from the Control MICROWIRE interface to a B channel, it is nec-
essary to send the control byte on each PCM frame.
A current byte received on DR input can be read in the register CR2. In order to implement a continuous data
flow from a B channel to MICROWIRE interface, it is necessary to read register CR2 at each PCM frame.
1.1.9 AUXCLK usage:The Auxiliary clock AUXCLK is only used to keep active the tone and buzzer generation functions to the Ear-
piece or to the Extra amplifier outputs when the Master Clock MCLK is not available, and there is no voice ac-
tivity both in transmit and receive channels. When AUXCLK is selected, the PCM digital interface is inactive (DX
in tristate and DR is not read). The selection between AUXCLK and MCLK is done by bit SLC in register CR1The
input frequency of AUXCLK is selected via bits F1 and F0 of register CR0 as for the MCLK signal.
1.1.10REMOCON function:The REMOCON (Remote Control) function can be used to detect the status of an headset button.
The REMOCON function is enabled by setting bit REN (7 of CR10). If enabled, this function is active also when
the STw5093 is in Power-down state.
At REMIN input an high level is detected as a non pressed button, while a low level is detected as a pressed
button.
The "Pressed Button" information can be treated in 2 ways depending on bit RLM (6 of CR10):
if RLM = 0 (Transparent mode) the information at REMIN is seen at REMOUT after a debounce time
of 50ms maximum.
if RLM = 1 (Latched Mode) the information stored in bit RDL (4 of CR10) is seen at REMOUT.When a
low level at REMIN is detected RDL is set after a debounce time of 50ms maximum.RDL is reset at
power on reset and can also be reset writing CR10.
The REMOUT output polarity can be inverted setting bit ROI (5 of CR10):the pressed button information is pre-
sented at REMOUT output as a logic 1 if bit ROI = 0. If ROI = 1 the polarity is inverted.
2.0 PROGRAMMABLE FUNCTIONSThe programmable functions are configured by writing to a number of registers using a 2-byte write cycle. Most
of these registers can also be read-back for verification. Byte one is always register address, while byte two is
Data. Table 1 lists the register set and their respective adresses.
9/34
STW5093
Table 1. Programmable Register IntructionsNotes:1. bit 7 of the address byte and data byte is always the first bit clocked into or out from: CI and CO pins when MICROWIRE serial
port is enabled.
X = reserved: write 0 "P" bit is Power up/down Control bit. P = 1 Means Power Down.Bit 1 indicates, if set, the presence of a second byte. Bit 2 is write/read select bit. Registers CR12, CR13, and CR14 are not accessible.
STw5093
Table 2. Control Register CR0 Functions*: state at power on initialization
(1): significant in companded mode only
Table 3. Control Register CR1 Functions state at power on initialization
(1): significant in companded mode only reserved: write 0
11/34
STW5093
Table 4. Control Register CR2 Functions(1) Significant in companded mode only.
Table 5. Control Registers CR3 Functions(1) Significant in companded mode only.
Table 6. Control Register CR4 Functions state at power on initialization
STw5093
Table 7. Control Register CR5 Functions*: state at power on initialization
Table 8. Control Register CR6 Functions*: state at power on initialization
Table 9. Control Register CR7 Functions state at power on initialization
(2): value provided if f1 or f2 is selected alone.if f1 and f2 are selected in the summed mode, f1=0.89 Vpp while f2=0.7 Vpp. reserved: write 0
13/34
STW5093
Table 10. Control Register CR8 Functions
Table 11. Control Register CR9 Functions
Table 12. Control Register CR10 Functions(*) Default values inserted into the Register at Power On.
Table 13. Control Register CR11 Functions* state at power on initialization
STw5093
CONTROL REGISTER CR0First byte of a READ or a WRITE instruction to Control Register CR0 is as shown in TABLE 1.
Second byte is as shown in TABLE 2.
Master Clock / Auxiliary Clock Frequency SelectionA master clock must be provided to STw5093 to activate all the functions. In the case MCLK is absent, AUXCLK
can be provide to STw5093 for activating tone or buzzer functions only.
MCLK or AUXCLK frequency can be either 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz..
Bit F1 (7) and F0 (6) must be set during initialization to select the correct internal divider.Default value is 512
kHz. Any clock different from the default one must be selected prior a Power-Up instruction.
Coding Law SelectionBits MA (4) and IA (3) permit selection of Mu-255 law or A law coding with or without even bit inversion if com-
panded code (bit CM = 1) is selected. Bits MA(4) and IA(3) permit selection of 2-complement, 1-complement or
sign and magnitude if linear code (bit CM = 0) is selected.
Coding SelectionBit CM (5) permits selection either of linear coding (14-bit) or companded coding (8-bit). Default value is linear
coding.
Digital Interface format (1)Bit FF(2) = 0 selects digital interface in Format 1 where B1 and B2 channel are consecutive. FF=1 selects For-
mat 2 where B1 and B2 channel are separated by two bits. (See digital interface format section.)
56+8 selection (1)Bit 'B7' (1) selects capability for STw5093 to take into account only the seven most significant bits of the PCM
data byte selected.
When 'B7' is set, the LSB bit on DR is ignored and LSB bit on DX is high impedance. This function allows con-
nection of an external "in band" data generator directly connected on the Digital Interface.
Digital loopbackDigital loopback mode is entered by setting DL bit(0) equal 1.
In Digital Loopback mode, data written into Receive PCM Data Register from the selected received time-slot is
read-back from that Register in the selected transmit time-slot on DX.
No PCM decoding or encoding takes place in this mode. Transmit and Receive amplifier stages are muted.
CONTROL REGISTER CR1First byte of a READ or a WRITE instruction to Control Register CR1 is as shown in TABLE 1. Second byte is
as shown in TABLE 3.
Digital Interface TimingBit DM1(7) = 0 selects digital interface in delayed timing mode, while DM1 = 1 and DM0 = 0 selects non-delayed
normal data timing mode, and DM1 = 1 and DM0 = 1 selects non-delayed reverse data timing mode.Default is
delayed data timing.
(1) Significant in companded mode only
15/34
STW5093
Latch output controlBit DO controls directly logical status of latch output LO: ie, a "ZERO" written in bit DO puts the output LO at
logical 1, while a "ONE" written in bit DO sets the output LO to zero.
Microwire access to B channel on receive path (1)Bit MR (4) selects access from MICROWIRE Register CR2 to Receive path. When bit MR is set high, data writ-
ten to register CR2 is decoded each frame, sent to the receive path and data input at DR is ignored.
In the other direction, current PCM data input received at DR can be read from register CR2 each frame.
Microwire access to B channel on transmit path (1)Bit MX (3) selects access from MICROWIRE write only Register CR3 to DX output. When bit MX is set high,
data written to CR3 is output at DX every frame and the output of PCM encoder is ignored.
MSB is always the first PCM bit shifted in or out of: STw5093.
Transmit/Receive enabling/disablingBit 'EN' (2) enables or disables voice data transfer on DX and DR pins. When disabled, PCM data from DR is
not decoded and PCM time-slots are high impedance on DX. Default value is disabled.
B-channel selection (1)Bit TS(1) permits selection between B1 or B2 channels. Default value is B1 channel.
Clock SelectionBit SLC(0) allows the selection between MCLK and AUXCLK. Default value is MCLK.
CONTROL REGISTER CR2(1)Data sent to receive path or data received from DR input. Refer to bit MR(4) in "Control Register CR1" para-
graph.
CONTROL REGISTER CR3 (1)DX data transmitted. Refer to bit MX(3) in "Control Register CR1" paragraph.
CONTROL REGISTER CR4First byte of a READ or a WRITE instruction to Control Register CR4 is as shown in TABLE 1. Second byte is
as shown in TABLE 6.
(1) Significant in companded mode only
STw5093
Transmit Input SelectionMIC1 or MIC2 or MIC3 or transmit mute can be selected with bits 6 and 7 (VS and TE).
Transmit gain can be adjusted within a 22.5 dB range in 1.5 dB step with Register CR5.
Sidetone SelectionBit "SI" (5) enables or disables Sidetone circuitry. When enabled, sidetone gain can be adjusted with Register
(CR5). When Transmit path is disabled, sidetone circuit is also disabled.
Output Driver SelectionBits OE1(4) and OE2(3) provide the selection among the earpiece output or the extra amplifier output or both
outputs muted.OE1 = 1 and OE2 = 1 is not allowed.
Ring/Tone signal selectionBit RTE (2) provide select capability to connect on-chip Ring/Tone generator either to an extra amplifier input
or to earpiece amplifier input.
Receiver High Pass Filter SelectionBit HPB(1) provides the selection of the receiver high pass filter cutoff frequency.
PCM receive data selectionBits "SE" (0) provide select capability to connect received speech signal either to an extra amplifier input or to
earpiece amplifier input.
CONTROL REGISTER CR5First byte of a READ or a WRITE instuction to Control Register CR5 is as shown in TABLE 1. Second byte is
as shown in TABLE 7.
Transmit gain selectionTransmit amplifier can be programmed for a gain from 0dB to 22.5dB in 1.5dB step with bits 4 to 7.
0 dBmO level at the output of the transmit amplifier (A reference point) is 0.492 Vrms (overload voltage is 0.707
Vrms).
Sidetone attenuation selectionTransmit signal picked up after the switched capacitor low pass filter may be fed back into both Receive ampli-
fiers.
Attenuation of the signal at the output of the sidetone attenuator can be programmed from Ä12.5dB to -27.5dB
relative to reference point A in 1 dB step with bits 0 to 3.
CONTROL REGISTER CR6First byte of a READ or a WRITE instruction to Control Register CR6 is as shown in TABLE 1. Second byte is
as shown in TABLE 8.
17/34
STW5093
Earpiece amplifier gain selection:Earpiece Receive gain can be programmed in 2 dB step from 0 dB to -30 dB relative to the maximum with bits
4 to 7.
0 dBmO voltage at the output of the amplifier on pin VFr is 0.9825 Vrms when 0dB gain is selected down to
30.925 Vrms when -30dB gain is selected.
Extra amplifier gain selection:Extra Receive amplifier gain can be programmed in 2 dB step from 0 dB to -30 dB relative to the maximum with
bits 0 to 3.
0 dBmO voltage on the output of the amplifier on pins VLr+ and VLr- 1.965 Vrms when 0 dB gain is selected down
to 61.85 mVrms when -30 dB gain is selected.
CONTROL REGISTER CR7:First byte of a READ or a WRITE instruction to Control Register CR7 is as shown in TABLE 1. Second byte is
as shown in TABLE 9.
Tone/Ring amplifier gain selectionOutput level of Ring/Tone generator, before attenuation by programmable attenuator is 1.6 Vpk-pk when f1 gen-
erator is selected alone or summed with the f2 generator and 1.26 Vpk-pk when f2 generator is selected alone.
Selected output level can be attenuated down to -27 dB by programmable attenutator by setting bits 4 to 7.
Frequency mode selectionBits 'F1' (3) and 'F2' (2) permit selection of f1 and/or f2 frequency generator according to TABLE 9.
When f1 (or f2) is selected, output of the Ring/Tone is a squarewave (or a sinewave) signal at the frequency
selected in the CR8 (or CR9) Register.
When f1 and f2 are selected in summed mode, output of the Ring/Tone generator is a signal where f1 and f2
frequency are summed.
In order to meet DTMF specifications, f2 output level is attenuated by 2dB relative to the f1 output level.
Frequency temporization must be controlled by the microcontroller.
Waveform selectionBit 'SN' (1) selects waveform of the output of the Ring/Tone generator. Sinewave or squarewave signal can be
selected.
DTMF selectionBit DE (0) permits connection of Ring/Tone/DTMF generator on the Transmit Data path instead of the Transmit
Amplifier output. Earpiece or extra receive output feed-back may be provided by sidetone circuitry by setting bit
SI or directly by setting bit RTE in Register CR4. Loudspeaker feed-back may be provided directly by setting bit
RTL in Register CR4.
CONTROL REGISTERS CR8 AND CR9First byte of a READ or a WRITE instruction to Control Register CR8 or CR9 is as shown in TABLE 1. Second
byte is respectively as shown in TABLE 10 and 11.
If "standard frequency tone range" is selected, Tone or Ring signal frequency value is defined by the formula:
f1 = CR8 / 0.128 Hz
