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STV9420-STV9421
MULTISYNC ON-SCREEN DISPLAY FOR MONITOR
STV9420
STV9421MULTISYNC ON-SCREEN DISPLA Y FOR MONITOR
October 1995 CMOS SINGLE CHIP OSD FOR MONITOR. BUILT IN 1 KBYTE RAM HOLDING :
- PAGES’ DESCRIPTORS
- CHARACTER CODES
- USER DEFINABLE CHARACTERS. 128 ALPHANUMERIC CHARACTERS OR
GRAPHIC SYMBOLS IN INTERNAL ROM
(12 x 18 DOT MATRIX). UP TO 26 USER DEFINABLE CHARACTERS. INTERNAL HORIZONTAL PLL (15 TO 120kHz). PROGRAMMABLE VERTICAL HEIGHT OF
CHARACTER WITH A SLICE INTERPOLATOR
TO MEET MULTI-SYNCH REQUIREMENTS. PROGRAMMABLE VERTICAL AND HORI-
ZONTAL POSITIONING. FLEXIBLE SCREEN DESCRIPTION. CHARACTER BY CHARACTER COLOR SE-
LECTION (UP TO 8 DIFFERENT COLORS). PROGRAMMABLE BACKGROUND (COLOR,
TRANSPARENT OR WITH SHADOWING). CHARACTER BLINKING. 2-WIRES ASYNCHRONOUS SERIAL MCU
INTERFACE (I2 C PROTOCOL). 4 x 8 BITS PWM DAC OUTPUTS ON THE
STV9421. SINGLE POSITIVE 5V SUPPLY
DESCRIPTIONThe STV9420/21 is an ON SCREEN DISPLAY for
monitor. It is built as a slave peripheral connected
to a host MCU via a serial I2 C bus. It includes a
display memory, controls all the display attributes
and generates pixels from the data read in its on
chip memory. The line PLL and a special slice
interpolator allow to have a display aspect which
does not depend on the line and frame frequencies.2 C interface allows MCU to make transparent in-
ternal access to prepare the next pages during the
display of the current page. Toggle from one page
to another by programming only one register.
4 x 8 bits PWM DAC are available (STV9421) to
provide DC voltage control to other peripherals.
The STV9420/21 provides the user an easy to use
and cost effective solution to display alphanumeric
or graphic information on monitor screen.
1/16
PIN CONNECTIONS
PIN DESCRIPTION
STV9420 - STV94212/16
BLOCK DIAGRAMSSTV9420
STV9421
STV9420 - STV94213/16
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD = 5V, VSS = 0V, TA = 0 to 70°C, FXTAL = 8 to 15MHz, TEST = 0 V, unless otherwise specified)
SUPPLY
INPUTS
OUTPUTS
2.5-5 10-4 10-3 10-2 10-1
(V),VOL OHV
Figure 1 : Typical R, G, B Outputs Characteristics
STV9420 - STV94214/16
TIMINGSOSCILATOR INPUT : XTI (see Figure 2)
RESET
R, G, B, FBLK (CLOAD = 30pF)2 C INTERFACE : SDA AND SCL (see Figure 3)
Note 1 : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes
characterization on batches comming from corners of our processes and also temperature characterization.
Figure 2
Figure 3
STV9420 - STV94215/16
FUNCTIONAL DESCRIPTIONThe STV9420/21 display processor operation is
controlled by a host MCU via the I2 C interface. It is
fully programmable through 8 internal read/write
registers (12 for STV9421) and performs all the
display functions by generating pixels from data
stored in its internal memory. After the page down-
loading from the MCU, the STV9420/21 refreshes
screen by its built in processor, without any MCU
control (access).In addition, the host MCU has a
direct access to the on chip 1Kbytes RAM during
the display of the current page to make any update
of its contents.
With the STV9420/21, a page displayed on the
screen is made of several strips which can be of 2
types : spacing or character and which are de-
scribed by a table of descriptors and character
codes in RAM. Several pages can be downloaded
at the same time in the RAM and the choice of the
current display page is made by programming the
CONTROL register.
I - Serial InterfaceThe 2-wires serial interface is an I2 C interface. To
be connected to the I2 C bus, a device must own its
slave address ; the slave address of the
STV9420/21 is BA (in hexadecimal).
I.1 - Data Transfer in Write ModeThe host MCU can write data into the STV9420/21
registers or RAM.
To write data into the STV9420/21, after a start, the
MCU must send (Figure 3) : First, the I2 C address slave byte with a low level
for the R/W bit, The two bytes of the internal address where the
MCU wants to write data(s), The successive bytes of data(s).
All bytes are sent MS bit first and the write data
transfer is closed by a stop.
I.2 - Data Transfer in Read ModeThe host MCU can read data from the STV9420/21
registers, RAM or ROM.
To read data from the STV9420/21 (Figure 4), the
MCU must send 2 different I2 C sequences.
The first one is made of I2 C slave address byte with
R/W bit at low level and the 2 internal address
bytes.
The second one is made of I2 C slave address byte
with R/W bit at high level and all the successive
data bytes read at successive addresses starting
from the initial address given by the first sequence.
Figure 4 : STV9420/I2 C Read Operation
Figure 3 : STV9420/I2 C Write Operation
STV9420 - STV94216/16
FUNCTIONAL DESCRIPTION (continued)
I.3 - Addressing SpaceSTV9420/21 registers, RAM and ROM are mapped
in a 16Kbytes addressing space. The mapping is
the following :
0000 Descriptors character
codes user definable
characters
03FF
0400
1FFF
2000
32FF
3300
3FFF
3FF0
3FFF
I.4 - Register SetLINE DURATION
3FF0
LD[5:0]: LINE DURATION (number of character
period, 1LSB = 12 pixel periods).
HORIZONTAL DELAY
3FF1
DD[7:0]: HORIZONTAL DISPLAY DELAY from
the H-SYNC reference falling edge to
the 1st pixel position of the character
strips.
Unit = 3 pixel periods.
CHARACTERS HEIGHT
3FF2
CH[5:0]: HEIGHT of the character strips in scan
lines. For each scan line, the number of
the slice which is displayed is given by :
SLICE-NUMBER =
round
SCAN−LINE−NUMBER x 18
CH[5:0]
SCAN-LINE-NUMBER = Number of the current scan
line of the strip.
DISPLAY CONTROL
3FF3
OSD : ON/OFF (if 0, R, G, B and FBLK are 0).
FBK : Fast blanking control : 1 : FBLK = 1, forcing black where
these is no display,
= 0 : FBLK is active only during
character display.
FL[1:0]: Flashing mode : 00 : No flashing. The character
attribute is ignored, 01 : 1/1 flashing (a duty cycle = 50%), 10 : 1/3 flashing, 11 : 3/1 flashing.
P[8:6] : Address of the 1st descriptor of the
current displayed pages.
P[13:9] and P[5:0] = 0 ; up to 8 different
pages can be stored in the RAM.
LOCKING CONDITION TIME CONSTANT
3FF4 : Free Running ; if = 1 PLL is disabled and
the pixel frequency keeps its last value.
AS[2:0]: Phase constant during locking
conditions.
BS[2:0]: Frequency constant during locking
conditions.
CAPTURE PROCESS TIME CONSTANT
3FF5
AF[2:0]: Phase constant during the capture
process.
BF[2:0]: Frequency constant during the capture
process.
INITIAL PIXEL PERIOD
3FF6
PP[7:0] :V alue to initialize the pixel period of the
PLL.
FREQUENCY MULTIPLIER
3FF7
FM[3:0]: Frequency multiplier of the crystal
frequency to reach the high frequency
used by the PLL to derive the pixel
frequency.
STV9420 - STV94217/16
FUNCTIONAL DESCRIPTION (continued)The last fourth registers described below are only
available with the STV9421 :
PULSE WIDTH MODULATOR 1
3FF8
V1[7:0]: Digital value of the 1st PWM D to A
converter (Pin1).
PULSE WIDTH MODULATOR 2
3FF9
V2[7:0]: Digital value of the 2d PWM DAC (Pin11).
PULSE WIDTH MODULATOR 3
3FFA
V3[7:0]: Digital value of the 3rd PWM DAC
(Pin20).
PULSE WIDTH MODULATOR 4
3FFB
V4[7:0]: Digital value of the 4th PWM DAC
(Pin10).
Note : * is power on reset value.
II - DescriptorsSPACING
MSB
LSB
SL[7:0]: The number of the scan lines of the
spacing strip (1 to 255).
CHARACTER
MSB
LSB
C[9:0]: The address of the first character code of
the strip (even). : Display enable : DE = 0, R = G = B = 0 and FBLK = FBK
(display control register) on whole strip, DE = 1, display of the characters. : Zoom, ZY = 1 all the scan lines are
repeated once.
III - Code FormatMSB
LSB: Flashing attribute (the flashing mode is
defined in the DISPLAY CONTROL register).
SET : The set CHARACTER NUMBER If SET = 0 : ROM character, If SET = 1 : If CHARACTER NUMBER is 0 to
25, a user redefinable character
(UDC) located in RAM at the
addr ess equal to : 38 x
CHARACTER NUMBER, If CHARACTER NUMBER is 26 to
63, space character, If CHARACTER NUMBER >63,
end of line. , GF , BF: Foreground color.
BK[3:0] : Background : If BK3 = 0, BK[2:0] = background
color R, G and B, If BK3 = 1, shadowing : BK2 : vertival shadowing, BK1 : horizontal shadowing.
(if BK2 = BK1 = 0, the background is
transparent).
IV - Clock and TimingThe whole timing is derived from the XTALIN and
the SYNCHRO (horizontal and vertival) input fre-
quencies. The XTALIN input frequency can be an
external clock or a crystal signal thanks to
XTALIN/XTALOUT pins. The value of this fre-
quency can be chosen between 8 and 15MHz, it is
available on the CKOUT pin and is used by the PLL
to generate a pixel clock locked on the horizontal
synchro input signal.
IV.1 - Horizontal TimingThe number of pixel periods is given by the LINE
DURATION register and is equal to :
[LD[5:0] + 1 ] x 12
(LD[5:0] : value of the LINE DURATION register).
This value allows to choose the horizontal size of
the characters.
The horizontal left margin is given by the HORI-
ZONTAL DELAY register and is equal to :
[DD[7:0] + 8] x 3 x tPXCK
(DD[7:0] : value of the DISPLAY DELAY register
and TPXCK : pixel period).
This value allows to choose the horizontal position
of the characters on the screen. The value of
DD[7:0] must be equal or greater than 4 (the mini-
mum value of the horizontal delay is 36 x tPXCK = 3
character periods). The length of the active area,
where R, G, B are different from 0, depends on the
number of characters of the strips.
STV9420 - STV94218/16
