STV9212 ,VIDEO PROCESSOR FOR CRT MONITORS WITH PICTUREBOOSTElectrical Characteristics ......274.6 I²C-Bus Interface Timing Requirements ...27Chapter 5 Solde ..
STV9302 ,VERTICAL DEFLECTION PROCESSOR FOR MONITOR/TV. 2 APP/60V WITH FLYBACK GENERATORABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitVOLTAGEV Supply Voltage (pin 2) - Note 1 and Not ..
STV9302A ,VERTICAL DEFLECTION BOOSTER FOR 2 APP MONITOR/TV APPLICATIONS WITH 70 V FLYBACK GENERATORElectrical Characteristics(V = 32 V, T = 25°C, unless otherwise specified)S AMB Symbol Parameter Te ..
STV9306 ,BUS CONTROLLED VERTICAL DEFLECTION SYSTEM WITH EAST/WEST CORRECTION OUTPUT CIRCUITapplications. It integrates both the verticaldeflection and E/W correction circuitries neces-sary i ..
STV9306B ,BUS-CONTROLLED VERTICAL DEFLECTION SYSTEM WITH EAST/WEST CORRECTION OUTPUT CIRCUITElectrical CharacteristicsoV = 24 V, R = 0.5 Ω, Normal mode, T = 25 C, unless otherwise specified.S ..
STV9325 ,40V; vertical deflection booster for 2.5-app TV/monitor applications with 70-V flyback generatorElectrical Characteristics(V = 34 V, T = 25°C, unless otherwise specified)S AMB Symbol Parameter Te ..
T7503 , T7503 Dual PCM Codec with Filters
T77V1D10-12 , Potter & Brumfield
T77V1D10-12 , Potter & Brumfield
T7933 ,ROW DRIVER LSI FOR A DOT MATRIX GRAPHIC LCDT7933 TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T7933 ROW DRIVER LSI FOR A DOT M ..
T7NS1D4-48 , Miniature Power PCB Relay T7N / T7N-WG
T7NV5D4-24-WG-A , Miniature Power PCB Relay
STV9212
VIDEO PROCESSOR FOR CRT MONITORS WITH PICTUREBOOST
STV9212Video Processor for CRT Monitors with PictureBooST
Main Features General I²C-Bus Controlled Supports AC- and DC-coupled applications 5V to 8V Power Supply Matches to virtually any video amplifier
PictureBooST PictureBooST insertion input Full-screen PictureBooST via I²C-bus Context-sensitive Picture Enhancement
Video Clamping Input and Output Video Clamp Sync Pulse Polarity Auto-rectification Clamp Pulse Generation timed either by sync
or video blanking pulse
Video Processing Contrast Adjustment with excellent channel
matching Gain stages for control of white Two DC-mode cut-off ranges Output DC offset control Automatic Beam Limiter (ABL) Video Insertion Pulse (VIP), 2 levels Amplifier Control (Blanking and Stand-by)
OSD Insertion with Contrast Control Control Output Amplifier Standby and Blanking Control 3 DAC for control of DC Restore Amplifier or
Brightness in DC-coupled system
General DescriptionThe STV9212 is an I²C-bus controlled color video
processor designed for standard CRT monitor
applications. It can drive systems where cathodes
are either AC- or DC-coupled to the amplifier
outputs. The three video channels provide contrast
and white balance separate gain adjustments as
well as one-per-channel DC cut-off control and
common DC offset control functions. On top of
these usual controls, it features context-sensitive
picture enhancement circuitry to support the
PictureBooST function that enhances the
appearance of still pictures and moving video.
In AC coupling applications, the device can pilot
three cathode DC restore channels dedicated to set
CRT cut-off bias voltages and to control brightness
through cathodes.
The RGB video outputs have a class A architecture
and directly drive the amplifier channels without
unnecessarily consuming current. Bandwidth
limitation I²C-bus adjustments can contribute to
keeping the application EMI under control.
OSD (On-Screen Display) graphics are inserted by
means of a Fast Blanking signal. Independent OSD
contrast control facilitates adaptation to various
OSD generators and provides system flexibility.
The STV9212 is perfectly compatible with other ST
components for CRT video boards, such as video
amplifiers and OSD generators.
STV9212 able of Contents
Chapter 1 STV9212 Pin Allocation and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.1 Pinout ..................................................................................................................................4
1.2 Pin Descriptions ..................................................................................................................4
Chapter 2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.1 Video RGB Input Clamp .......................................................................................................6
2.2 Video Blanking .....................................................................................................................8
2.3 Contrast Control Stage and Automatic Beam Limiter ..........................................................9
2.4 PictureBooST .....................................................................................................................10
2.5 OSD Insertion .....................................................................................................................11
2.6 Drive Stage ........................................................................................................................11
2.7 Video Insertion Pulse .........................................................................................................12
2.8 Output Stage ......................................................................................................................12
2.9 Output Infra-black Level, Cut-off and Brightness ...............................................................15
2.10 Signal Waveforms ..............................................................................................................18
2.11 Miscellaneous ....................................................................................................................18
Chapter 3 I²C-Bus Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203.1 I²C-bus Register Descriptions ............................................................................................21
Chapter 4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244.1 Absolute Maximum Ratings ...............................................................................................24
4.2 Thermal Data .....................................................................................................................24
4.3 Static Electrical Characteristics ..........................................................................................24
4.4 Dynamic Electrical Characteristics .....................................................................................25
4.5 I²C-Bus Electrical Characteristics .......................................................................................27
4.6 I²C-Bus Interface Timing Requirements ...........................................................................27
Chapter 5 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Chapter 6 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Chapter 7 Input/Output Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
STV9212
Chapter 8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
STV9212 Pin Allocation and Description STV9212 STV9212 Pin Allocation and Description
1.1 Pinout
1.2 Pin Descriptions
Figure 1: STV9212 Pinout
Table 1: STV9212 Pin Descriptions
STV9212 Functional Description Functional Description
The functional blocks are described in the order they act on the signal.
Figure 2: STV9212 Block Diagram
Functional Description STV9212
2.1 Video RGB Input ClampThe three RGB inputs have to be supplied with a video signal through coupling capacitors playing
the role of analog memories for internal video clamps. The input clamping level is approximately 0V.
The clamp is gated by the Input Clamp Pulse (ICP) that is internally generated from a signal on
either the HS or BLK pin. The selection is done via register 8 of the I²C-bus. For more information,
refer to Figure3: ICP , OCP and BLKI Generation and Table2: ICP Timing.
Provided with an automatic polarity rectification function, the HS input accepts horizontal
synchronization signals of either polarity. The device can select either the leading or trailing edge of
this signal to trigger the ICP generator.
The BLK input is followed by an inverter stage that can be enabled or by-passed via the I²C-bus.
This allows the use of a signal of either polarity, the control software taking care of the inverter
position according to the signal applied. The BLKI signal found behind this inverter stage also drives
the video blanking circuitry which requires a positive BLKI polarity for correct operation. Once bit
BLKPOL has correctly been uploaded to ensure a positive BLKI polarity, the ICP triggering edge
can be selected via control bit BCEDGE. A horizontal flyback pulse is generally expected to be
applied on the BLK input. As the edges of horizontal flyback pulse can fall into the active video
content (outside the video signal line blanking portion), the application must ensure that such an
edge is never selected for triggering the ICP.
The width of the internally generated ICP is controlled via the I²C-bus. The HS input can be used to
pass a clamping pulse, if available in the application, directly to clamping stages, without any
additional processing. In this case, the appropriate polarity (positive) is required. See Table2: ICP
Timing. The ICP timings triggered by the trailing edge of the BLK signal are not presented.
The Output Clamp Pulse (OCP) is described in Section 2.8: Output Stage.
Figure 3: ICP, OCP and BLKI Generation
STV9212 Functional Description
Table 2: ICP Timing
Figure 4: Video Input Clamp
Functional Description STV9212
2.2 Video BlankingThe three video channels are simultaneously blanked with the high level of either BLKI or FBLK
signals. BLKI is an internal signal drawn from the signal applied on the BLK pin (H-flyback) as
shown in Figure 3. The blanking consists in forcing a “black” level to the internal clamped video
signal.
BLK InputThe BLK input receives an H-flyback pulse that drives: the video blanking circuitry during scan line retrace, the output clamping stage.
A clipping circuit at the input allows the direct use of a high-voltage H-flyback pulse applied through
a serial resistor as shown in Figure 5. A logic-level signal is also accepted but the serial resistor
remains mandatory. In all cases, the value of this resistor must be such that the sinking and
sourcing currents are limited to 1mA and 100μA, respectively.
Permanent BlankingThe entire TV screen can be blanked for an unlimited amount of time using the software blanking
feature. Both bits SWBLK and TST1 must be set to 1. The three video outputs are forced to their
infra-black levels as shown in Figure 6. Infra-black levels are defined in Section 2.9.
Figure 5: BLK Input Pin
Figure 6: Software Blanking
STV9212 Functional DescriptionThe screen can also be blanked by permanently keeping the On-Screen Display FBLK input signal
at high level. In this case, only the video contents of the three video channels are replaced by “black
level” OSD content insertion (signals on pins OSD1 through OSD3 permanently at low level). Refer
to Section 2.5: OSD Insertion on page 11.
2.3 Contrast Control Stage and Automatic Beam LimiterThe contrast stages are simultaneously controlled on all three RGB channels with high attenuation
matching precision. Refer to electrical specifications for values. See Figure7: Contrast Control and
Table4: I²C-Bus Register Map.
The Automatic Beam Limiter (ABL) is an attenuator controlled through the ABL input, independent
of contrast stage attenuation. The operating range is about 2 V (from 3 V to 1 V). A typical
characteristic is shown in Figure 8. Refer to Section4: Electrical Specifications for specific values.
When not used, the ABL pin is to be connected to VCCA.
Figure 7: Contrast Control
Figure 8: ABL Characteristics
Functional Description STV9212
2.4 PictureBooSTThe PictureBooST function provides a picture enhancement effect for images with photographic
or moving video contents.
The function is activated whenever the level on pin PB is high (TTL) or the bit PBINS is at 1, if the
general PictureBooST enable bit PBGEN is at 1. By means of PB input signal toggling, the
function can take effect in a part of the screen, e.g. a window, or on the whole screen.
The picture enhancement is achieved through combination of three actions, as shown in Figure9: a content-sensitive peaking with slow restore (vivacity), a contrast addition, a brightness addition.
The vivacity amplitude depends on the slope height and steepness and on the status of bits
PBVIVAM[1:0]. The return to stabilized state is exponential with a time constant adjustable via bits
PBVIVTC[2:0]. Any undershoot below the video black level is clipped to a level close to black.
The PictureBooST brightness is a DC offset superimposed on the video signal in the boosted
zone. Its value is selected by bits PBBRIG[1:0]. The vivacity and PictureBooST brightness are
both enabled by bit PBVIVEN.
The PictureBooST contrast component evenly increases the video amplitude in the boosted zone.
Its value is controlled by bits PBCRST[1:0].
Refer to Section4: Electrical Specifications for values.
Figure 9: PictureBooST Action
STV9212 Functional Description
2.5 OSD InsertionThe On-Screen Display (OSD) is inserted with a high level on the FBLK input (TTL). The device
acts as follows: The three RGB video input signals (IN1, IN2, IN3) are internally blanked, i.e. put at the black
level. Binary levels (TTL) on inputs OSD1, OSD2 and OSD3, after processing in the OSD contrast
stage, are added to the corresponding blanked video channels.
In this way, the OSD contents replace the video contents where the FBLK input is high. See
Figure 2 and Figure 10.
The OSD is inserted after the PictureBooST block and before the Drive block. As a consequence,
OSD insertion overlaps all video contents, including the PictureBooST-ed zones. Color
temperature adjustments by means of the I²C-bus Drive registers act in the OSD insets.
The OSD contrast stage allows the adjustment of the level of OSD insets simultaneously on the
three OSD channels and independently of the video contrast adjustment. Refer to
Section4: Electrical Specifications for values.
2.6 Drive StageThe Drive stage is a set of three attenuators separately controlled via three I²C-bus registers,
DRIVE1, DRIVE2 and DRIVE3. It affects all signals, ordinary video, PictureBooST processed
video and OSD insets. It is designed to compensate for differences in gain of the three CRT
cathodes. See Figure 11 and for values, refer to Section4: Electrical Specifications.
Figure 10: OSD Insertion
Functional Description STV9212
2.7 Video Insertion PulseThe Video Insertion Pulse (VIP) creates an indent on the three video signals, timed with the positive
part of the BLKI signal. (See Section 2.2: Video Blanking on page 8). As its level is below the video
black level, it introduces a video “infra-black” level. The video infra-black level position versus
ground is then controlled in subsequent stages. In the absence of the blanking pulse on pin BLK,
the VIP is not inserted and the subsequent stages control the position of video black level.
Figure 12 shows the signal before and after insertion of the VIP. Two different VIP values are
programmable by bit VIP. Refer to Section4: Electrical Specifications for values.
2.8 Output StageThe output stage consists of an output clamp and a buffer. If a reduced output video amplitude and/
Figure 11: Drive Control
Figure 12: VIP Insertion
STV9212 Functional DescriptionEven at 8V of V CCP , care must be taken at device application level to ensure operation without
signal top limitation.
2.8.1 Output ClampThe DC position of video infra-black and video black levels at the video outputs must be fixed
regardless of video or OSD inset contents, especially in applications where the device’s output
infra-black level determines directly the infra-black level on the CRT cathodes (DC-coupled
applications). This fixing is achieved by means of a fully-integrated output clamp that brings the
output video infra-black level (video black level, in absence of the BLK pulse) to the level of a
variable reference (Vib ) as shown in Figure 13. The Vib is described in detail in Section 2.9 on
page 15. The clamp circuit is driven by the Output Clamp Pulse (OCP). For correct operation, this
pulse must entirely fall into the VIP pulse if this is present (clamp of infra-black level) or onto the
video black part (clamp of black level). In the former case, the OCP generator is to be triggered with
the leading edge of the BLK pulse, in the latter case it must copy the ICP pulse. Refer to Figure 3 for
the OCP generation block diagram. Table 3 shows possible OCP timings. Although possible, the
OCP timings, triggered by the BLK trailing edge, are not shown as they have no practical use.
2.8.2 Bandwidth ControlControlled via bits BW[3:0], the output stage can limit the rise and fall time of the output signal. The
optimum choice for this adjustment is highly application dependent. Refer to Section4: Electrical
Specifications for values and to Section6: Application Hints for practical advice.
2.8.3 Output BufferThe output buffer provides enough current so that external buffers are not required and the power
amplifier can interface directly to the device’s outputs.
Figure 13: Output Stage
Functional Description STV9212
Table 3: OCP Timing
STV9212 Functional Description
2.9 Output Infra-black Level, Cut-off and BrightnessThe schematic diagram of these functions is shown in Figure 14.
2.9.1 Output Infra-black LevelThe infra-black level of the video signal at the video outputs OUT1, OUT2 and OUT3 is positioned
to the Vib reference by the output clamp circuit, thus defining the Output infra-black level. If the
output clamp circuit is furnished with a correctly timed OCP (see corresponding sections), the
output infra-black level equals Vib. Vib is composed of a fixed DC voltage (V ibmin ), a variable DC
voltage (Vibof ) applied on all three channels and a per-channel variable DC voltage (Vibl (1,2,3)) as
shown in Figure 15. In AC-coupling mode (bit MOD = 1), the Vibl part is suppressed and the Vib is
therefore equal on all three channels, only varying with bits IBOF[5:0] acting on Vibof . This can be
used to match the device’s outputs to the input of the video amplifier used (biasing). In DC-coupling
mode (bit MOD = 0), Vibl (1,2,3) are separately set via bits IBL1[7:0], IBL2[7:0] and IBL3[7:0],
respectively. This serves to adjust the cut-off points of the three CRT cathodes. In this case, Vibof
can serve to pre-position the cut-off ranges in the factory adjustment procedure or/and to provide a
rough brightness control.
Figure 14: Cut-off and Brightness Control Block Diagram
Functional Description STV9212
2.9.2 Cut-off and Brightness Control OutputsOutputs CO1, CO2 and CO3 provide a DC voltage controlled via bits BRIG[7:0], IBLx[7:0],
IBLRG[7:0], BRIGRG[1:0] and MOD[7:0]. The principal of operation is shown in Figure 14.
When bit MOD is in position AC (= 1), the output voltage is a sum of the “brightness” VbriAC, “cut-off” iblAC and a fixed V COmin providing a bottom limitation. The brightness adjustment is equally
applied to all three CO1, CO2 and CO3 outputs. It varies depending on bits BRIG[7:0] and
BRIGRG[1:0], with bits BRIGRG[1:0] controlling the range of BRIG adjustment. The cut-off
adjustment is separate for each channel, having one I²C-bus field per channel: IBL1, IBL2 and IBL3.
The ratio between the brightness and cut-off ranges depends on the brightness range selection.
See Figure 16.
When bit MOD is in position DC (= 0), the output voltage on CO3 output is a sum of the “brightness” briDC and a fixed V COmin providing a pedestal. Outputs CO1 and CO2 are floating with internal
Figure 15: Output Infra-black Level
Figure 16: CO1, CO2 and CO3 Outputs while MOD = 1
STV9212 Functional Descriptionresistors of approximately 40 kΩ to ground. The V briDC varies with bits BRIG[7:0] and does not
depend on bits BRIGRG[1:0]. See Figure 17.
Figure 17: CO1, CO2 and CO3 Outputs while MOD = 0
