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STV7697B
SCAN DRIVER FOR PLASMA DISPLAY PANELS
STV7697BScan Driver for Plasma Display Panels
Main Features 64-output PDP Scan Driver 170V Absolute Maximum Rating 5V Supply for Logic -200/750 mA Peak Output Current 1 A Source / Sink Output Diode 64-bit Shift Register (8 MHz) Blank Control Complementary Output Control BCD Technology 100 Pin-TQFP Package
DescriptionThe STV7697B is a scan driver for plasma display
panels (PDP) implemented in ST’s proprietary BCD
(Bi-polar CMOS DMOS) technology. Using a 64-bit
cascadable 8-MHz shift register, it drives 64 high-
current and high-voltage outputs.
By connecting several STV7697B devices in series,
any vertical pixel definition can be performed. The
STV7697B is supplied with separate 160V power
output and 5 V logic supplies. All command inputs
are CMOS compatible.
The STV7697B package is a 100-pin TQFP.
STV7697B able of Contents
Chapter 1 Pin Allocation and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31.1 Pinout Diagrams ...............................................................................................................3
Chapter 2 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Chapter 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93.1 Absolute Maximum Ratings ................................................................................................9
3.2 Thermal Data ......................................................................................................................9
3.3 Supply Characteristics .......................................................................................................10
3.4 Power Output Characteristics ...........................................................................................10
3.5 SIN and SOUT Characteristics .........................................................................................11
3.6 Input (CLR, CLK, STB, BLK, POL, SIN/SOUT, and F/R) Characteristics .........................11
3.7 AC Timing Requirements ...................................................................................................11
3.8 AC Timing Characteristics ..................................................................................................12
Chapter 4 Input/Output Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Chapter 5 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Chapter 6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
STV7697B Pin Allocation and Descriptions Pin Allocation and Descriptions
1.1 Pinout Diagram
Figure 1: STV7697B (TQFP100)
Pin Allocation and Descriptions STV7697B
Table 1: Supply Pins
Table 2: Shift Register and Input Pins
STV7697B Pin Allocation and Descriptions
Table 3: Power Output Pins
Pin Allocation and Descriptions STV7697B
Table 4: Miscellaneous Pins
STV7697B Circuit Description Circuit DescriptionThe STV7697B includes all the necessary logic and power circuits to drive the rows of electrodes of
a plasma display panel (PDP). The state of the displayed line is loaded into the shift register. Data
is shifted at each low to high transition of the (CLK) shift clock. After 64 shifts, the first bit presented
at the serial input (SIN) is available at the serial output (SOUT). This output is used to cascade
several drivers to perform any vertical resolution (Table 5). Inputs CLK, STB, SIN and SOUT are
Schmitt trigger inputs.
The forward / reverse (F/R) input is used to select the direction of the shift register where data input/
output status is set according to the selected direction. In Reverse mode (F/R = low), data is input
on the SOUT pin and output on the SIN pin.
The maximum frequency of the shift clock is 8 MHz.
The clear signal (CLR) resets the shift register data to 0 when it is pulled to a high level.
Shift register outputs (P1, ... P64) are transferred from the shift register to the latch stage when the
Figure 2: STV7697B Block Diagram
Table 5: Shift Register Truth Table
Circuit Description STV7697BAll the data are kept memorized in the latch stage when the strobe input (STB) is pulled high.
The Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input
(POL) at high level and forced to low level with POL at low level. The level of the power output is
inverted when the polarity command (POL) is pulled high.
Driver outputs can be simultaneously polarized at high or low level depending on the biasing of the
POL input signal (Table 6).
Sustain current must not be sunk in the power output to VPP when the power supply is applied. SSLOG and V SSSUB must be connected as close as possible to the logical reference ground of the
application. n is the parallel output of the shift register (n = 1 to 64). Pn takes the value of serial input (SIN) after “n” shift
clock periods.
Table 6: Power Output Truth Table
STV7697B Electrical Characteristics Electrical Characteristics
3.1 Absolute Maximum Ratings Note:1. Through one power output. Through one power output with VPP = V SSP (See Figure 4.) These parameters are measured during ST’s internal qualification which includes temperature
characterization on standard batches and on corners batches of the process. These parameters are
not tested on the parts.
3.2 Thermal Data Note:1. TQFP soldered on 4-layer printed circuit board.
