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STV5348-STV5348/T-STV5348D
MONOCHIP TELETEXT AND VPS DECODERWITH 8 INTEGRATED PAGES
1/30May 2004
STV5348
STV5348/H - STV5348/TMONOCHIP TELETEXT AND VPS DECODER
WITH 8 INTEGRATED PAGES
REV. 2
FEATURES SUMMARY COMPLETE TELETEXT AND VPS DECODER
INCLUDING AN 8 PAGE MEMORY ON A
SINGLE CHIP UPWARD SOFTWARE COMPATIBLE WITH
PREVIOUS ST’s MULTICHIP SOLUTIONS
(SAA5231, SDA5243, STV5345) PERFORM PDC SYSTEM A (VPS) AND PDC
SYSTEM B (8/30/2) DATA STORAGE
SEPARATELY DEDICATED "ERROR FREE" OUTPUT FOR
VALID PDC DATA INDICATION OF LINE 23 FOR EXTERNAL
USE SINGLE +5V SUPPLY VOLTAGE SINGLE 13.875MHz CRYSTAL REDUCED SET OF EXTERNAL
COMPONENTS, NO EXTERNAL
ADJUSTMENT OPTIMIZED NUMBER OF DIGITAL SIGNALS
REDUCING EMC RADIATION HIGH DENSITY CMOS TECHNOLOGY DIGITAL DATA SLICER AND DISPLAY
CLOCK PHASE LOCK LOOP 28 PIN DIP & SO PACKAGE
DESCRIPTIONThe STV5348 decoder is a computer-controlled
teletext device including an 8 page internal mem-
ory. Data slicing and capturing extracts the teletext
information embedded in the composite video sig-
nal. Control is accomplished via a two wire serial2 C bus ®. Chip address is 22h. Internal ROM pro-
vides a character set suitable to display text using
up to seven national languages. Hardware and
software features allow selectable master/slave
synchronization configurations. The STV5348
also supports facilities for reception and display of
current level protocol data.
Figure 1. Package
Figure 2. Pin Connections
STV5348 - STV5348/H - STV5348/T
Table 1. Pin Description
3/30
STV5348 - STV5348/H - STV5348/T
Figure 3. Block Diagram
Table 2. Absolute Maximum Ratings
STV5348 - STV5348/H - STV5348/T
ELECTRICAL CHARACTERISTICS (VDD = 5V, VSS = 0V, TA = 25°C)
Table 3. Supplies
Table 4. Inputs
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STV5348 - STV5348/H - STV5348/T
Table 5. Outputs
Table 6. Crystal Oscillator
STV5348 - STV5348/H - STV5348/T
Table 7. Timing
Figure 4. Display Output Timing
7/30
STV5348 - STV5348/H - STV5348/T
Figure 5. Serial Bus Timing
Figure 6. Master Synchronization Mode - Hardware Configuration
STV5348 - STV5348/H - STV5348/T
Figure 7. Master Synchronization Mode - Delivered Composite Synchronization Signal
Figure 8. Slave Synchronization Mode
Figure 9. Data Valid Timing (DV)
9/30
STV5348 - STV5348/H - STV5348/T
FUNCTIONAL DESCRIPTION
Displayable Page Memory MapThe organization of a page memory is shown in
Figure 10.
The display area consists of 25 rows of 40 charac-
ters per row.
The organization is as follows: Row zero contains the page header: The first seven characters (0 - 6) are used for
messages regarding the operational status. The eighth character is an alphanumeric
control character either "white" or "green"
defining the "search" status of the page.
When it is "white" the operational state is
normal and the header appears white; when
it is "green" the operational state corresponds
to the "search mode" and the header appears
green. The following twenty-four characters give the
header of the requested page when the
system is in search mode. The last eight characters display the time of
day. Row number twenty-four is used by the
microprocessor for the display of information, or
used to display X/24 colored key data according
to R0D7 bit. Row twenty-five comprises ten bytes of control
data concerning the received page (see Table
9) and fourteen free bytes which can be used by
the microprocessor.
Figure 10. Page Memory Organization
STV5348 - STV5348/H - STV5348/T
Table 8. Ghost Row Storage OrganizationNote:1. Packet 8/30 storage: 8/30/0,1: chapter 4, row23
8/30/2,3: chapter 5, row23
8/30/4 to 15: chapter 6, row23 See Table 10 for VPS data storage.
Page related data
stored in chapter
corresponding tolevel 1 data,
i.e. For 0 goes in 4 1 " " 5""6""7
11/30
STV5348 - STV5348/H - STV5348/T
Table 9. Row 25 Received Page Control Data Format
VPS DATA (see Table 10)VPS data are stored in row 25 chapter 5 as shown
in Table 10 when VPS enable bit (D4 of R8 regis-
ter) is set. VPS data bits are decoded and stored
in a received area with biphase error bit.
8/30/2 data are stored as received (without ham-
ming decoding) in Row 23 chapter 5 according to
Table 10.
8/30 packet and VPS data decoding is the respon-
sibility of the control software. The decoder simply
stores transmitted data.
2 C Bus Register Map (see Table 11)Registers R0 to R10 are write only whilst R11A is
a read/write and R11B is read only.
The automatic succession on a byte by byte basis
is indicated by the arrows in Table 10.
In the normal operating mode TB should be set to
logic level 0.
After power-up the contents of the registers are as
follows: all bits in registers R0 to R11A are cleared
to zero with the exception of bits D0 and D1 in reg-
isters R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimal value 20H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to "alpha white" hexadecimal value 07H.
Table 10. PDC Data Storage
STV5348 - STV5348/H - STV5348/T
Table 11. Register SpecificationNote (1). Reserved register bits: must be set to 0.
R0 Mode 0
R1 Mode 1 Page request address Page request data Display chapter Display control
(normal) Display control
(newsflash / subtitle)
R7 Display mode
R8 Active chapter
R9 Active row
R10 Active column
R11A Active data
R11B Status
13/30
STV5348 - STV5348/H - STV5348/T
Table 12. Registers Functions
STV5348 - STV5348/H - STV5348/TNote:1. Reading of R11A or R11B is determined by register 0, bit D0. However, write operation is always performed on R11A register.
15/30
STV5348 - STV5348/H - STV5348/T
Table 13. Register R3
Character SetsThe complete character set with 8-bit decoding is
given in Table 12.
Characters in columns 0 and 1 are normally dis-
played as blanks. Black dots represent the charac-
ter shape whereas white dots represent the
background.
Each character can be identified by a pair of corre-
sponding row and column integers: for example
the character "3" may be indicated by 3/3.
A rectangle may be represented as follows:
The characters 8/6, 8/7, 9/5, 9/7 are used as spe-
cial characters, always in conjunction with 8/5.
The 13 national characters are placed in columns
with bit 8 = 0.
