STV0299B ,QPSK/BPSK LINK ICSTV0299BQPSK/BPSK LINK IC
STV0299B
QPSK/BPSK LINK IC
May 2000 1/36
STV0299BQPSK/BPSK LINK IC
MULTISTANDARD QPSK AND BPSK
DEMODULATION EASY IMPLEMENTATION WITH LOW COST
DIRECT CONVERSION TUNERS EXTREMELY LOW BER WHEN
CO-CHANNEL INTERFERENCE WIDE CARRIER LOOP TRACKING RANGE TO
COMPENSATE FOR DISH FREQUENCY DRIFT COMMON INTERFACE COMPLIANT VERY LOW POWER CONSUMPTION INTEGRATED DUAL 6-BIT ANALOG TO
DIGITAL CONVERTERS DUAL DIGITAL AGC DIGITAL NYQUIST ROOT FIL TER WITH
ROLL-OFF OF 0.35 OR 0.20 DIGITAL CARRIER LOOP WITH LOCKDETECTOR, ON-CHIP WIDE RANGE
DEROTATOR AND TRACKING LOOP
(TYP±45 MHz) DIGITAL TIMING RECOVERY WITH LOCK
DETECTOR CHANNEL BIT RATE UP TO 90 Mbps AND
SYMBOL FREQUENCY RATE FROMTO50 MSYMBOLS INNER DECODER: VITERBI SOFT DECODER FOR
CONVOLUTIONAL CODES, M=7, RATE 1/2 PUNCTURED CODES 1/2, 2/3, 3/4, 5/6, 6/7 AND 7/8 SYNCHROWORD EXTRACTION CONVOLUTIVE DEINTERLEAVER OUTER DECODER: REED-SOLOMON DECODER FOR PARITY BYTES; CORRECTION OF UP
TO 8 BYTE ERRORS ENERGY DISPERSAL DESCRAMBLER ON-CHIP FLEXIBLE CLOCK SYSTEMS TO
ALLOW USE OF EXTERNAL CLOCK
SIGNALS IN 4 MHz TO 30 MHz RANGE EASY-TO-USE C/N ESTIMATOR WITH 2 TO dB RANGEI2 C SERIAL BUS AND REPEATER DVB COMMON INTERFACE COMPLIANT
PARALLEL OUTPUT FORMAT PARALLEL AND SERIAL DATA OUTPUT LNB SUPPL Y CONTROL WITH STANDARD I/O, KHz TONE AND DISEQCTM MODULATOR
WITH TTL OUTPUT CMOS TECHNOLOGY: 2.5 V OPERATION;
JEDEC (EIA/JESD8-5)
APPLICATIONS DIGITAL SATELLITE RECEIVER AND
SET-TOP BOXES
DESCRIPTIONThe STV0299 Satellite Receiver with FEC is a
CMOS single-chip multistandard demodulator for
digital satellite broadcasting. It consists of two A/D
converters for I-input and Q-input, a multistandard
QPSK and BPSK demodulator, and a forward
error correction (FEC) unit having both an inner
(Viterbi) and outer (Reed-Solomon) decoder.
The FEC unit is compliant with the DVB-S and
DSSTM specifications. Processing is fully digital.
It integrates a derotator before the Nyquist root
filter, allowing a wide range of offset tracking.
The high sampling rate facilitates the
implementation of low-cost, direct conversion
tuners.
A variety of configurations and behaviours can be
selected through a bank of control/configuration
registers via an I2 C. The chip outputs MPEG ransport Streams and interfaces seamlessly to
the Packet Demultiplexers embedded in ST’s
ST20-TPx or STi55xx. High sampling frequency
(up to 90MHz) considerably reduces the cost of
LPF of direct conversion tuners.
The multistandard capability associated with a
broad range of input frequency operations makes
it easy-to-use. Its low power consumption, small
package and optional serial output interface
makes it perfect for embedding into a tuner.
STV0299B2/36
PageTABLE OF CONTENTS
1 PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pinout Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 SYSTEM CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Front End Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.1.1 I2 C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.2 Write Operation (Normal Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.3 Read Operation (Normal Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.4 I2 C Interface in Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1.5 Specific Concerns about SCL Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.6 Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.7 Sampling Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.8 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1.9 Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.10 I2C Bus Repeater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.11 General Purpose ΣΔ DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.12 DiSEqC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1.13 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.2.1 I and Q Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.2 Main AGC (or AGC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.3 Nyquist Root and Interpolation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.4 Offset Cancellation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2.5 Signal AGC (or AGC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Timing Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.3.1 Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.2 Loop Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.3 Timing Lock Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Carrier Recovery and Derotator Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.4.1 Loop Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.2 Carrier Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.3 Derotator Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.4 Carrier Frequency Offset Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Noise Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Forward Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154.6.1 FEC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6.2 Viterbi Decoder and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6.3 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.4 Error Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.5 Convolutional Deinterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.6 Reed-Solomon Decoder and Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.7 Parallel Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.8 Serial Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 REGISTER LIST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STV0299B
PageTABLE OF CONTENTS (continued)
6.2 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5 I2
C Bus Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7 APPLICATION BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STV0299B4/36
PIN INFORMATION
1.1 Pin Connections
STV0299B5/36
PIN INFORMATION (continued)
1.2 Pinout DescriptionNote:1 The following abbreviations are used: I - Input; O - Output; OD - Open drain output. 3.3 V output levels. 5 V tolerant
SIGNAL INPUTSFRONT END CONTROLS
SIGNAL OUPUTS2 C INTERFACE
OTHERS
STV0299B6/36
BLOCK DIAGRAM SYSTEM CHARACTERISTICS
PerformancesThe following given parameters are for indication
purposes only.
Carrier Loop Tracking Range: ±f M_CLK/2
Carrier Loop Capture Range (C/N>=4 dB): up to ± 5% fs in less than 100 Ksymbols up to ± 2% fs in less than 10 Ksymbols
C/N Threshold (lowest C/N at which capture is
possible) = 1 dB.
Timing Loop Capture Range (C/N>=2 dB): up to ±250 ppm in less than 100 Ksymbols conventions used for the above characteristics
are:
fsampling = fm_clk = fmaster_clocks = f symbol
C/N = Carrier/Noise =
PR = Puncture Rate-
STV0299B7/36
FUNCTIONAL DESCRIPTIONThe STV0299B is a multistandard demodulator
and error correction decoder IC for the reception
of QPSK and BPSK modulated signals. It is
intended for use in digital satellite television
applications. The IC can accept two standards of
QPSK modulated signals (DVB and DSS) as well
as BPSK modulated signals over a wide symbol
frequency range (from 1 to 50 Msymbols/s). The
signals are digitized via an integrated dual 6-bit
analog to digital converter, and interpolated and
digitally filtered by a Nyquist root filter (with a
settable roll-off value of either 0.35 or 0.20).
There are two built-in digital Automatic Gain
Controls (AGCs). The first AGC allows the tuner
gain to be controlled by the pulse density
modulated output. The second AGC performs
power optimization of the digital signal bandwidth
(internal to the STV0299B). The digital signal then
passes through the digital carrier loop fitted with
an on-chip derotator and tracking loop, lock
detector, and digital timing recovery.
Forward error correction is integrated by way of an
inner Viterbi soft decoder, and an outer
Reed-Solomon decoder.
4.1 Front End Interfaces
4.1.1I2 C InterfaceThe standard I2 C protocol is used whereby the
first byte is Hex D0 for a write operation, or Hex
D1 for a read operation. The I2 C interface
operates differently depending on whether it is in
normal or standby mode.
4.1.2 Write Operation (Normal Mode)The byte sequence is as follows: The first byte gives the device address plus the
direction bit (R/W=0). The second byte contains the internal address
of the first register to be accessed. The next byte is written in the internal register.
Following bytes (if any) are written in
successive internal registers. The transfer lasts until stop conditions are
encountered. The STV0299B acknowledges every byte
transfer.
4.1.3 Read Operation (Normal Mode)The address of the first register to read is
programmed in a write operation without data, and
terminated by the stop condition. Then, another
start is followed by the device address and R/= 1. All following bytes are now data to be read
at successive positions starting from the initial
address. Figure 2 shows the I2 C Normal Mode
Write and Read Registers.
4.1.4I2 C Interface in Standby ModeOnly three registers can be addressed while in
standby mode: RCR (address 01 Hex), MCR
(address 02 Hex) and ACR (address 03 Hex).
These three registers can be either read or written
to (refer to Figure3).
Only one register may be read or written to per
sequence (no increment). While in standby mode,
the Serial Clock (SCL) frequency must be lower than
one tenth of the CLK_IN frequency (fCLK_IN/ 10).
Figure 2:I2 C Read and Write Operations in Normal Mode
Figure 3:I C Read and Write Operations in Standby Mode
STV0299B8/36
FUNCTIONAL DESCRIPTION (continued)
4.1.5 Specific Concerns about SCL
FrequencyFor reliable operation in Normal Mode, the SCL
frequency must be lower than 1/40 of the Master
Clock (M_CLK) frequency. Consequently, care
should be taken to observe the following: Before returning to Normal Mode from Standby
Mode, the M_CLK frequency must be selected
such that fM_CLK ≥ 40 fSCL After Power-on reset signal, the STV0299B
operates in Normal Mode. There are two possi-
ble cases: DIRCLK-DIS (pin 58) is grounded.
M_CLK= CLK_IN, the fSCL frequency of the2 C bus must satisfy: . DIRCLK-DIS (pin 58) is tied to VDD
(where ), and the fSCL
frequency of the I2 C bus must satisfy:
and fSCL≤ 400 kHz.
For example, this second operating mode is
required when the application features both a MHz XTAL and a 400 kHz I2 C bus.
4.1.6 Identification RegisterThe Identification Register (at address Hex 00)
gives the release number of the circuit.
The content of this register at reset is presently A1
(same as STV0299).
4.1.7 Sampling FrequencyThe STV0299B converts the analog inputs into
digital 6-bit I and Q flows. The sampling frequency
is fM_CLK which is derived from an external
reference described in Section 4.1.8 ‘Clock
Generation’. The maximum value of fM_CLK is 90
MHz.
The sampling causes the repetition of the input
spectrum at each integer multiple of fM_CLK. One
has to ensure that no frequency component is
folded in the useful signal bandwidth of fS (1+α)/2
where fS is the symbol frequency, and α is the
roll-off value.
4.1.8 Clock GenerationAn integrated VCO (optimised to run in the range
of 300 to 400 MHz) is locked to a reference
frequency provided by a crystal oscillator by the
following relation:
The VCO’s loop filter is optimized for a reference
frequency between 4 and 8 MHz.
The VCO generates the following by division: The Master Clock (M_CLK) An auxiliary clock (AUX_CLK) which may either
be in the MHz range or in the 25 Hz to 1500Hz
range for some specific LNB control (for
example, 60 Hz). A lower frequency, F22, typically 22 KHz,
needed for LNB control or DiSEqCTM control.
When DIRCLK_CTRL = 1, the crystal signal is
routed directly to M_CLK; the VCO may still be
used to generate AUX_CK and/or the F22 (used
by the DiSEqCTM interface).
If the internal VCO is not used by any of the
dividers, it may be stopped in order to decrease
the power consumption and/or radiation
emissions. The only guaranteed function in
standby mode is the I2 C Write/Read function of
the three clock control registers.
There are restrictions on the high and low level
durations, and on the crystal (or external clock)
frequency when the direct clock is used.
These restrictions are explained in Section 4.1.5
Specific Concerns about SCL Frequency.
SCL CLK_IN
---------------------≤
fSCL 100 40×------------------- CLK_IN⋅≤
fVCO fref 4M1+()⋅⋅
fXTAL4 M1+
+--------------⋅⋅==
STV0299B9/36
FUNCTIONAL DESCRIPTION (continued)
Figure 4: Clock Signal Generation
Note:1 Refer to the Register List P[2:0] in table 1 At the rising edge of RESET signal (pin 15) the corresponding bit of the I2 C bus register is forced to the status of pin STDBY or
to DIRCLK-DIS.
Table 1: Divider Programming
Table 2: Summary of FM_CLK
STV0299B10/36
FUNCTIONAL DESCRIPTION (continued)
4.1.9 Clock RegistersThe Reference Clock, Master Clock, Auxiliary
Clock and F22 Frequency Registers are in
Addresses 01, 02, 03 and 04.
4.1.10I2 C Bus RepeaterIn low symbol rate applications, signal pollution
generated by the SDA/SCL lines of the I2 C bus
may dramatically worsen tuner phase noise. In
order to avoid this problem, the STV0299B offers
an I2 C bus repeater so that the SDAT and SCLT
are active only when necessary and muted once
the tuner frequency has settled.
Both SDAT and SCLT pins are set high at reset.
When the microprocessor writes a 1 into register
bit I2 CT, the next I2 C message on SDA and SCL is
repeated on the SDAT and SCLT pins respectively,
until stop conditions are detected. o write to the tuner, the external microprocessor
must, for each tuner message, perform the
following: Program 1 in I2CT. Send the message to the tuner.
Any size of byte transfers are allowed, regardless
of the address, until the stop conditions are
detected. T ransfers are fully bi-directional.
The I2 CT bit is automatically reset at the stop
condition. If not used for the I2 C repeater, both
SDAT and SCLT outputs may be used as general
purpose output ports.
SDAT status may be read on the DiSEqC register.
Configuration is controlled by the I2 C repeater
register in Address 0Ah.
In the first version of the STV0299, operation of
the repeater was very fast, and often too fast
versus the rise time of the SDAT and SCLT
signals. In the STV0299B, a programmable delay
is implemented to accept a wide range of rise
times on SDAT and SCLT. The delay is
programmed with Reg.05 [5:4]. In practice,
operation of the repeater is ensured in the
following case: Reg.05 [5:4]: xxf M_CLK≤90 MHz RC≤ 250ns (R: pull-up resistor, C: total
capacitance on either SDAT or SCLT).
4.1.11 General Purpose ΣΔ DACA DAC is available in order to control external
analog devices. It is built as a sigma-delta
first-order loop, and has 12-bit resolution-it only
requires an external low-pass filter (simple RC
filter). The clock frequency is derived from the
main clock by programmable division. The
converter is controlled by two registers-one for
clock divider control and 4 MSBs, and the other for
the 8 LSBs.
If the DAC is not needed, the DAC output may be
used as an output port. The DAC Registers are in
Addresses 06 and 07.
4.1.12 DiSEqC InterfaceThis interface allows for the simplification of real
time processing of the dialog from microprocessor
to LNB. It includes a FIFO that is filled by the
microprocessor via the I2 C bus, and then
transmitted by modulating the F22 clock adjusted
beforehand to 22 kHz. wo control signals are available on the I2 C bus:
FE (FIFO empty) and FF (FIFO full).
A typical byte transfer loop, as seen from the
microprocessor, may be the following:
While (there is data to transfer) Read the control signals If FF=1, go to 1 Write byte to transfer in the FIFO
Note, for the above transfer loop, the following: At the beginning, the FIFO is empty (FE=1,
FF=0). This is the idle state. As soon as a byte is written in the FIFO, the
transfer will begin. After the last transmitted byte, the interface will
go into the idle state.
ModulationThe output is a gated 22 kHz square signal.
In the idle state, modulation is permanently
inactive.
In byte transmission, the byte is sent (MSBfirst) and is followed by an odd parity bit.
A byte transmission is therefore a serial 9-bit
transmission with an odd number of “1’s”.
Each bit lasts 33 periods of F22 and the
transmission is PWM-modulated.
Transmission of “0’s”. There are twosubmodes controlled by PortCtrl(2):
a) PortCtrl2 = 1: Modulation is active during
22 pulses, then inactive during 11 pulses
(2/3 PWM).
b) PortCtrl2 = 0: Modulation is active during
33 pulses (3/3 PWM).
Transmission of “1’s”. During transmissionof “1’s”, modulation is active during 11 pulses,
then inactive during 22 pulses (1/3 PWM).
This is compatible with “Tone Burst” in older LNB
protocols.
For the “Modulated Tone Burst”, only one byte
(with value Hex FF) is written in the FIFO.
The parity bit is 1, and as a result, the output
signal is 9 bursts of 0.5 ms, separated by intervals of 1ms.
STV0299B11/36
For the “Unmodulated Tone Burst” Port CTRL2 is
set to 0 and, only one byte, of value 00h is sent.
The parity bit is still 1, and as a result, the signal is continuous train of 12.5 ms. When the
modulation is active, the DiSEqC output is driven
alternatively to VDD and VSS levels. The DiSEqC
and Lock Control, DiSEqC FIFO and DiSEqC
Status Registers are in Addresses 08, 09 and
0Ah.
Figure 5: Schematic showing Bit Transmission
Table 3: Note:1 Byte to transfer in DiSEqC mode. In mode PortCtrl (1:0)=10, the F22/DiSEqC pin returns to High -2 mode once the transmission is completed.
4.1.13 Standby ModeA low power consumption mode (standby mode)
can be implemented (in this mode, fM_CLK = 0). In
standby mode, the I2 C decoder still operates, but
with some restrictions (see Sections 4.1.4 and
4.1.5).
Standby mode can be initiated or stopped by I2C
bus commands as described in MCR Register 02.
At power-on, the circuit starts to operate in
standby mode when the STDBY pin (pin 42) is
tied to VDD. This guarantees low power
consumption for the stand-alone modules
(PCMCIA size front-end modules) before any
command is initiated. After the power-on
sequence, the standby mode is entirely controlled
via MCR Register (02).
STV0299B12/36
FUNCTIONAL DESCRIPTION (continued)
4.2 Signal Processing
4.2.1 I and Q InputsThe ADC features differential inputs, but in most
applications I & Q signals are single-ended. In
such applications, I and Q signals from the tuner
are fed to the respective IP and QP inputs through
a capacitor. The IN and QN pins are DC biased,
typically to VBOT .The internal biasing of the ADC is
done on the circuit at the mid-voltage between
VTOP and VBOT.
The Input/Output Configuration Register is
described in Address 0Ch.
4.2.2 Main AGC (or AGC1)The modulus of the I/Q input is compared to a
programmable threshold, m1, and the difference
is integrated. This signal is then converted into a
pulse density modulation signal to drive the AGC
output. It should be filtered by a simple analog
filter to control the gain command of any amplifier
before the A to D converter.
The output converter operates at f M_CLK /8 in order
to decrease the radiated noise and to simplify the
filter design. The output is a 5 V tolerant open
drain stage.
The reset value of the coefficient allows an initial
settling time of less than 100k master clock
periods.
The 8 integrator MSBs may be read or written at
any time by the microprocessor. When written, the
LSB’s are reset and the coefficient may be set to
zero by programming (in this case, the AGC is
reduced to a programmable 8-bit voltage
synthesizer).
The time constant of agc1 is estimated as
followed:
with m1= AGC1 reference level.
The AGC1 Control, AGC1 Reference and AGC1
Integrator Registers are in Addresses 0D and 0F.
4.2.3 Nyquist Root and Interpolation FiltersTwo roll off values are available: 0.35 and 0.20.
Refer to the Input/Output Configuration Register
in Address 0C.
4.2.4 Offset CancellationThis device suppresses the residual DC
component on I and Q. The compensation may be
frozen to its last value by resetting the DC offset
compensation bit in the AGC Control Register in
Address 0D.
4.2.5 Signal AGC (or AGC2)The rms value of I and Q is measured after the
Nyquist filter and compared to a programmable
value, m2, such as that of the main AGC.
The integrated error signal is applied to a
multiplier on each I and Q path.
The AGC2 Control Register is in Address 10.
Bits [7:5] give the AGC2 coefficient, which sets
beta_agc2, the gain of the integrator. Table4
shows how beta_agc2 is programmed with AGC2
coefficient (which is related to the time constant of
the AGC).
Table 4: If AGC2 Coefficient=0, the gain remains
unchanged from its last value.
The time constant is independent of the symbol
frequency, however it does depend on the
modulus, m1, of the input signal, programmed in
AGC1, with the following approximate relation:
The AGC2 Integrator Registers (2 bytes - MSB
and LSB) are in Addresses 18 and 19. These
values may be read or written by the
microprocessor. When written, all the LSB’s
integrator bits are reset. This value is an image of
the signal power in the useful band. Compared
with the total power of the signal, the out-of-band
power may be computed (noise, or other channel).
Tagc12 βagc1–
-----------------------
TM_CLK×=
agc2 103×
T M_CLK⋅
beta_agc2⋅ ---------------------------------------------=
STV0299B13/36
FUNCTIONAL DESCRIPTION (continued)
4.3 Timing Recovery
4.3.1 Timing ControlThe loop is parametrized by two coefficients:
alpha_tmg and beta_tmg. alpha_tmg can take
values from 0 to 4, and beta_tmg from 0 to 7
(Register 0E).
When the parameter is 0, the actual coefficient
value is zero. The 8 MSBs of the frequency
accumulator may be read or written at any time by
the I2 C bus—when written, all LSBs are reset.
The Symbol Frequency Registers (MSB, Middle
Bits and LSB) are in Addresses 1F, 20 and 21.
These must be programmed with the expected
symbol frequency.
The units are:
Write mode is effective when writing the Middle Bit
Register. The MSB Register must be loaded
before the Middle Bit Register.
The value of the Timing Frequency Register, when
the system is locked, is an image of the frequency
offset. The unit is fS/219 (approx. 2 ppm). It should
be as close as possible to 0 (by adjusting symbol
frequency register value) in order to have a
symmetrical capture range. Reading it allows for
optimal trimming of the timing range (Register
1A).
The actual symbol frequency is:
where fs_reg is the content of the symbol frequency
register and Tmg_reg the content of the timing
frequency register.
4.3.2 Loop EquationThe timing loop may be considered as a second
order loop. The natural frequency and the
damping factor may be calculated using the
following formula:
where, fS is the symbol frequency, m2 is the AGC2
reference level and β is programmed by the timing
register:
The damping factor is:
where m2 is the reference level of the AGC2
register.able 5 shows the natural frequency in DVB, with
nominal reference level m2= 20, for different
values of beta_tmg and alpha_tmg, without noise.
4.3.3 Timing Lock IndicatorThe timing lock indicator reports a value
dependent upon the signal-to-noise ratio and on
the signal lock state.
With an AGC2 Reference level m2= 20, if the
timing lock indicator is above 48, the timing is
locked; if it is above 42, this shows that a QPSK
signal is present, either locked with low C/N
(<3.6 dB) or unlocked with higher C/N; the
ambiguity may be solved by changing on purpose
the timing frequency of 1%; if it was locked before,
the indicator should be now under 42.
The indicator needs 30K symbols for stabilization
from unlock to lock after a frequency change.
The timing lock registers - the Timing Lock Setting
Register and the Timing Lock Indicator Register -
are in Addresses 11 and 17.
Table 5:
fM_CLK20----------------
Sact M_CLKfs_reg⋅ ()
2fsT mg_reg⋅⋅ ()+
20-------- -------------------------------------------------------------------------------=
STV0299B14/36
FUNCTIONAL DESCRIPTION (continued)
4.4 Carrier Recovery and Derotator LoopThe tracking range of the derotator is ±f M_CLK/2 fsampling/2). The initial frequency search may
therefore be performed on several MHz ranges
without reprogramming the tuner.
Three phase detectors are selectable using
software: Phase detector algorithm 0: This algorithm
should only be used for BPSK reception. Phase detector algorithm 1: This algorithm is
used with QPSK reception, over a small range
of capture phases and with a channel noise
value over 4.5dB. Phase detector algorithm 2: For QPSK
reception, it is used after locking, to minimize
the bit error rate in low channel noise
conditions. Algorithm 2 is recommended for
most applications.
The loop is controlled through α and β
parameters.
The carrier loop control registers (the Alpha
Carrier Register, the Beta Carrier Register and the
Carrier Frequency Register) are in Addresses 13,
14, 22 and 23.
4.4.1 Loop ParametersLike the timing loop, the carrier loop is a
second-order system where two parameters, α
and β, may be programmed with alpha_car and
beta_car respectively.
The natural frequency (fn) is:
The damping factor is:
where α =(2+a)⋅2b⋅214 , with b≥ 1, and= (4+2c+d)⋅2e , with e≥ 1. m2 is the reference
level in the AGC2 register.
4.4.2 Carrier Lock DetectorThe carrier lock detector provides an indicator
with a high value when the carrier is locked,
dependent on the channel noise. When the carrier
is not locked, the indicator value is low.
The indicator value is compared to a
programmable 8-bit threshold (Register 15h). The
result of this comparison (1 if greater than the
threshold, else 0 if not) is written as the Carrier
Found flag (CF), and may be read in the status
register. The CF signal may be permanently
routed on the output LOCK (see Register 08h).
The Lock Detector Threshold Register and Lock
Detector Value Register are in Addresses 15 and
1C.
4.4.3 Derotator FrequencyThe derotator frequency can be either measured
(read operation) or forced (write operation).
Derot_freq is a 16-bit signed value.
The Derot_freq Registers are Registers 22 and
4.4.4 Carrier Frequency Offset Detector
The carrier recovery loop features a carrier
frequency offset detector and two phase
detectors. When the carrier frequency offset
detector is enabled, the central loop frequency is
modified proportionally to the carrier offset. The
gain and time constants of the detector are set by
CFD[6:4] and CFD[3:2] respectively. When the
carrier loop is about to “phase lock” with the
carrier, the frequency detector stops automatically
and the phase lock is ensured by the selected
phase detector. This switchover point is
determined by the threshold CFD [1:0].
For stability reasons, the gain CFD [6:4] should
not exceed the coefficient e[3:0] of Register
BCLC.
The carrier frequency offset detector is in Address
4.5 Noise Indicator
The noise indicator may be used to facilitate the
antenna pointing or to give an idea of the RF
signal quality and of the front-end installation
(dish, LNB, cable, tuner or ADC).
A simple C/N estimator can be easily
implemented by comparing the current indications
with a primarily-recorded look-up table.
The time constant ranges from 4 k to 256k
symbols. The 16 MSB of the result may be read by
the microprocessor (Registers 24 and 25).
n 7106–
f M_CLK⋅⋅=
22106–α⋅ ⋅
=
freq()
kHz Derot_freq16------------------------------
f M_CLK()
kHz⋅=
STV0299B15/36
FUNCTIONAL DESCRIPTION (continued)
4.6 Forward Error Correction
4.6.1 FEC ModesSince the STV0299B is a multistandard decoder,
several combinations are possible, at different
levels: The demodulator may accept either QPSK or
BPSK signals - the only impact is on the carrier
algorithm choice (refer to Chapter 4.4).
The algorithm choice also affects the carrier
lock detector and the noise evaluation. There two primary options concerning the FEC
operation - between DVB, DSS and Reserved
Mode. There are two options concerning the FEC
feeding. The first is IQ flow, which is the usual
case in QPSK modes DVB or DSS. The second
mode is I-only flow, used for BPSK.
The FEC Mode Register is in Address 28.
In Modes DVB and DSS, data is fed to the Viterbi
decoder. Other parts of the decoding (such as the
Convolutional Deinterleaver) may be bypassed.
4.6.2 Viterbi Decoder and SynchronizationThe convolutive codes are generated by the
polynomial Gx = 171 octets and Gy = 133 octets in
modes DVB or DSS.
The Viterbi decoder computes for each symbol
the metrics of the four possible paths, proportional
to the square of the Euclidian distance between
the received I and Q and the theoretical symbol
value.
The puncture rate and phase are estimated on the
error rate basis. Several rates are allowed and
may be enabled/disabled through register
programming: 1/2, 2/3, 3/4, 5/6, 7/8 in DVB. 1/2, 2/3, 3/4, 5/6 and 6/7 in DSS.
For each enabled rate, the current error rate is
compared to a programmable threshold. If it is
greater than this threshold, another phase (or
another rate) is tried until the right rate is obtained.
A programmable hysteresis is added to avoid
losing the phase during short term perturbation.
The rate may also be imposed by external
software, and the phase is incremented only upon
request by the microprocessor. The error rate may
be read at any time in order to use an algorithm
other than that implemented.
The Viterbi decoder produces an absolute
decoding. The decoder is controlled via several
Viterbi Threshold Registers (Registers 29, 2A, 2B,
2C and 2D). For each Viterbi Threshold Register,
bits 6 to 0 represent an error rate threshold - the
average number of errors occurring during 256-bit
periods. The maximum programmable value is
127/256 (higher error rates are of no practical
use).
The Puncture Rate and Synchro Register is in
Address 31.
The automatic rate research is only done through
the enabled rates (see the corresponding bit set in
the Puncture and synchro register). In DSS, the
puncture rate 6/7 replaces the puncture rate 7/8.
In DSS, it is recommended that you disable
puncture rates 3/4 and 5/6 in order to save time in
the synchronization process.
The VSEARCH Register is in Address 32.
VSEARCH bit 7 (A/M) and bit 6 (F) programs the
automatic/manual (or computer aided) search
mode as follows: If A/M =0 and F=0, automatic mode is set.
Successive enabled punctured rates are tried
with all possible phases, until the system is
locked and the block synchro found. This is the
default (reset) mode. If A/M=0 and F=1, the current puncture rate is
frozen. If no sync is found, the phase is
incremented, but not the rate number.
This mode allows shortening of the recovery
time in case of noisy conditions. The puncture
rate is not supposed to change in a given
channel. In a typical computer-aided
implementation, the research begins in
automatic mode. The microprocessor reads the
error rate or the PRF flag in order to detect the
capture of a signal, then it switches F to 1, until
a new channel is requested by the remote
control. If AM=1 manual mode is set. In this case, only
one puncture rate should be validated -
the system is forced to this rate, on the current
phase, ignoring the time-out register and the
error rate. In this mode, each 0 to 1 transition of
the bit F leads to a phase incrementation,
allowing full control of the operation by an
external microprocessor by choosing the lowest
error rate.
The reset values are A/M=0, and F=0 (automatic
search mode).
The VERROR Register (a read only register) is in
Address 26. The last value of the error rate may
be read at any time in the register. Unlike the VTH,
the possible range is from 0 to 255/256.
The VSTATUS Register (a read only register) is in
Address 1B.
STV0299B16/36
FUNCTIONAL DESCRIPTION (continued)
4.6.3 SynchronizationIn DVB, the packet length after inner decoding is
204. The sync word is the first byte of each
packet. Its value is Hex 47, but this value is
complemented every 8 packets. In DSS, the
packet length is 147 and the sync word is Hex 1D.
An Up/Down Sync counter counts whenever a
sync word is recognized with the correct timing,
and counts down during each missing sync word.
This counter is bounded by a programmable
maximum - when this value is reached, the LK bit
(“locked”) is set in the VSTATUS register. When
the event counter counts down to until 0, this flag
is reset.
4.6.4 Error MonitoringA 16-bit counter, ERRCNT , allows the counting of
errors at different levels. ERRCNT is fed either by: the input QPSK bit errors (that are corrected by
the Viterbi decoder), or, the bit, or, the byte error (that are corrected by the
Reed-Solomon decoder), or, the packet error (not corrigible, leading to a
pulse at the ERROR output).
The content of ERRCNT may be transferred to the
read only registers ERRCNT_LOW (LSB) and
ERRCNT_HIGH (MSB).
Two functional modes are proposed, depending
on a control register bit: Error Mode= 0. This is an error rate measure,
that tells the number of errors occurring within
a specified number of output bytes, NB. NB has
four possible values given in the Error Control
Register in Address 34. Every NB bytes, the
state of the error counter is transferred to a
16-bit register, then the error counter is reset.
The Error Count Registers in Addresses 1D
and 1E may be read by the microprocessor via2C bus. Two ways of reading may be used:
16-bit reading, starting with MSB, or 8-bit
reading (LSB only or MSB only). Error Mode= 1. The error counter just counts
the error; the I2 C register permanently copies
the content of the error counter. When the MSB
byte is read, the error counter is reset. In both
modes, the 16-bit counter is saturated to its
maximum value.
4.6.5 Convolutional DeinterleaverIn DVB, the convolutional deinterleaver is 17x12.
The periodicity of 204 bytes per sync byte is
retained. In DSS, the convolutional deinterleaver
is 146x 13, and there is also a periodicity of
147 bytes per sync byte. The deinterleaver may
be bypassed - for details, see Section 4.6.6
‘Reed-Solomon Decoder and Descrambler’.
4.6.6 Reed-Solomon Decoder and
DescramblerThe input blocks are 204-byte long with 16 parity
bytes in DVB. The synchro byte is the first byte of
the block. Up to 8 byte errors may be fixed.
The Code Generator polynomial is:
over the Galois Field generated by:
Energy dispersal descrambler and output energy
dispersal descrambler generator:
The polynomial is initialized every eight blocks
with the sequence 100101010000000.
The synchro words are unscrambled and the
scrambler is reset every 8 packets.
The output interface may be forced into high
impedance mode by setting bit 0 of Address 28.
Doing this affects the D[7:0], CLK_OUT,
STR_OUT, D/P and ERROR pins. This also allows
for board testing, and “OR” wiring several link
circuits (for example, cable links). The output
stream is either parallel (byte stream) or serial (bit
stream) depending on bit 1 of Address 28.
The outputs are controlled by the RS Control
Register in Address 33.
4.6.7 Parallel Output InterfaceA schematic diagram of the parallel output
interface is shown in Figure 7. The parallel output
format is compliant with the DVB common
interface protocol.
When the SYNC is not found (LK= 0 in the status
register), D/P (corresponding to the MiVAL signal
of the DVB common interface standard) remains
at a low level.
CLK_OUT has a duty cycle between 40 and 60%.
()
xω
0–()
xω
1–()……()
xω
15– ()
=
STV0299B
17/36 FUNCTIONAL DESCRIPTION (continued)
4.6.8 Serial Output Interface
The serial output interface is shown in Figure6.
The serial bit stream is available on D7,
where MSB is first to reconstruct the original
order. If RS0= 0, then the parity bits are output
(Register 33). If RS0= 1, the data is null during
the parity time slots.
STR_OUT is only high during the first bit of each
packet, instead of during the first byte in parallel
mode.
ERROR has the same function as in parallel
mode.
CLK_OUT is the serial bit clock; it is derived fromeither the master clock, M_CLK, (if SerClk=0 in
Registers 02 and B3), or from the internal VCO
frequency divided by 6, (if SerClk= 1), by skippingsome pulses to accommodate the frequency
difference.
All of the outputs are synchronous of the same
master clock edge.
D0, STR_OUT , D/P and ERROR may be properly
sampled externally by the rising edge of
CLK_OUT, if RS1= 0, or by the falling edge of
CLK_OUT if RS1= 1. This clock runs
continuously, even during parity data, whatever
the value of RS0.
The first bit detected in a valid packet may be
decoded if it is found on the appropriate edge of
CLK_OUT, where STR_OUT= 1, ERROR=0,
D/P= 1. The following bits only require the
assertion of D/P (while D/P= 1,...).
Outputs D0 to D6 remain at low level in serial
mode.
Figure 6: Serial Output Interface
Figure 7: Parallel Output Interface
STV0299B
18/36
Table 6: Functional I2 C Register Map
