STV0056AF Fast Delivery |IC PHOENIX CO.,LIMITED

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STV0056AF
SATELLITE SOUND AND VIDEO PROCESSOR
STV0056AF
SATELLITE SOUND AND VIDEO PROCESSOR
February 1998
SOUND. TWO INDEPENDENT SOUND DEMODULATORS. PLL DEMODULATION WITH 5-10MHz FRE-
QUENCY SYNTHESIS. PROGRAMMABLE FM DEMODULATOR
BANDWIDTH ACCOMODATING FM DEVIA-
TIONS FROM ±30kHz TILL ±400kHz. PROGRAMMABLE 50/75μs, J17 OR NO DE-
EMPHASIS. WEGENER PANDA SYSTEM. TWO AUXILIARY AUDIO INPUTS AND OUTPUTS. GAIN CONTROLLED AND MUTEABLE
AUDIO OUTPUTS. HIGH IMPEDANCE MODE AUDIO OUTPUTS
FOR TWIN TUNER APPLICATIONS
VIDEO. COMPOSITE VIDEO 6-bit 0 to 12.7dB GAIN
CONTROL. COMPOSITE VIDEO SELECTABLE INVERTER. TWO SELECTABLE VIDEO DE-EMPHASIS
NETWORKS. 6 x 3 VIDEO MATRIX. BLACK LEVEL ADJUSTABLE OUTPUT FOR
ON-BOARD VIDEOCRYPT DECODER. HIGH IMPEDANCE MODE VIDEO OUTPUTS
FOR TWIN TUNER APPLICATIONS
MISCELLANEOUS. 22kHz TONE GENERA TION FOR LNB CONTROL.I2 C BUS CONTROL
CHIP ADDRESSES = 06HEX OR 46HEX. LOW POWER STAND-BY MODE WITH AC-
TIVE AUDIO AND VIDEO MATRIXES
DESCRIPTION
The STV0056AF BICMOS integrated circuit realizes
all the necessary signal processing from the tuner to
the Audio/Video input and output connectors regard-
less the satellite system.
1/27
PIN CONNECTIONS
PIN ASSIGNMENT
STV0056AF
2/27
PIN ASSIGNMENT (continued)
STV0056AF
3/27
PIN DESCRIPTION
1 - Sound Detection
FMIN
This is the input to the two FM demodulators. It
feeds two AGC amplifiers with a bandwidth of at
least 5-10MHz. There is one amplifier for each
channel both with the same input. The AGC ampli-
fiers have a 0dB to +40dB range.
ZIN = 5kΩ, Min input = 2mVPP per subcarrier.
Max input = 500mVPP (max when all inputs are
added together, when their phases coincide).
AGC L, AGC R
AGC amplifiers peak detector capacitor connec-
tions. The output current has an attack/decay ratio
of 1:32. That is the ramp up current is approxi-
mately 5μA and decay current is approximately
160μA. 11V gives maximum gain. These pins are
also driven by a circuit monitoring the voltage on
AMPLK L and AMPLK R respectively.
AMPLK L, AMPLK R
The outputs of amplitude detectors LEFT and
RIGHT . Each requires a capacitor and a resistor to
GND. The voltage across this is used to decide
whether there is a signal being received by the FM
detector. The level detector output drives a bit in
the detector I2 C bus control block.
AMPLK L and AMPLK R drive also respectively
AGC L and AGC R. For instance when the voltage
on AMPLK L is > (VREF + 1 VBE) it sinks current to
VREF from pin AGCL to reduce the AGC gain.
DET L, DET R
Respectively the outputs of the FM phase detector
left and right.
This is for the connection of an external loop filter
for the PLL. The output is a push-pull current
source.
CPUMP L, CPUMP R
The output from the frequency synthesizer is a
push-pull current source which requires a capacitor
to ground to derive a voltage to pull the VCO to the
target frequency. The output is ±100μA to achieve
lock and ±2μA during lock to provide a tracking time
constant of approximately 10Hz.
VREF
This is the audio processor voltage reference used
through out the FM/audio section of the chip. As
such it is essential that it is well decoupled to
ground to reduce as far as possible the risk of
crosstalk and noise injection. This voltage is de-
rived directly from the bandgap reference of 2.4V.
The VREF output can sink up to 500μA in normal
operation and 100μA when in stand-by.
IREF
This is a buffered VREF output to an off-chip resistor
to produce an accurate current reference, within
the chip, for the biasing of amplifiers with current
outputs into filters. It is also required for the Noise
reduction circuit to provide accurate roll-off fre-
quencies. This pin should not be decoupled as it
would inject current noise. The target current is
50μA ±2% thus a 47.5kΩ ±1% is required.
A 12V
Double bonded main power pin for the audio/FM
section of the chip. The two bond connections are
to the ESD and to power the circuit and on chip
regulators/references.
A GND L
This ground pin is double bonded : to channel LEFT : RF section & VCO, to both AGC amplifiers, channel LEFT and
RIGHT audio filter section.
A GND R
This ground pin is double bonded : to the volume control, noise reduction system,
ESD + Mux + VREF to channel right : RF section & VCO
STV0056AF
4/27
PIN DESCRIPTION (continued)
2 - Baseband Audio Processing
PK OUT L, PK OUT R, PK OUT
The noise reduction control loop peak detector
output requires a capacitor to ground from this pin,
and a resistor to VREF pin to give some accurate
decay time constant. An on chip 5kΩ ±25 % resistor
and external capacitor give the attack time.
PK IN L, PK IN R or PK IN
Each of these pins is an input to a control loop peak
detector and is connected to the output of the
offchip control loop band pass filter.
LEVEL L, LEVEL R
Respectively the audio left and right signals of the
FM demodulators are output to level L and level R
pins through an input follower buffer. The off-chip
filters driven by these pins must include AC cou-
pling to the next stage (PK IN L and PK IN R pins
respectively).
FC L, FC R
The variable bandwidth transconductance ampli-
fier has a current output which is variable depend-
ing on the input signal amplitude as defined by the
control loop of the noise reduction. The output
current is then dumped into an off-chip capacitor
which together with the accurate current reference
define the min/max rolloff frequencies. A resistor in
series with a capacitor is connected to ground from
these two pins.
J17 L, J17 R
The external J17 de-emphasis networks for chan-
nels left and right. The amplifier for this filter is
voltage input, current output. Output with ±500mV
input will be ±55μA. o perform J17 de-emphasis with the STV0042, an
external circuit is required.
U75 L, U75 R
External deemphasis networks for channels left
and right. For each channel a capacitor and resistor
in parallel of 75μs time constant are connected
between here and VREF to provide 75μs de-empha-
sis. Internally selectable is an internal resistor that
can be programmed to be added in parallel thereby
converting the network to approx 50μs de-empha-
sis (see control block map). The value of the inter-
nal resistors is 54kΩ ±30 %. The amplifier for this
filter is voltage input, current output ; with ±500mV
input the output will be ±55μA.
VOL L, VOL R
The main audio output from the volume control
amplifier the signal to get output signals as high as
2VRMS (+12dB) on a DC bias of 4.8V. Control is
from +12dB to -26.75dB plus Mute with 1.25dB
steps. This amplifier has short circuit protection and
is intended to drive a SCART connector directly via
AC coupling and meets the standard SCART drive
requirements. These outputs feature high imped-
ance mode for parallel connection.
S2 OUT L, S2 OUT R, S3 OUT L, S3 OUT R
These audio outputs are sourced directly from the
audio MUX, and as a result do not include any
volume control function. They will output a 1VRMS
signal biased at 4.8V. They are short circuit pro-
tected. These outputs feature high impedance
mode for parallel connection and meet SCART
drive requirement.
S2 RTN L, S2 RTN R, S3 RTN L, S3 RTN R
These pins allow auxiliary audio signals to be con-
nected to the audio processor and hence makes
use of the on-chip volume control. For additional
details please refer to the audio switching table.
STV0056AF
5/27
PIN DESCRIPTION (continued)
3 - Video Processing
B-BAND IN
AC-coupled video input from a tuner.
ZIN > 10kΩ ±25%. This drives an on-chip video
amplifier. The other input of this amp is AC
grounded by being connected to an internal VREF.
The video amplifier has selectable gain from 0dB
to 12.7dB in 63 steps and its output signal can be
selected normal or inverted.
UNCL DEEM
Deemphasized still unclamped output. It is also an
input of the video matrix.
VIDEEM1
Connected to an external de-emphasis network
(for instance 625 lines PAL de-emphasis).
VIDEEM2 / 22kHz
Connected to an external de-emphasis network
(for instance 525 lines NTSC or other video de-em-
phasis). Alternatively a precise 22kHz tone may be
output by I2 C bus control.
CLAMP IN
This pin clamps the most negative extreme of the
input (the sync tips) to 2.7VDC (or appropriate volt-
age). The video at the clamp input is only 1VPP.
This clamped video which is de-emphasised, fil-
tered and clamped (energy dispersal removed) is
normal, negative syncs, video. This signal drives
the Video Matrix input called Normal Video.
It has a weak (1.0μA ±15 %) stable current source
pulling the input towards GND. Otherwise the input
impedance is very high at DC to 1kHz ZIN > 2MΩ.
Video bandwidth through this is -1dB at 5.5MHz.
The CLAMP input DC restore voltage is then used
as a means for getting the correct DC voltage on
the SCART outputs.
S3 VID RTN
This input can be driven for instance by the de-
coder. This input has a DC restoration clamp on its
input. The clamp sink current is 1μA ±15% with the
buffer ZIN > 1MΩ.
S2 VID RTN, S1 VID RTN
External video input 1.0Vpp AC coupled 75Ω source
impedance. This input has a DC restoration clamp
on its input. The clamp sink current is 1μA ±15%
with the buffer ZIN > 1MΩ. This signal is an input to
the Video Matrix.
S1 VID OUT, S2 VID OUT
Video drivers for SCART 1 and SCART 2. An
external emitter follower buffer is required to drive
a 150Ω load. The average DC voltage to be 1.5V
on the O/P . The signal is video 2.0VPP 5.5MHz BW
with sync tip = 1.2V. These pins get signals from
the Video Matrix. The signal selected from the
Video Matrix for output on this pin is controlled by
a control register. This output also feature a high
impedance mode for parallel connection.
S3 VID OUT
This output can drive for instance a decoder. Also
it is able to pass 10MHz ; ZOUT < 75Ω. Video on
this pin will be 2VPP. The black level of the ouput
video signal can be adjusted through I2 C bus con-
trol to easily interface with on-board Videocrypt
decoder. This output feature an high impedance
mode for parallel connection.
V 12V
+ 12V double bonded : ESD+guard rings and video
circuit power.
V GND
Doubled bonded. Clean VID IN GND. Strategically
placed video power ground connection to reduce
video currents getting into the rest of the circuit.
4 - Control Block
GND 5V
The main power ground connection for the control
logic, registers, the I2 C bus interface, synthesizer
& watchdog and XTLOSC.
VDD 5V
Digital +5V power supply.
SCL
This is the I2 C bus clock line. Clock = DC to 100kHz.
Requires external pull up eg. 10kΩ to 5V.
SDA
This is the I2 C bus data line. Requires external pull
up eg. 10kΩ to 5V.
I/O / 22kHz
General purpose input output pin or 22kHz output.
XTL
This pin allows for the on-chip oscillator to be either
used with a crystal to ground of 4MHz or 8MHz, or
to be driven by an external clock source. The
external source can be either 4MHz or 8MHz. A
programmable bit in the control block removes a ÷2
block when the 4MHz option is selected.
Hardware address with internal 135μA pull down.
Chip address is 06 when this pin is grouded and
chip address is 46 when connected to VDD.
STV0056AF
6/27
GENERAL BLOCK DIAGRAM
VIDEO PROCESSING BLOCK DIAGRAM
STV0056AF
7/27
AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL RIGHT)
AUDIO PROCESSING BLOCK DIAGRAM (CHANNEL LEFT)
STV0056AF
8/27
AUDIO SWITCHING :a→ ANRS input non-scrambled audio→ ANRS input descrambled audio
FM DEMODULATION BLOCK DIAGRAM
STV0056AF
9/27
CIRCUIT DESCRIPTION
Video Section
The composite video is first set to a standard level
by means of a 64 step gain controlled amplifier. In
the case that the modulation is negative, an inverter
can be switched in.
One of two different external video de-emphasis
networks (for instance PAL and NTSC) is select-
able by an integrated bus controlled switch.
Then energy dispersal is removed by a sync tip
clamping circuit, which is used on all inputs to a
video switching matrix, thus making sure that no
DC steps occur when switching video sources.
The matrix can be used to feed video to and from
decoders, VCR’s and TV’s.
A bus controlled black level adjustment circuit is
provided on the decoder output allowing a direct
connection to an on-board Videocrypt decoder.
Additionaly all the video outputs are tristate type
(high impedance mode is supported), allowing a
simple parallel connections to the scarts (Twin
tuner applications).
Audio Section
The two audio channels are totally independent
except for the possibility given to output on both
channels only one of the selected input audio chan-
nels. o allow a very cost effective application, each
channel uses PLL demodulation. Neither external
complex filter nor ceramic filters are needed.
The frequency of the demodulated subcarrier is
chosen by a frequency synthesizer which sets the
frequency of the internal local oscillator by com-
paring its phase with the internally generated
reference. When the frequency is reached, the
microprocessor switches in the PLL and the de-
modulation starts. At any moment the microproces-
sor can read from the device (watchdog registers)
the actual frequency to which the PLL is locked. It
can also verify that a carrier is present at the wanted
frequency (by reading AMPLK status bit) thanks to
a synchronous amplitude detector, which is also
used for the audio input AGC.
In order to maintain constant amplitude of the
recovered audio regardless of variations between
satellites or subcarriers, the PLL loop gain may be
programmed from 56 values.
Any frequency deviation can be accomodated
(from ±30kHz till ±400kHz).
Two different networks can be permanently con-
nected for either 75μs or J17 de-emphasis. If 50μs
de-emphasis is required, this can be inserted by an
internal switch, thus allowing a worldwide applica-
tion.
The STV0056AF is intended to be compatible with
Wegener Panda System.
Two types of audio outputs are provided : one is a
fixed 1VRMS and the other is a gain controlled
2VRMS max. The control range being from +12dB
to -26.75dB with 1.25dB steps. This output can also
be muted.
A matrix is implemented to feed audio to and from
decoders VCR’s and TV’s.
Noise reduction system and de-emphasis can be
inserted or by-passed through bus control.
Also all the audio outputs are tristate-type (high
impedance mode is supported), allowing a simple
parallel connections to the scarts (Twin tuner appli-
cations).
Others
A 22kHz tone is generated for LNB control.
It is selectable by bus control and available on one
of the two pins connected to the external video
de-emphasis networks. One general purpose I/O
is also available on the STV0056AF.
By means of the I2 C bus there is the possibility to
drive the ICs into a low power consumption mode
with active audio and video matrixes. Inde-
pendantly from the main power mode, each indi-
vidual audio and video output can be driven to high
impedance mode.
STV0056AF
10/27
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
DC AND AC ELECTRICAL CHARACTERISTICS
(VCC = 12V, VDD = 5V, Tamb = 25o C unless otherwise specified)
AUDIO DEMODULATOR
AUTOMATIC NOISE REDUCTION SYSTEM
STV0056AF
11/27
DC AND AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 12V, VDD = 5V, Tamb = 25o C unless otherwise specified)
AUDIO OUTPUT (Pins VOL OUT R, VOL OUT L)
AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L, S3 OUT R, S3 OUT L)
STV0056AF
12/27
DC AND AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 12V, VDD = 5V, Tamb = 25o C unless otherwise specified)
AUXILIARY AUDIO OUTPUT (Pins S2 OUT R, S2 OUT L, S3 OUT R, S3 OUT L) (continued)
I/O
RESET
COMPOSITE SIGNAL PROCESSING
CLAMP STAGES (Pins CLAMP IN, S1, S2, S3 VID RTN)
VIDEO MATRIX
STV0056AF
13/27
Figure 1
Figure 2
Figure 3
Figure 5
Figure 6
PIN INTERNAL CIRCUITRY
S1 VID RTN, S2 VID RTN, S3 VID RTN,
CLAMP IN
50μA source is active only when VIDIN < 2.7V.
S3 VID OUT
I black level is I2 C programmable from source 16μA
to sink 33μA equivalent to an offset voltage of
-150mV to + 300mV. The 60Ω collector resistor is
for short cct. protection.
S1 VID OUT, S2 VID OUT
Same as above but with no black level adjustment.
UNCL DEEM
Same as above but with no black level adjustment
and slightly different gain.
VIDEEM1
Ron of the transistor gate is ≈10kΩ.
VIDEEM2 / 22kHz
Ron of the transistor gate is ≈10kΩ.
Figure 4
Figure 7
VID IN
STV0056AF
14/27

Partno	Mfg	Dc	Qty	Available	Descript
STV0056AF	ST	N/a	960	avai	SATELLITE SOUND AND VIDEO PROCESSOR