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STV0042A/Z
ANALOG SATELLITE SOUND AND VIDEO PROCESSOR
STV0042A/ZAnalog Satellite Sound and Video Processor
Sound Features Two Independent Sound Demodulators PLL Demodulation with 5-10 MHz Frequency
Synthesis Programmable FM Demodulator Bandwidth
accommodating FM Deviations between ±30
and ±400 kHz Programmable 50/75 μs or No De-emphasis Dynamic Noise Reduction (ANRS) One or Two Auxiliary Audio Inputs and
Outputs Gain-controlled and Mutable Audio Outputs High-impedance Mode Audio Outputs for
Twin Tuner Applications
Video Features Composite 6-bit Video with 0 to 12.7 dB Gain
Control Selectable Composite Video Inverter Two Selectable Video De-emphasis Networks 4 x 2 Video Matrix High-impedance Mode Video Outputs for
Twin Tuner Applications
Miscellaneous Features22 kHz Tone Generation for LNB Control I²C Bus Control: Chip Addresses = 06h Low Power Stand-by Mode with Active Audio
and Video Matrices
General DescriptionThe STV0042 BICMOS integrated circuit is
designed for low-cost analog satellite receiver
applications.
The STV0042A/Z performs all the necessary signal
processing from the tuner to the Audio/Video input
and output connectors regardless of the satellite
system.
STV0042A/Z able of Contents
Chapter 1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31.1 Pin Description ..................................................................................................................3
Chapter 2 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chapter 3 Input/Output Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Chapter 4 I²C Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194.1 Writing to the Chip ..............................................................................................................19
4.2 Reading from the Chip .......................................................................................................19
Chapter 5 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Chapter 6 FM Demodulation Software Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256.1 Detailed Description ...........................................................................................................25
Chapter 7 Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Chapter 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308.1 Absolute Maximum Ratings ..............................................................................................30
8.2 Thermal Data ....................................................................................................................30
8.3 Electrical Characteristics ....................................................................................................30
Chapter 9 Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Chapter 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
STV0042A/Z General Information General Information
1.1 Pin Description
Figure 1: Pin Connections
Table 1: Pin Description (Sheet 1 of 2)
General Information STV0042A/Z
Table 1: Pin Description (Sheet 2 of 2)
STV0042A/Z General Information
1.1.1 Sound Detection
1.1.1.1 FM DemodulatorsA block diagram of the FM Demodulation block is shown in Figure3.
Pin FMIN (pin 20) is the input to the two FM demodulators. It feeds two AGC amplifiers with a
bandwidth of at least 5 to 10 MHz. There is one amplifier for each channel. Both channels have the
same input. The AGC amplifiers have a range between 0 and +40 dB.
The input impedance (ZIN ) is 5 kΩ with a minimum input of 2 mVPP per subcarrier and a maximum
input of 500 mVPP . This is the maximum value when all inputs are added together, when their
phases coincide.
1.1.1.2 AGC Peak Detector CapacitorsPins AGCL and AGCR (pins 21 and 31, respectively) are the AGC amplifier peak detector capacitor
connections. The output current has an attack/decay ratio of 1:32. This means that the ramp-up
current is approximately 5 μA and decay current is approximately 160 μA. 11V gives maximum
gain. These pins are also driven by a circuit monitoring the voltage on pins AMPLKL and AMPLKR,
respectively.
1.1.1.3 Amplitude Detector Capacitors Pins AMPLKL and AMPLKR (pins 30 and 35, respectively) are the left and right outputs of their
respective amplitude detectors. Each pin requires a capacitor and a resistor to GND. The voltage
across these pins is used to decide whether a signal is being received by the FM detector. The level
detector output drives a bit in the I²C bus detector control block. Pins AMPLKL and AMPLKR drive
also respectively pins AGCL and AGCR. For instance, when the voltage on pin AMPLKL is > (VREF
+ 1 V ) it sinks current to V from pin AGCL in order to reduce the AGC gain.
Figure 2: STV0042A/Z General Block Diagram
General Information STV0042A/Z
1.1.1.4 FM PLL Filters Pins DETL and DETR (pins 28 and 36, respectively) are the left and right outputs of their respective
FM phase detectors. These pins are used to connect an external PLL loop filter. The output is a
push-pull current source.
1.1.1.5 FM PLL Charge Pump Capacitors Pins CPUMPL and CPUMPR (pins 27 and 38, respectively) are the FM PLL Charge Pump
Capacitors. The output from the frequency synthesizer is a push-pull current source which requires
capacitors to pull each VCO to the target frequency. The output is ±100 μA to achieve lock and μA during lock to provide a tracking time constant of approximately 10 Hz.
In order to prevent a false locking in certain marginal conditions, it is best to add a 8.2V
Zener diode to pins CPUMPL and CPUMPR.
Figure 3: FM Demodulation
STV0042A/Z General Information
1.1.1.6 Voltage Reference Pin VREF (pin 33) is the audio processor voltage reference used throughout the FM/audio section
of the chip. This pin must be correctly decoupled from to ground in order to reduce as much as
possible the risk of crosstalk and noise injection. This voltage reference is directly derived from the
bandgap reference of 2.4 V. The VREF output can sink up to 500 μA in normal operation and 100 μA
when in Standby mode.
1.1.1.7 Current Reference Resistor Pin IREF (pin 39) is a buffered VREF output to an off-chip resistor used to produce an accurate
current reference, within the chip, for the biasing of amplifiers with current outputs into filters. It also
provides accurate roll-off frequencies for the Noise Reduction circuit.
This pin should not be decoupled as this would inject current noise. The target current is 50 μA
±2%, therefore a 47.5 kΩ ±1% resistor is required.
1.1.1.8 12 V Audio Power SupplyPin A12V (pin 34) is a double-bonded main power pin used by the Audio/FM section of the chip. The
two bond connections are used for the ESD and to power the circuit and on-chip regulators/
references.
1.1.1.9 Audio Ground Pins AGNDL and AGNDR (pins 32 and 42, respectively) are double-bonded ground pins.
1.1.2 Baseband Audio Processing
1.1.2.1 Noise Reduction Peak Detector The Noise Reduction Control Loop Peak Detector output (PKOUT pin (pin 40)) is connected to a
capacitor to ground and to a resistor to the VREF pin in order to provide an accurate decay time
constant. An on-chip 5 kΩ ±25% resistor and external capacitor give the attack time.
Pin PKIN (pin 2) is an input to a control loop peak detector and is connected to the output of the off-
chip control loop band pass filter.
1.1.2.2 Noise Reduction Summing OutputA 0.5-gain amplifier is used to sum together the two audio demodulated signals. This value is then
output on pin SUMOUT (pin 3). For example, if both inputs are equal to 1 V, then the output is 1V.
This amplifier has an input follower buffer which provides a VBE offset in the DC bias voltage.
Therefore, the filter driven by this amplifier must include AC coupling to the next stage (pin PKIN).
1.1.2.3 Audio Roll-off The variable bandwidth transconductance amplifier has a current output which is variable
depending on the input signal amplitude as defined by the ANRS control loop. The output current is
then dumped into an off-chip capacitor which together with the accurate current reference define
General Information STV0042A/Zthe minimum/maximum roll-off frequencies. A resistor in series with a capacitor is connected to the
ground via pins FCL and FCR (pins 41 and 1, respectively).
1.1.2.4 De-emphasis Time Constants Pins U75L and U75R (pins 29 and 37, respectively) are external de-emphasis networks for left and
right channels. For each channel, a capacitor and resistor in parallel with a 75 μs time constant are
connected to the VREF to provide a 75 μs de-emphasis. An internal resistor can be programmed to
be added in parallel thereby converting the network to approximately 50 μs de-emphasis. The value
of the internal resistors is 30 kΩ ±30%. The amplifier for this filter is voltage input, current output;
with ±500 mV input the output will be ±55 μA.
1.1.2.5 Volume-controlled Audio Outputs Pins VOLL and VOLR (pins 7 and 4, respectively) are the main audio outputs from the volume
control amplifier. Output signals may be as high as 2V RMS (+12 dB) with a DC bias of 4.8 V. The
volume control is between +12 dB and -26.75 dB in steps of 1.25 dB with possible Mute. This
amplifier has short-circuit protection and is intended to drive a SCART connector directly via AC
coupling and meets the standard SCART drive requirements. These outputs feature high
impedance mode for parallel connections.
1.1.2.6 Fixed-level Audio Outputs Pins S2OUTL and S2OUTR (pins 9 and 11, respectively) are audio outputs that are directly sourced
from the audio multiplexer, and as a result do not include any volume control functions. They will
output a 1V RMS signal biased at 4.8 V. They are short-circuit protected. These outputs feature high
impedance mode for parallel connections and meet SCART drive requirements.
Figure 4: Audio Switching
STV0042A/Z General Information
1.1.2.7 Auxiliary Audio ReturnsPins S2RTNL and S2RTNR (pins 18 and 19, respectively) allow auxiliary audio signals to be
connected to the audio processor and therefore make use of the on-chip volume control. For
additional details please refer to the audio switching table.
Figure 5: Audio Signal Processing Diagram (Left)
General Information STV0042A/Z
1.1.3 Video ProcessingA block diagram of the Video Processing block is shown in Figure7.
1.1.3.1 Base Band Input Pin BBANDIN (pin 17) is an AC-coupled video input from a tuner with an impedance greater than kΩ ±25%. This pin drives an on-chip video amplifier. The other input of this amplifier is AC
grounded via an internal connection to pin VREF. The video amplifier has selectable gain from 0 dB
to 12.7 dB in 63 steps and its output signal can be selected as normal or inverted.
1.1.3.2 Unclamped De-emphasized Video Output Pin UNCLDEEM (pin 12) is an unclamped de-emphasized video output. It is also an input of the
video matrix.
1.1.3.3 Sync Tip Clamp Input Pin CLAMPIN (pin 10) clamps the extreme negative values (the sync tips) of the input signal to
2.7VDC (or the appropriate voltage). The video at the clamp input is only 1VPP . This clamped video
which is de-emphasized, filtered and clamped (energy dispersal removed), is a normal video signal
with negative synchronization. This signal drives the Video Matrix input called Normal Video. It has
a weak (1.0 μA ±15%) stable current source pulling the input towards the ground. Otherwise, the
input impedance is very high at DC to 1 kHz ZIN> 2 MΩ. Video bandwidth through this pin is -1 dB
at 5.5 MHz. The clamp input DC restore voltage is then used to obtain the correct DC voltage on the
SCART outputs.
1.1.3.4 Video De-emphasis 1Pin VIDEEM1 (pin 15) is connected to an external de-emphasis network (for instance, 625 lines
PAL de-emphasis).
Figure 6: Audio Signal Processing Diagram (Right)
STV0042A/Z General Information
1.1.3.5 Video De-emphasis 2 or 22 kHz OutputPin VIDEEM2/22KHZ (pin 13) is connected to an external de-emphasis network (for instance, 525
lines NTSC or other video de-emphasis). Alternatively, a precise 22 kHz tone may be output by I²C
bus control.
1.1.3.6 VCR SCART Video ReturnPin S2VIDRTN (pin 8) is an external video input 1.0VPP AC-coupled 75 Ω source impedance. This
input has a DC restoration clamp on its input. The clamp sink current is 1 μA ±15% with the input
buffer impedance greater than 1 MΩ. This is the input signal to the Video Matrix.
1.1.3.7 SCART Video Outputs Pins S1VIDOUT and S2VIDOUT (pins 5 and 6, respectively) are video drivers for SCART 1 and
SCART 2. An external emitter follower buffer is required to drive a 150-Ω load. The average DC
voltage must be 1.5 V on the outputs. The video signal is 2.0VPP with a 5.5 MHz bandwidth with
1.2 V sync tips. These pins receive the signals sent from the Video Matrix. The signal that will be
output from the Video Matrix is controlled by a control register. These outputs also feature High
Impedance mode for parallel connections.
1.1.3.8 12V Video Power SupplyPin V12V (pin 14) is a double-bonded 12-V video power supply with ESD and guard rings.
1.1.3.9 V GNDPin VGND (pin 16) a strategically placed double-bonded video power ground connection used to
reduce video currents getting into the rest of the circuit.
General Information STV0042A/Z
1.1.4 Control Block
1.1.4.1 5-V GroundPin GND5V (pin 26) is the main power ground connection for the control logic registers, the I²C bus
interface, synthesizer, watchdog and the crystal oscillator.
1.1.4.2 5-V Digital Power SupplyPin VDD5V (pin 25) is a digital 5-V power supply.
1.1.4.3 SCLThis pin (pin 22) is the I²C bus clock line. It requires an external pull-up (for example, 10 kΩ at 5V).
Clock = DC to 100 kHz.
1.1.4.4 SDAThis pin (pin 23) is the I²C bus data line. It requires an external pull-up (for example, 10 kΩ at 5V).
1.1.4.5 4/8 MHz Quartz Crystal or Clock InputPin XTL (pin 24) allows the on-chip oscillator to be either used with a 4 MHz or 8 MHz crystal
oscillator connected to ground or to be driven by an external clock source. The external source can
be either 4 MHz or 8 MHz. A programmable bit in the control block removes a ÷2 block when the MHz option is selected.
Figure 7: Video Processing Block Diagram
STV0042A/Z Circuit Description Circuit Description
2.0.1 Video SectionThe composite video is first set to a standard level by means of a 64-step gain-controlled amplifier.
If the modulation is negative, an inverter can be switched in.
One of two different external video de-emphasis networks (for instance PAL and NTSC) is
selectable by an integrated bus controlled switch. Then energy dispersal is removed by a sync tip
clamping circuit, which is used on all inputs to a video switching matrix, thus making sure that no DC
steps occur when switching video sources.
The matrix can be used to feed video to and from decoders, VCRs and TVs.
Additionally, all the video outputs are tri-state type (high impedance mode is supported), allowing a
simple parallel connections to the SCART s (Twin tuner applications).
2.0.2 Audio SectionThe two audio channels are totally independent except for the possibility given to output on both
channels only one of the selected input audio channels.
To allow a very cost-effective application, each channel uses PLL demodulation. Neither external
complex filter nor ceramic filters are needed.
The frequency of the demodulated subcarrier is chosen by a frequency synthesizer which sets the
frequency of the internal local oscillator by comparing its phase with the internally generated
reference. When the frequency is reached, the microprocessor switches in the PLL and the
demodulation starts. At any moment the microprocessor can read from the device (watchdog
registers) the actual frequency to which the PLL is locked. It can also verify that a carrier is present
at the wanted frequency (by reading AMPLK status bit) thanks to a synchronous amplitude detector,
which is also used for the audio input AGC.
In order to maintain constant amplitude of the recovered audio regardless of variations between
satellites or subcarriers, the PLL loop gain may be programmed from 56 values.
Any frequency deviation can be accommodated between ±30 and ±400 kHz.
In the typical application, the STV0042A/Z offers two audio de-emphasis 75 μs and 50 μs. When
required a J17 de-emphasis can be implemented by using specific application diagram (see
Application Note: AN838, Chapter 4.2).
A dynamic noise reduction system (ANRS) is integrated into the STV0042A/Z using a low-pass
filter, the cut-off frequency of which is controlled by the amplitude of the audio after insertion of a
bandpass filter.
Two types of audio outputs are provided: one is a fixed 1V RMS and the other is a gain-controlled RMS max. The control range is between +12 and -26.75 dB in steps of 1.25 dB. This output can
also be muted.
A matrix is implemented to feed audio to and from decoders, VCRs and TVs.
Noise reduction system and de-emphasis can be inserted or by-passed through bus control.
Also all the audio outputs are tri-state-type (high impedance mode is supported), allowing a simple
parallel connections to the SCARTs (Twin tuner applications).
Circuit Description STV0042A/Z
2.0.3 Other FeaturesA 22kHz tone is generated for LNB control. It is selectable by bus control and available on one of
the two pins connected to the external video de-emphasis networks.
By means of the I2 C bus there is the possibility to drive the ICs into a low power consumption mode
with active audio and video matrixes. Independently from the main power mode, each individual
audio and video output can be driven to high impedance mode.
STV0042A/Z Input/Output Diagrams Input/Output Diagrams
Figure 8: S2VIDRTN and CLAMPIN Pins1 The 50 μA source is active only when
VIDIN< 2.7 V.
Figure 9: S1VIDOUT and S2VIDOUT Pins1 Same as Figure 8, but with no Black Level
Adjustment.
Figure 10: VIDEEM1 Pin1
Figure 11: UNCLDEEM Pin1 Same as Figure 9, but with a slightly different
gain.
Figure 12: FCL and FCR Pins1 IVAR is controlled by the maximum peak
detection audio level ±15 μA (1 VPP audio).
Figure 13: S2OUTL and S2OUTR Pins1 Same as Figure 17, but with gain fixed atdB.
Input/Output Diagrams STV0042A/Z
Figure 14: VIDIN Pin
Figure 15: PKOUT Pin
Figure 16: S2RTNL and S2RTNR Pins1 4.8V bias voltage is the same as the bias level
on the audio outputs.
Figure 17: VOLOUTR and VOLOUTL Pins1 Audio output with volume and SCART driver
with +12 dB gain for up to 2 VRMS. The Op
Amp has a push-pull output stage.
Figure 18: VIDEEM2 / 22kHz Pin1 RON of the transistor gate is ≈10 kΩ.
Figure 19: FMIN Pin1 The other input for each channel is internally
biased in the same way via 10 kΩ to the 2.4V
VREF.
Figure 20: IREF Pin1 The optimum value if IREF is 50 μA ±2% so
an ext. resistor of 47.5 kΩ ±1% is required.
Figure 21: DETL and DETR Pins1I - I = f (phase error).
STV0042A/Z Input/Output Diagrams
Figure 22: SCL Pin1 This is the input to a Schmitt input buffer made
with a CMOS amplifier.
Figure 23: SDA Pin1 Input same as above. Output pull down only,
relies on external resistor for pull-up.
Figure 24: U75L and U75R Pins1I1 - I2 = 2 x Audio / 18 kΩ. e.g. 1VPP Audio:
±55 μA. There are internal switches to match
the audio level of the different standards.
Figure 25: XTL Pin
Figure 26: CPUMPL and CPUMPR Pins1 An offset on the PLL loop filter will cause an
offset in the two 1 μA currents that will prevent
the PLL from drifting-off frequency.
Figure 27: AMPLKL, AMPLKR, AGCL and AGCR
Pins1I2 and I1 from the amplitude detecting mixer.
Figure 28: VREF Pin1 The 400 μA source is off during stand-by
mode.
Input/Output Diagrams STV0042A/Z
Figure 29: SUMOUT Pin
Figure 30: PKIN Pin
Figure 31: V12V, VGND, VDD5V, GND5V, AGNDL,
A12V and AGNDR Pins1 Refer to Table2.
Table 2: Double-buffered Supply Pins A third bond wire on this pin is connected directly to the die pad (substrate).
STV0042A/Z I²C Protocol I²C Protocol
4.1 Writing to the Chip
S-Start Condition
P-Stop Condition
CHIP ADDR - 7 bits. 06H Write/Read bit is the 8th bit of the chip address.
ACKNOWLEDGE after receiving 8 bits of data/address.
REG ADDR Address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are ’X’
or don’t care i.e. only the first 3 bits are used.
DATA 8 bits of data being written to the register. All 8 bits must be written to at the
same time.
REG ADDR/A/DATA/A Can be repeated, the write process can continue until terminated with a
STOP condition. If the REG ADDR is higher than 07 then IIC PROTOCOL
will still be met (i.e. an A generated).
4.2 Reading from the ChipWhen reading, there is an auto-increment feature. This means any read command always starts by
reading Reg 8 and will continue to read the following registers in order after each acknowledge or
until there is no acknowledge or a stop. This function is cyclic that is it will read the same set of
registers without re-addressing the chip. There are two modes of operation as set by writing to bit 7
of register 0. Read 3 registers in a cyclic fashion or all 5 registers in a cyclic fashion. Note only the
last 5 of the 11 registers can be read.
Reg0 bit 7 = L → Start / chip add / R / A / Reg 8 / A / Reg 9 / A / Reg 0A / A / Reg 8 / A / Reg 9
/ A / Reg 0A /... / P /
Reg0 bit 7 = H → Start / chip add / R / A / Reg 8 / A / Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6
/ A / Reg 8 / A / Reg 9 / A / Reg 0A / A / Reg 7 / A / Reg 6 / ... / P /
Table 3: Example
