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STSR2P-STSR2PCD-STSR2PMCD-STSR2PMCD-TR
FORWARD SYNCHRONOUS RECTIFIERS SMART DRIVER
1/12September 2003 SUPPLY VOLTAGE RANGE: 4.5V TO 5.5V TYPICAL PEAK OUTPUT CURRENT:
SOURCE -2A, SINK 3.5A OPERATING FREQUENCY:20 TO 750 KHZ SMART TURN-OFF ANTICIPATION TIMING OPERATION INDEPENDENT FROM THE
FORWARD MAGNETIC RESET TECHNIQUE POSSIBILITY TO OPERATEIN
DISCONTINUOUS MODE
DESCRIPTIONSTSR2P Smart Driver IC provides two
complementary high current outputs to drive
Power Mosfets. TheICis dedicatedto properly
drive secondary Synchronous Rectifiers in
medium power, low output voltage, high efficiency
Forward Converters. Froma synchronizing clock
input, STSR2P generates two driving signals with
the self-setting of dead time between
complementary pulses. TheIC operation prevents
secondary side shoot-through conditions
providing proper timingat the outputs turn-off
transition. This smart function operates througha
fast cycle-after-cycle control logic mechanism
based on an internal high frequency oscillator,
synchronized by the clock signal. A fixed
anticipation in turning-off the OUT GATE1 with
respectto the clock signal transitionis provided,
while the anticipationin turning off the OUT GATE2can be set through external components. The
adopted transitions revelation mechanism makes
circuit operation independent by the forward
magnetic reset technique used, avoiding mostof
the common problems inherent in self-driven
synchronous rectifiers.A special Inhibit function
allows the shut-offof OUT GATE2. This feature
makes discontinuous conduction mode possible
and prevents the freewheeling mosfet from
sinking current from the output.
STSR2P automatically turnsoff the outputs when
duty-cycleis lower than 13%, while STSR2PM
works evenat very low duty-cycle values.
STSR2P/STSR2PMFORWARD SYNCHRONOUS
RECTIFIERS SMART DRIVER
SCHEMATIC DIAGRAM
STSR2P/STSR2PM2/12
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device may occur. Functional operation under these conditionis
not implied.
(*)A higher positive voltage level canbe appliedtothepin witha resistor which limitsthe current flowingintothepinto 10mA maximum
THERMAL DATA(*) This valueis referredtoone layerpcb board with minimum copper connectionsforthe leads.a minimum valueof 120 °C/Wcanbe
obtained improving thermal conductivityofthe board
ORDERING CODES
CONNECTION DIAGRAM (top view)
STSR2P/STSR2PM3/12
PIN DESCRIPTION
STSR2P/STSR2PM4/12
ELECTRICAL CHARACTERISTICS(VCC =5V, CK= 250kHz,V INHIBIT =-200mV,TJ =-40to 125°C, unless
otherwise specified.)
Note1:tRis measured between 10% and 90%ofthe final voltage;tFis measured between 90% and 10%onthe initial voltage
Note2: Parameter guaranteedby design
STSR2P/STSR2PM5/12
TIMING DIAGRAM
APPLICATION INFORMATION: STSR2IN FORWARD CONVERTER SECONDARY SIDENOTES Ceramic CapacitorsC1andC2 mustbe placed very closetotheIC;R1 andR2set theanticipationtimeby partitioning theVCC voltage;R3andR4isa resistor divider meantto providethe correctCK voltage range;R5 limitsthe current flowing through diodeD2 when Freewheeling drain voltageis high;D1 couldbe necessaryto protect INHIBITpin from negative voltages.D2 couldbe necessaryto protect INHIBITpin from voltages higher than VCCD3 couldbe necessaryto protectCKpin from voltages higher than VCC. SGLGND layout trace mustnot include OUTGATE1,2 current paths.A capacitorin parallel withR4 couldbe necessaryto eliminate turnoff voltage spike.
STSR2P/STSR2PM6/12
EXAMPLE OF COMPONENTS SELECTION FORA FORWARD CONVERTERForward Specification:IN =36-72V
VOUT=3.3V
n=Np/Ns=4.53 andR4 are calculated assuringa minimum voltageof 2.8Vat CK pin.At 36V input, the voltageon the
secondary windingis 36/4.5=8V. Choosing R3=1.5KΩ,R4 resultsto be:
R4=1kΩis chosen.At 72V input the currentat CK pinis calculated as:
This valueis below the maximum allowable current flowing into the CK pin (10mA).If the 10mA valueis
exceededan external diode connectedtoVCC mustbe added (D3). and R2 values set the anticipation time for OUTGATE2.For R1=∞ and R2=0, tANT2=75ns; for
R1=R2=10kΩ,tANT2=150ns;for R1=0 and R2=∞,tANT2=225ns.
The RC group composed byR5 and the parasitic capacitanceof Inhibit pin (typically 5pF) delays the
signal on Inhibit comparator. This delay mustbe lower than 200ns. This condition imposesa maximum
value forR5of about 20kΩ. generala suggested value forR5is 10kΩ.At 72V input, the secondary voltageis 16V,so the maximum
current flowing into Inhibit pinis 16V/10kΩ=1.6mA whichis below the maximum allowable currentfor the
pin (10mA).If the 10mA valueis exceededan external diode (D2) connectedto VCC mustbe added.
The maximum negative voltageof –0.6V mustbe guaranteed for the Inhibit pin.If this negative voltageis
exceeded the current mustbe limitedto 50mA.If necessary,a diode (D1) connectedto SGLGND canbe
addedto satisfy this specification.
INHIBIT OPERATION OF OUTGATE2IN DISCONTINUOUS CONDUCTION MODE4CK R3×INICK2.8()– R3 VCK–×--------------- --------------- --------------- -------------------≥ 1kΩ 2.8V 1.5kΩ()× 220μA– 1.5kΩ 2.8V–×--------------- --------------- --------------- ---------------- -------------× 862Ω==CKIN max() VCC– 0.3–3
--------- --------------- --------------- -------------- 16 5– 0.3–
1.5kΩ------------------------------ 7.13mA== =
