STPM10BTR ,Programmable single phase energy metering IC with tamper detectionFeatures■ Measures active, reactive, and apparent energies■ Current, voltage RMS and instantaneous ..
STPR1020 ,ULTRA-FAST RECOVERY RECTIFIER DIODESapplications.ABSOLUTE MAXIMUM (limiting values, per diode)Symbol Parameter Value UnitRepetitive pea ..
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STPR1020CB ,ULTRA-FAST RECOVERY RECTIFIER DIODESapplications.ABSOLUTE MAXIMUM (limiting values, per diode)Symbol Parameter Value UnitRepetitive pea ..
STPR1020CF ,ULTRA-FAST RECOVERY RECTIFIER DIODESapplications.ABSOLUTE MAXIMUM (limiting values, per diode)Symbol Parameter Value UnitRepetitive pea ..
STPR1020CF. ,ULTRA-FAST RECOVERY RECTIFIER DIODESapplications.ABSOLUTE MAXIMUM (limiting values, per diode)Symbol Parameter Value UnitRepetitive pea ..
T1006NL , TELECOMMUNICATIONS PRODUCTS
T1007 , TELECOMMUNICATIONS PRODUCTS
T1007NL , TELECOMMUNICATIONS PRODUCTS
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STPM10BTR
Programmable single phase energy metering IC with tamper detection
January 2013 Doc ID 17728 Rev 4 1/53
STPM10Programmable single-phase energy metering IC
with tamper detection
Datasheet − production data
Features Measures active, reactive, and apparent
energies Current, voltage RMS and instantaneous
measurement Frequency measurement Ripple-free active energy pulsed output Live and neutral monitoring for tamper
detection Fast and simple one-point digital calibration
over the whole current range Integrated linear voltage regulators for digital
and analog supply Selectable RC or crystal oscillator Supports 50 - 60 Hz - IEC62052-11, IEC62053-
2x specifications Less than 0.1% error in the 1000:1 range Precision voltage reference: 1.23 V with 30
ppm/°C max
DescriptionThe STPM10 is designed for effective
measurement of active, reactive and apparent
energy in a power line system using current
transformer and shunt sensors. The device can
be implemented for peripheral measurement in a
microcontroller-based single-phase or poly-phase
energy meter. The STPM10 consists of two main
sections: analog and digital. The analog part is
composed of preamplifier and first-order sigma-
delta A/D converter blocks, a band-gap voltage
reference and low-drop voltage regulator. The
digital part is composed of system control,
oscillator, hard-wired DSP and SPI interface.
There is also an internal volatile memory, which is
controlled through the SPI by means of a
dedicated command set. The configured bits are
used for configuration and calibration purposes.
From a pair of sigma-delta output signals
produced by the analog section, the DSP unit
computes the amount of active, reactive and
apparent energy consumed, as well as the RMS
and instantaneous voltage and current values.
The results of the computation are available as
pulse frequencies and states on the digital
outputs of the device, or as data bits in a data
stream, which can be read from the device by
means of the SPI interface. The system bus
interface is also used for temporary programming
of bits of internal volatile memory. The STPM10
generates an output signal with a pulse frequency
proportional to the energy, and this signal is used
in the calibration phase of the energy metering
application.
Table 1. Device summary
Contents STPM102/53 Doc ID 17728 Rev 4
Contents Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125.1 Measurement error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 ADC offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Power supply DC and AC rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.5 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.1 General operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 ΣΔ A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.4 Zero-crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5 Period and line voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.6 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.7 Load monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.8 Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.9 Tamper detection module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.9.1 Detailed operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.10 Phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.11 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.11.1 RC startup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.12 Resetting the STPM10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.13 Using the STPM10 in microcontroller-based meters . . . . . . . . . . . . . . . . 26
STPM10 ContentsDoc ID 17728 Rev 4 3/53
7.14 Energy to frequency conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.15 Status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.16 Programming the STPM10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.16.1 Data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.17 Configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.18 Mode signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.19 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.20 Remote reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.21 Reading data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.22 Writing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.22.1 Interfacing the standard 3-wire SPI with the STPM10 SPI . . . . . . . . . . 38
7.23 Energy calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.23.1 Active power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.23.2 Reactive power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.23.3 Apparent power and RMS values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.24 STPM10 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Application design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
List of tables STPM10
4/53 Doc ID 17728 Rev 4
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Gain of voltage and current channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Configuration of current sensors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. No-load detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. LED pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Status bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Configuration bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 12. Mode signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Working point settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 14. Device constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 15. Resistor divider ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 16. Current channel typical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 17. Footprint data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STPM10 List of figures
Doc ID 17728 Rev 4 5/53
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Supply current vs. supply voltage, TA = 25 °C (f = 4.194MHz, 8.192MHz) . . . . . . . . . . . . 13
Figure 4. RC oscillator frequency vs. VCC,
R = 12 kW, TA = 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. RC oscillator: frequency jitter vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Analog voltage regulator: line - load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Digital voltage regulator: line - load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Voltage channel linearity at different VCC voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Power supply AC rejection vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Power supply DC rejection vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Error over dynamic range gain dependence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Primary current channel linearity at different VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. Gain response of ΣΔ A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. First-order ΣΔ A/D converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. ZCR signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. LIN and BFR signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17. Band-gap temperature variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Timings of tamper module - primary channel selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 19. Timings of tamper module - secondary channel selected. . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 20. Different oscillator circuits with (a) quartz, (b) internal oscillator, (c) external source. . . . . 25
Figure 21. STPM10 data record map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22. Timing for providing remote reset request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23. Data record reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24. Timing for data record reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 25. Timing for writing configuration and mode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 26. Active energy computation diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 27. STPM10 reference schematic with one current transformer and one shunt. . . . . . . . . . . . 47
Figure 28. TSSOP20 footprint recommended data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Schematic diagram STPM10 Doc ID 17728 Rev 4
1 Schematic diagram
Figure 1. Block diagram
STPM10 Pin configuration
Doc ID 17728 Rev 4 7/53 Pin configuration
Figure 2. Pin connections (top view)
Table 2. Pin description A: analog, D: digital, P: power
Maximum ratings STPM10
8/53 Doc ID 17728 Rev 4
3 Maximum ratings
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these condition is not implied.
Table 3. Absolute maximum ratings
Table 4. Thermal data This value is based on a single-layer PCB, JEDEC standard test board.
STPM10 Electrical characteristics
Doc ID 17728 Rev 4 9/53
4 Electrical characteristics
VCC = 5 V, TA = 25 °C,100 nF to 1 µF between VDDA and VSS, 100 nF to 1 µF between VDDD
and VSS, 100 nF to 1 µF between VCC and VSS unless otherwise specified.
Table 5. Electrical characteristics
Electrical characteristics STPM10
10/53 Doc ID 17728 Rev 4
Table 5. Electrical characteristics (continued)
STPM10 Electrical characteristics
Doc ID 17728 Rev 4 11/53
Table 5. Electrical characteristics (continued)
Terminology STPM10
12/53 Doc ID 17728 Rev 4
5 Terminology
5.1 Measurement error
The error associated with the energy measurement made by the STPM10 is defined as:
Percentage error = [STPM10 (reading) - true energy] / true energy
5.2 ADC offset error
This is the error due to the DC component associated with the analog inputs of the A/D
converters. Due to the internal automatic DC offset cancellation, the STPM10 measurement
is not affected by DC components in the voltage and current channel. The DC offset
cancellation is implemented in the DSP.
5.3 Gain error
The gain error is gain due to the signal channel gain amplifiers. This is the difference
between the measured ADC code and the ideal output code. The difference is expressed as
percentage of the ideal code.
5.4 Power supply DC and AC rejection
This parameter quantifies the STPM10 measurement error as a percentage of the reading
when the power supplies are varied. For the PSRRAC measurement, a reading at two
nominal supply voltages (3.3 and 5 V) is taken. A second reading is obtained with the same
input signal levels when an AC (200 mVRMS/100 Hz) signal is introduced on the supplies.
Any error introduced by this AC signal is expressed as a percentage of the reading. For the
PSRRDC measurement, a reading at two nominal supply voltages (3.3 and 5 V) is taken. A
second reading is obtained with the same input signal levels when the supplies are varied ±
10%. Any error introduced is again expressed as a percentage of the reading.
5.5 Conventions
The lowest analog and digital power supply voltage is called VSS, which represents system
ground (GND). All voltage specifications for digital input/output pins are referred to GND.
Positive currents flow into a pin. Sinking current refers to the current flowing into the pin, and
thus it is positive. Sourcing current means that the current is flowing out of the pin, so it is
negative.
Timing specifications of signals treated by the digital control part are relative to CLKOUT.
This signal is provided by the 4.194 MHz nominal-frequency crystal oscillator or from the
internal RC oscillator. An external source of 4.194 MHz or 8.192 MHz can also be used.
Timing specifications of signals from the SPI interface are relative to the SCL, and there is
no direct relationship between the clock (SCL) of the SPI interface and the clock of the DSP
block. A positive logic convention is used in all equations.
STPM10 Typical performance characteristics
6 Typical performance characteristics
Figure 3. Supply current vs. supply voltage,
TA = 25 °C (f = 4.194MHz, 8.192MHz)
Figure 4. RC oscillator frequency vs. VCC,
R = 12 kΩ , TA = 25 °C
Figure 5. RC oscillator: frequency jitter vs.
temperature
Figure 6. Analog voltage regulator: line - load
regulation
Typical performance characteristics STPM10
Figure 7. Digital voltage regulator: line - load
regulation
Figure 8. Voltage channel linearity at
different VCC voltages
Figure 9. Power supply AC rejection vs. VCC Figure 10. Power supply DC rejection vs. VCC
Figure 11. Error over dynamic range gain
dependence
Figure 12. Primary current channel linearity at
different VCC
STPM10 Typical performance characteristics
Figure 13. Gain response of ΔΣ A/D converters
Theory of operation STPM10
16/53 Doc ID 17728 Rev 4 Theory of operation
7.1 General operation description
The STPM10 is capable of performing measurements of active, reactive and apparent
energy, RMS and instantaneous voltage and current values, and line frequency information.
Most of the functions are fully programmable using internal configuration bits accessible
through the SPI interface. The STPM10 works as a peripheral in microcontroller-based
metering systems. The ZCR and WDG pins are used to provide zero-crossing and watch-
dog information, and the SPI pins are used to communicate with the microcontroller.
The STPM10 includes volatile internal registers that hold the useful information for the
metering system. T wo kinds of active energy are available: wide-band active energy (AW)
which includes all harmonic content (also called type 0) and fundamental active energy
(AF), limited to the 1st harmonic (also called type 1). This latter energy value is obtained by
filtering type 0 active energy. Both the two active energies are stored in up-down counting
accumulator registers with a 20-bit length. Reactive and apparent energies are also
available with a 20-bit accumulation.
The STPM10 also provides the RMS values for voltage and current. Due to the modest
dynamic variation of the voltage, the RMS value is stored with a resolution of 11 bits, while
the RMS current value has a resolution of 16 bits. The instantaneous (momentary) sampled
value of voltage and current are also available with a resolution of 11 and 16 bits,
respectively. The line frequency value is stored with a resolution of 14 bits.
Due to the proprietary energy computation algorithm, the STPM10 calibration is quick and
simple, allowing calibration at only one point over the entire current range.
The configuration and calibration parameters must be downloaded in the internal non-
volatile memory of STPM10 at power-up.
7.2 Analog inputs
Input amplifiers
The STPM10 has one fully differential voltage input channel and two fully differential current
input channels.
The voltage channel consists of a differential amplifier with a gain of 4. The maximum
differential input voltage for the voltage channel is ± 0.3 V.
The two current channels are multiplexed (see Section 7.9 for details) to provide a single
input to a preamplifier with a gain of 4. The output of this preamplifier is connected to the
input of a programmable gain amplifier (PGA) with possible gain selections of 2 and 8. The
total gain of the current channels are then 8 and 32. The gain selections are made by writing
to the gain register, and they can be different for the two current channels. If the tamper
function is not used, the secondary current can be disabled.
The maximum differential input voltage is dependent on the selected gain, in accordance
with Table6.
STPM10 Theory of operation
Doc ID 17728 Rev 4 17/53
The gain register is included in the device configuration register with the address name
PST. The table below shows the gain configuration according to the register values:
Note: If the device is used in configuration PST = 1, TMP = 1 (primary channel with CT, secondary
channel with Shunt), the shunt Ks must always be equal to one fourth of the current
transformer Ks.
Both the voltage and current channels implement an active offset correction architecture
which provides the benefit of avoiding any offset compensation.The analog voltage and
current signals are processed by the Σ Δ analog-to-digital converters, which feed the hard-
wired DSP . The DSP implements an automatic digital offset cancellation that makes it
possible to avoid any manual offset calibration on the analog inputs.
Table 6. Gain of voltage and current channels
Table 7. Configuration of current sensors
Theory of operation STPM10
18/53 Doc ID 17728 Rev 4
7.3 ΣΔ A/D converters
Analog-to-digital conversion in the STPM10 is carried out using two first-order Σ Δ
converters. The device performs A/D conversions of analog signals on two independent
channels in parallel. The current channel is multiplexed as a primary or secondary current
channel in order to perform the tamper function, if enabled. The converted Σ Δ signals are
supplied to the internal hard-wired DSP unit, which filters and integrates these signals in
order to boost the resolution and to yield all the necessary signals for the computations.
A Σ Δ modulator converts the input signal into a continuous serial stream of 1’s and 0’s at a
rate determined by the sampling clock. In the STPM10, the sampling clock is equal to
fCLK/4.
The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is
subtracted from the input signal. If the loop gain is high enough, the average value of the
DAC output (and therefore the bit stream) can approach that of the input signal level. When
a large number of samples are averaged, a very precise value for the analog signal is
obtained. This averaging is carried out in the DSP section, which implements decimation,
integration and DC offset cancellation of the supplied Σ Δ signals. The gain of the
decimation filters is 1.004 for the voltage channel and 0.502 for the current channel. The
resulting signal has a resolution of 11 bits per voltage channel and 16 bits per current
channel.
Figure 14. First-order ΣΔ A/D converter
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7.4 Zero-crossing detection
The STPM10 has a zero-crossing detector circuit on the voltage channel which can be used
by application for synchronization of some utility equipment in the event of zero-crossing of
the line voltage. This circuit produces the internal signal ZCR which has a rising edge every
time the line voltage crosses zero, and a negative edge every time the voltage reaches its
positive or negative peak. The ZCR signal is then at twice the line voltage frequency. The
ZCR signal is available on the ZCR pin.
7.5 Period and line voltage measurement
The period module measures the period of the base frequency of the voltage channel and
checks if the voltage signal frequency is within the fCLK/217 to fCLK/215 band. To do this, the
LIN signal is produced, which is low when the line voltage is rising, and high when the line
voltage is falling. This means that the LIN signal is the sign of dv/dt. With further elaboration,
the ZCR signal is also produced. On the trailing edge of LIN (line frequency) the period
counter starts counting up pulses of the fCLK/4 reference signal. The LIN signal is available
on the status bit register (see Table 10).
If the counted number of pulses between two trailing edges of LIN is higher than 215 , or if
the counting is never stopped (no LIN trailing edge) this means that the base frequency is
lower than fCLK/217 Hz and a BFR (base frequency range) error flag is set.
Figure 15. ZCR signal
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If the number of pulses counted between two trailing edges of LIN is lower than 213 , the
base frequency exceeds the limit (this means it is higher than fCLK/215 ). In this case, the
error must be repeated three consecutive times in order to set the BFR error flag.
For example, with a 4.194304 MHz oscillator frequency and MDIV bit clear (or 8.192 MHz
with MDIV set), fCLK/4 is 1.048576 MHz. If the line frequency is 30 Hz, the counted fCLK/4
pulses between two LIN trailing edges are 34952, more than 215 (32768 pulses).
The BFR low frequency limit is then:
fCLK/217 = 4194304/131072 = 32 Hz
With the same clock frequency, if the line frequency is 130 Hz, the fCLK/4 pulses between
two LIN trailing edges are 8066, less than 213 (8192). The BFR high frequency limit is then:
fCLK/215 = 4194304/32768 = 128 Hz.
The BFR flag is also set if the register value of the RMS voltage drops below 64. BFR is
cleared when the register value goes above 128. The BFR, then, also gives information
about the presence of the line voltage within the meter.
When the BFR error is set, the computation of power is zero unless the FRS bit is set.
In fact, the effect of the BFR bit can be overridden by setting FRS configuration bit.
Figure 16. LIN and BFR signals
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It means that if FRS is set and BFR is also set, all the energy computation is carried on as
BFR was cleared. In this case then p=u*i, where u could be zero or not (if BFR was set
because voltage RMS register value is below 64).
When the line frequency re-enters the nominal band, the BFR flag is automatically reset.
This BFR error flag is also assembled as part of the 8-bit status register (see Table 10).
7.6 Power supply
The main STPM10 supply pin is the VCC pin. From the VCC pin two linear regulators
provide the necessary voltage for the analog part VDDA (3 V) and for the digital part VDDD
(1.8 V).
The VSS pin represents the reference point for all the internal signals. A 100 nF low ESR
capacitor should be connected between VCC and VSS, VDDA and VSS, VDDD and VSS.
All these capacitors must be located very close to the device.
The STPM10 contains a power on reset (POR) detection circuit. If the VCC supply is less
than 2.5 V, then the STPM10 goes into an inactive state, all the functions are blocked and a
reset condition is asserted. This is useful to ensure correct device operation at power-up
and during power-down. The power supply monitor has built-in hysteresis and filtering,
which give a high degree of immunity from false triggering due to noisy supplies.
A band-gap voltage reference (VBG) of 1.23 V ±1% is used as the reference voltage level
source for the two linear regulators and for the A/D converters. Also, this module produces
several bias currents and voltages for all other analog modules. The band-gap voltage can
be compensated regardless of the temperature variations with the BGTC bits.
7.7 Load monitoring
The STPM10 includes a no-load condition detection circuit with adjustable threshold. This
circuit monitors the voltage and the current channels and, when the measured voltage is
below the set threshold, the internal signal BIL becomes high. Information about this signal
is also available in the status bit BIL.
Figure 17. Band-gap temperature variation
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The no-load condition occurs when the product of the VRMS and IRMS register values is
below a given value. This value can be set with the LTCH configuration bits. Four different
no-load threshold values can be chosen according to the two configuration bits L TCH (see
Table8).
When a no-load condition occurs (BIL=1) the integration of power is suspended and the
tamper module is disabled. The BIL signal can be accessed only through the SPI interface.
7.8 Error detection
In addition to the no-load condition and the line frequency band, the integration of power can
also be suspended due to an error detected on the source signals.
There are two kinds of error-detection circuits involved. The first checks all the Σ Δ signals
from the analog part if any is stacked at 1 or 0 within the 1/128 of fCLK period of observation.
In case of a detected error, the corresponding Σ Δ signal is replaced with an idle Σ Δ signal,
which represents a constant value of 0. All error and other resolved flags are treated as bits
of a device status and can be read out by means of the SPI interface.
Another error condition occurs if LED pin output signals are different from the internal
signals that drive them. This can occur if some of these pins are forced to GND or to some
other imposed voltage value. In this case, the internal status bit PIN is activated, providing
the information that some hardware problem has been detected.
7.9 Tamper detection module
The STPM10 is able to measure the current in both live and neutral wire with a time domain
multiplexing approach on a unique sigma delta modulator. This mechanism is adopted to
implement anti-tamper function. If this function is selected (see Table 7), the live and neutral
wire currents are monitored; when the difference between the two measurements exceeds a
rated threshold the STPM10 enters the "tamper state", while in "normal state" the two
measurements are below the threshold.
In particular, both channels are not observed all the time, rather a time multiplex mechanism
is used. During the observation time of each channel, its active energy is calculated. A
tamper condition occurs when the absolute value of the difference between the two active
energy values is greater than a certain percentage of the averaged energy during the
activated tamper module (see Equation 1).
This percentage value can be selected between two different values (12.5 % and 6.25 %)
according to the value of the configuration bit CRIT.
The tamper condition is detected when the following formula is satisfied:
Table 8. No-load detection thresholds
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Equation 1
EnergyCH1 - EnergyCH2 > KCRIT (EnergyCH1 + EnergyCH2)/2;
where KCRIT can be 12.5 % or 6.25 %.
The detection threshold is much higher than the accuracy difference of the current channels,
which should be less than 0.2 %, but, some headroom should be left for possible transition
effect, due to accidental synchronism of actual load current change with the rhythm of taking
the energy samples.
The tamper circuit works if the energies associated with the two current channels are both
positive or negative, if the two energies have different sign, the tamper is on all the time
however, the channel with the associated higher power is selected for the final computation
of energy.
When internal signals are not good enough to perform the calculations, i.e. line period is out
or range or ΔΣ signals from analog section are stacked at high or low logic level, or no load
condition is activated, the tamper module is disabled and its state is preset to normal.
7.9.1 Detailed operational description
The meter is initially set to normal state, i.e. tamper not detected.In this condition the
primary channel is selected for final integration of energy. In such state the values of both
load currents should not differ more than the accuracy difference of the channels does.
Sixty-four periods of line voltage is used as a tamper checking period.
After 24 periods of line voltage two internal signals MUX and INH are changed in order to
enable secondary current channel and to freeze the last power and RMS values of primary
current channel. The following 16 periods of line frequency are used for tamper detection
integration. During this gap, the final energy calculation does not use the signal from
selected channel but the frozen values.
Four line periods after the INH switch, the integration of power from secondary current
channel is started and lasts four periods. Additional four line periods later MUX signal is
switched back to primary current channel and the integration for tamper detection is started.
The timings of MUX and INH signals are shown in Figure 18 below.
Figure 18. Timings of tamper module - primary channel selected
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When the secondary channel is selected to be integrated by the final energy integrator, the
MUX and INH signals change according to Figure 19 below.
This means that energy of four periods from secondary channel followed by energy of four
periods from primary channel is sampled within the tamper module. From these two
samples, called B and A respectively, the criteria of tamper is calculated and the channel
with higher current is selected, resulting in a new tamper state. If four consecutive new
results of criteria happen, i.e. after elapsed 5.12 s at 50 Hz, the meter will enter into tamper
state. Thus, the channel with the higher current will be selected for the energy calculation. If
samples of power A and B would have different signs, the Tamper would be on all the time
but, the channel with bigger power would be still selected for the final integration of energy.
If a tamper status has been detected, the multiplex ratio will be 56:8 if the primary channel
energy is greater than the secondary one, otherwise it will be 8:56.
The detected tamper condition is stored in the BIT status bit. If BIT = 0 tamper is not
detected, if BIT = 1 a tamper condition has been detected. In standalone mode the BIT flag
is also available in the SDATD pin.
7.10 Phase compensation
The STPM10 does not introduce any phase shift between the voltage and current channel.
However, the voltage and current signals come from transducers, which could have inherent
phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current
transformer (CT). These phase errors can vary from part to part, and they must be corrected
in order to perform accurate power calculations. The errors associated with phase mismatch
are particularly noticeable at low power factors. The STPM10 provides a means of digitally
calibrating these small phase errors by introducing delays on the voltage or current signal.
The amount of phase compensation can be set using the 4 bits of the phase calibration
register (CPH).
The default value of this register is at a value of 0, which gives 0° phase compensation.
When the 4 bits give a CPH of 15 (1111) the compensation introduced is +0.576°. This
compensates the phase shift usually introduced by the current sensor, while the voltage
sensor, normally a resistor divider, does not introduce any delay. The resolution step of the
phase compensation is 0.038°.
Figure 19. Timings of tamper module - secondary channel selected
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7.11 Clock generator
All the internal timing of the STPM10 is based on the CLKOUT signal. This signal can be
generated in three different ways: RC: this oscillator mode can be selected using the RC configuration bit. If RC = 1, the
STPM10 runs using the RC oscillator. A resistor connected between CLKIN and
ground sets the RC current. For 4 MHz operation, the recommended settling resistor is
12 kΩ . The oscillator frequency can be compensated using the CRC configuration bit.
2. Quartz: If RC = 0, the oscillator works with an external crystal. The recommended
circuit is depicted in Figure 20 (b).
3. External clock: by keeping RC=0, it is also possible to feed the CLKOUT pin with an
external oscillator signal.
The clock generator is powered from an analog supply and is responsible for two tasks. The
first is to retard the turn-on of some function blocks after POR in order to help smooth the
start of the external power supply circuitry by keeping off all major loads. The second task of
the clock generator is to provide all necessary clocks for the analog and digital parts. During
this task, the MDIV configuration bit is used to inform the device about the nominal
frequency value of CLKOUT . Two nominal frequency ranges are expected to be from 4.000
MHz to 4.194 MHz (MDIV = 0) or from 8.000 MHz to 8.192 MHz (MDIV = 1).
7.11.1 RC startup procedure
To use the device with RC oscillator the configuration bit RC (see Table 11) must be set.
Since the default configuration is for a crystal oscillator, when a RC oscillator is used instead
and the device is supplied for the very first time it is not internally clocked and consequently
the DSP is inactive. In this condition it is not possible to set RC or any other configuration bit.
The following SPI procedure can be run in order to set the RC bit and provide the clock to
the device: Set the mode signal BANK; Perform a software reset; Read the registers: BANK mode signal should be checked and the records should
show something (not 000000F0); Clear the mode signal BANK; DO NOT perform a reading, and write configuration bit RC;
Figure 20. Different oscillator circuits with (a) quartz, (b) internal oscillator, (c) external source
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In this way the RC oscillator is started. If the registers are read again, it can be seen that RC
bit is set and BANK is cleared. Once the RC startup procedure is complete, the device is
clocked and active. For details on mode signals refer to Section 7.18, for SPI operations
refer to Section 7.19.
7.12 Resetting the STPM10
The STPM10 has no reset pin. The device is automatically reset by the POR circuit when
the VCC crosses the 2.5 V value, but it can also be reset through the SPI interface by
providing a dedicated command (see Section 7.19 for remote reset command details).
In case of reset caused by the POR circuit, all clocks and both DC buffers in the analog part
are kept off for about 30 ms, as well as all blocks of the digital part, except for the SPI
interface, which is held in a reset state for about 125 ms after a reset condition.
When a reset is performed through SPI, no delayed turn-on is generated.
Resetting the STPM10 causes all the functional modules of the STPM10 to be cleared,
including the volatile memory.
The reset through SPI (remote reset request) normally takes place during production
testing.
7.13 Using the STPM10 in microcontroller-based meters
The STPM10 can be used in microcontroller-based energy meters.
The SPI pins (SCS, SCL, SDA, SYN) are used for communication purposes, allowing the
microcontroller to write and read the internal STPM10 registers.
The zero-crossing signal is available at the ZCR pin (see Section 7.4 for details about the
ZCR signal).
The WDG pin provides the watchdog signal (DOG). The DOG signal generates a 16 ms
long positive pulse every 1.6 seconds. Generation of these pulses can be suspended if data
are read in intervals shorter than 1.6 s. The DOG signal is actually a watchdog reset signal
which can be used to control operation of an on-board microcontroller. It is set to high
whenever the VDDA voltage is below 2.5 V , but after VDDA goes above 2.5 V this signal
starts running.
It is expected that an application microcontroller should access the data in the metering
device on a regular basis at least 1/s (recommended is 32/s). Every latching of results in the
metering device requested from the microcontroller also resets the watchdog. If latching
requests are not 1.6 seconds from one another, an active high pulse on WDG is produced,
because the device assumes that the microcontroller is not operating properly. An
application can use this signal either to control the reset pin of its microcontroller, or it can
be tied to an interrupt pin. The latter option is recommended for a battery-backup application
which can enter a sleep mode due to power-down conditions, and should not be reset by a
metering device as it would exit from sleep mode.
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7.14 Energy to frequency conversion
