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STPIC6C595
POWER LOGIC 8-BIT SHIFT REGISTER
1/17July 2004 LOW R DS(on) : 4Ω TYP 30mJ AVAILANCHE ENERGY EIGHT 100mA DMOS OUTPUTS 250mA CURRENT LIMIT CAPABILITY 33V OUTPUT CLAMP VOLTAGE DEVICE ARE CASCADABLE LOW POWER CONSUMPTION
DESCRIPTIONThis STPIC6C595 is a monolithic,
medium-voltage, low current power 8-bit shift
register designed for use in systems that require
relatively moderate load power such as LEDs. The
device contains a built-in voltage clamp on the
outputs for inductive transient protection. Power
driver applications include relays, solenoids, and
other low-current or medium-voltage loads.
The device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage register clock (SRCK) and the register
clock (RCK), respectively. The device transfers
data out the serial output (SER OUT) port on the
rising edge of SRCK. The storage register
transfers data to the output buffer when shift
register clear (CLR) is high. When CLR is low, the
input shift register is cleared. When output enable
(G) is held high, all data in the output buffer is held
low and all drain output are off. When G is held
low, data from the storage register is transparent
to the output buffer. When data in the output
buffers is low, the DMOS transistor outputs are off.
When data is high, the DMOS transistor outputs
have sink-current capability. The SER OUT allows
for cascading of the data from the shift register to
additional devices.
Output are low-side, open-drain DMOS transistors
with output ratings of 33V and 100mA continuous
sink-current capability. Each output provides a
250 mA maximum current limit at TC = 25°C. The
current limit decreases as the junction
temperature increases for additional device
protection. The device also provides up to 1.5KV
of ESD protection when tested using the
human-body model and 200V machine model.
The STPIC6C595 is characterized for operation
over the operating case temperature range of
-40°C to 125°C.
ORDERING CODES
STPIC6C595POWER LOGIC 8-BIT SHIFT REGISTER
Rev. 2
STPIC6C5952/17
Figure 1: Logic Symbol And Pin Configuration
Figure 2: Input And Output Equivalent Circuits
STPIC6C5953/17
Table 1: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
Table 2: Thermal Data
Table 3: Recommended Operating Conditions
STPIC6C5954/17
Table 4: DC Characteristics (VCC =5V, TC = 25°C, unless otherwise specified.)
Table 5: Switching Characteristics (VCC =5V, TC = 25°C, unless otherwise specified.)
Note 1: All Voltage value are with respect to GND
Note 2: Each power DMOS source is internally connected to GND
Note 3: Pulse duration ≤ 100μs and duty cycle ≤ 2%
Note 4: Drain Supply Voltage = 15V, starting junction temperature (TJS) = 25°C. L = 1.5H and IAS = 200mA (See Fig. 11 and 12)
Note 5: Technique should limit TJ - TC to 10°C maximum
Note 6: These parameters are measured with voltage sensing contacts separate from the current-carrying contacts.
Note 7: Nominal Current is defined for a consistent comparison between devices from different sources. It is the current that produces a volt-
age drop of 0.5V at TC = 85°C.
STPIC6C5955/17
Figure 3: Logic Diagram
STPIC6C5956/17
Figure 4: Typical Operation Mode Test Circuits
Figure 5: Typical Operation Mode Waveforms NOTE:
A) The word generator has the following characteristics: tr ≤ 10ns, tf ≤ 10ns, tW = 300ns, pulse repetition rate (PRR) = 5KHz, ZO = 50Ω
B) CL includes probe and jig capacitance.
STPIC6C5957/17
Figure 6: Typical Operation Mode Test Circuits
Figure 7: Switching Time Waveform
Figure 8: Input Setup And Hold Waveform NOTE:
A) The word generator has the following characteristics: tr ≤ 10ns, tf ≤ 10ns, tW = 300ns, pulse repetition rate (PRR) = 5KHz, ZO = 50Ω
B) CL includes probe and jig capacitance.
STPIC6C5958/17
Figure 9: Reverse Recovery Current Test Circuits
Figure 10: Source Drain Diode Waveform NOTE:
A) The VGG amplitude and RG are adjusted for di/dt = 10A/μs. A VGG double-pulse train is used to set IF = 0.1A. where t1 = 10μs, t2 = 7μs
and t3 = 3μs
B) The Drain terminal under test is connected to the TPK test point. All other terminals are connected together and connected to the TPA test
point.
C) IRM = maximum recovery current.
STPIC6C5959/17
Figure 11: Single Pulse Avalanche Energy Test Circuits
Figure 12: Single Pulse Avalanche Energy Waveform NOTE:
A) The word generator has the following characteristics: tr ≤ 10ns, tf ≤ 10ns, ZO = 50Ω
B) Input pulse duration, tW is increased until peak current IAS = 200 mA. Energy test level is defined as EAS = (IAS x V(BR)DSX x tAV)/2 = 30mJ.
