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Partno	Mfg	Dc	Qty	Available	Descript
STP3NA100FP	ST	N/a	3	avai	OLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-IN

STP3NA100FP ,OLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-INSTP3NA100STP3NA100FIN - CHANNEL ENHANCEMENT MODEFAST POWER MOS TRANSISTORTYPE V R IDSS DS(on) DSTP ..
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T0-220 , Fit Rate / Equivalent Device Hours
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STP3NA100FP
OLD PRODUCT: NOT SUITABLE FOR NEW DESIGN-IN
STP3NA100
STP3NA100FI
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR TYPICAL RDS(on) = 4.3 Ω ± 30V GATE TO SOURCE VOLTAGE RATING 100% AVALANCHE TESTED REPETITIVE AVALANCHE DATA AT 100oC LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED REDUCED THRESHOLD VOLTAGE SPREAD
APPLICATIONS HIGH CURRENT, HIGH SPEED SWITCHING SWITCH MODE POWER SUPPLIES (SMPS) DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
February 1998
ABSOLUTE MAXIMUM RATINGS
(•) Pulse width limited by safe operating area
1/9
THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (Tcase = 25 o C unless otherwise specified)
OFF
ON (∗)
DYNAMIC
STP3NA100/FI
2/9
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
(∗) Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Safe Operating Area for TO-220 Safe Operating Area for TO-220FP
STP3NA100/FI
Thermal Impedance for TO-220
Output Characteristics
Transconductance
Thermal Impedance forTO-220FP
Transfer Characteristics
Static Drain-source On Resistance
STP3NA100/FI
4/9
Gate Charge vs Gate-source Voltage
Normalized Gate Threshold Voltage vs
Temperature
Source-drain Diode Forward Characteristics
Capacitance Variations
Normalized On Resistance vs Temperature
STP3NA100/FI
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 2: Unclamped Inductive Waveform
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
STP3NA100/FI
6/9

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