STMPE811QTR ,S-Touch® advanced resistive touchscreen controller with 8-bit GPIO expanderfeatures . . . . . . . 124.2 Data input . 134.3 Read operation . . . . . 144.4 Wri ..
STMPE812ABJR ,Touchscreen controller S-Touch with PWM and dedicated RESET pinfeatures 92.2 Data input . . 92.3 Read operation . . . . . 122.4 Write operations ..
STMPS2151MTR ,Enhanced single channel power switches
STMPS2171STR ,Enhanced single channel power switches
STMPS2171STR ,Enhanced single channel power switches
STMPS2262MTR ,Enhanced dual channel power switches
SY89327LMITR , 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR
SY89327LMITR , 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR
SY89328LMITR , 3V LVTTL-TO-DIFFERENTIAL, LVPECL AND DIFFERENTIAL, LVPECL-TO-LVTTL TRANSLATOR
SY89328LMITR , 3V LVTTL-TO-DIFFERENTIAL, LVPECL AND DIFFERENTIAL, LVPECL-TO-LVTTL TRANSLATOR
SY89420VJC , 5V/3.3V DUAL PHASE LOCKED LOOP
SY89420VJC , 5V/3.3V DUAL PHASE LOCKED LOOP
STMPE811QTR
S-Touch® advanced resistive touchscreen controller with 8-bit GPIO expander
September 2011 Doc ID 14489 Rev 6 1/65
STMPE811S-T ouch® advanced resistive touchscreen controller
with 8-bit GPIO expander
Features 8 GPIOs 1.8- 3.3 V operating voltage Integrated 4-wire touchscreen controller Interrupt output pin Wakeup feature on each I/O SPI and I2 C interface Up to 2 devices sharing the same bus in 2 C mode (1 address line) 8-input 12-bit ADC 128-depth buffer touchscreen controller Touchscreen movement detection algorithm 25 kV air-gap ESD protection (system level)4 kV HBM ESD protection (device level)
Applications Portable media players Game consoles Mobile and smartphones GPS
DescriptionThe STMPE811 is a GPIO (general purpose
input/output) port expander able to interface a
main digital ASIC via the two-line bidirectional bus 2 C). A separate GPIO expander is often used in
mobile multimedia platforms to solve the
problems of the limited amount of GPIOs typically
available on the digital engine.
The STMPE811 offers great flexibility, as each I/O
can be configured as input, output or specific
functions. The device has been designed with
very low quiescent current and includes a wakeup
feature for each I/O, to optimize the power
consumption of the device.
A 4-wire touchscreen controller is built into the
STMPE811. The touchscreen controller is
enhanced with a movement tracking algorithm (to
avoid excessive data), a 128 x 32 bit buffer and
programmable active window feature.
Table 1. Device summary
Contents STMPE8112/65 Doc ID 14489 Rev 6
Contents STMPE811 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C and SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.1 Interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.1 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155.1 SPI protocol definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.1 Register reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2 Register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.3 Termination of data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 SPI timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1 SPI timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
STMPE811 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Touchscreen controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3310.1 Driver and switch control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.2 T ouch detect delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
STMPE811 ContentsDoc ID 14489 Rev 6 3/65
Touchscreen controller programming sequence . . . . . . . . . . . . . . . . . 46 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.0.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.0.2 Power-up reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5414.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
List of tables STMPE811
4/65 Doc ID 14489 Rev 6
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Pin configuration for IN2, IN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Pin configuration for X+, Y+, X-, Y-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Interface selection pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. I2C address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. SPI timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Register summary map table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. System and identification registers map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. ADC controller register summary table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. ADC conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. Touchscreen controller register summary table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 16. Touchscreen controller DATA register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. Touchscreen parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 18. GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 19. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 20. Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 21. DC electrical characteristics (-40 °C to 85 °C) all GPIOs comply to JEDEC standard JESD-
8-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 22. AC electrical characteristics (-40 °C to 85 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 23. ADC specification (-40 °C to 85 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 24. Switch drivers specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 25. Package mechanical data for QFN16 (3x3 x 1 mm) - 0.50 pitch . . . . . . . . . . . . . . . . . . . 60
Table 26. Exposed pad variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 27. Footprint dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 28. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
STMPE811 List of figures
Doc ID 14489 Rev 6 5/65
List of figures
Figure 1. STMPE811 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. STMPE811 pin configuration (top through view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. STMPE811 interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. STMPE811 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. I2 C timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Read and write modes (random and sequential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Interrupt system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Touchscreen controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. Window tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. Sampling time calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. Package outline for QFN16 (3x3 x 1 mm) - 0.50 pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 14. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 15. Carrier tape for QFN16 (3x3x1 mm) - 0.50 pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 16. Reel information for QFN16 (3 x3x1 mm) - 0.50 pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
STMPE811 functional overview STMPE811
6/65 Doc ID 14489 Rev 6 STMPE811 functional overview
The STMP811 consists of the following blocks: I2 C and SPI interface Analog-to-digital converver (ADC) Touchscreen controller (TSC) Driver and switch control unit Temperature sensor GPIO controller
Figure 1. STMPE811 functional block diagram
STMPE811 Pin configuration and functions
Doc ID 14489 Rev 6 7/65 Pin configuration and functions
Figure 2. STMPE811 pin configuration (top through view)
Table 2. Pin assignments
Pin configuration and functions STMPE811
8/65 Doc ID 14489 Rev 6
2.1 Pin functions
The STMPE811 is designed to provide maximum features and flexibility in a very small pin-
count package. Most of the pins are multi-functional. Table 3 and Table 4 show how to select
the pin’s function.
Table 3. Pin configuration for IN2, IN3
Table 4. Pin configuration for X+, Y+, X-, Y-
STMPE811 I2C and SPI interface
Doc ID 14489 Rev 6 9/65
3 I2 C and SPI interface
3.1 Interface selection
The STMPE811 interfaces with the host CPU via a I2 C or SPI interface. The pin IN_1 allows
the selection of interface protocol at reset state.
Figure 3. STMPE811 interface
Table 5. Interface selection pins
I2C interface STMPE811
10/65 Doc ID 14489 Rev 6
4 I2 C interface
The addressing scheme of STMPE811 is designed to allow up to 2 devices to be connected
to the same I2 C bus.
Figure 4. STMPE811 I2 C interface
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and be followed by the slave device address. Accompanying the slave device
address, is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation. If a
match occurs on the slave device address, the corresponding device gives an acknowledge
on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not
responding to the transaction.
Figure 5. I2 C timing diagram
Table 6. I2 C address
STMPE811 I2C interface
Doc ID 14489 Rev 6 11/65
Table 7. I2 C timing
I2C interface STMPE811
12/65 Doc ID 14489 Rev 6
4.1 I2 C features
The features that are supported by the I2 C interface are listed below: I2 C slave device Operates at 1.8V Compliant to Philips I2 C specification version 2.1 Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
Stop condition
A Stop condition is identified by a rising edge of SDA TA while SCLK is stable at high state. A
Stop condition terminates communication between the slave device and the bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I2 C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it does not acknowledge the receipt of the data.
STMPE811 I2C interface
Doc ID 14489 Rev 6 13/65
4.2 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
Figure 6. Read and write modes (random and sequential)
Table 8. Operating modes
I2C interface STMPE811
14/65 Doc ID 14489 Rev 6
4.3 Read operation
A write is first performed to load the register address into the Address Counter but without
sending a Stop condition. Then, the bus master sends a reStart condition and repeats the
Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the
content of the addressed byte. If no additional data is to be read, the bus master must not
acknowledge the byte and terminates the transfer with a Stop condition.
If the bus master acknowledges the data byte, then it can continue to perform the data
reading. To terminate the stream of data bytes, the bus master must not acknowledge the
last output byte, and be followed by a Stop condition. If the address of the register written
into the Address Counter falls within the range of addresses that has the auto-increment
function, the data being read are coming from consecutive addresses, which the internal
Address Counter automatically increments after each byte output. After the last memory
address, the Address Counter 'rolls-over' and the device continues to output data from the
memory address of 0x00. Similarly, for the register address that falls within a non-increment
range of addresses, the output data byte comes from the same address (which is the
address referred by the Address Counter).
Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an
acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a
low state, then the slave device terminates and switches back to its idle mode, waiting for
the next command.
4.4 Write operations
A write is first performed to load the register address into the Address Counter without
sending a Stop condition. After the bus master receives an acknowledgement from the slave
device, it may start to send a data byte to the register (referred by the Address Counter).
The slave device again acknowledges and the bus master terminates the transfer with a
Stop condition.
If the bus master needs to write more data, it can continue the write operation without
issuing the Stop condition. Whether the Address Counter autoincrements or not after each
data byte write depends on the address of the register written into the Address Counter.
After the bus master writes the last data byte and the slave device acknowledges the receipt
of the last data, the bus master may terminate the write operation by sending a Stop
condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the
next data byte write.
STMPE811 SPI interface
Doc ID 14489 Rev 6 15/65
5 SPI interface
The SPI (serial peripheral interface) in STMPE811 uses a 4-wire communication connection
(DATA IN, DATA OUT , CLK, CS). In the diagram, “Data in” is referred to as MOSI (master
out slave in) and “DATA out” is referred to as MISO (master in slave out).
5.1 SPI protocol definition
The SPI follows a byte-sized transfer protocol. All transfers begin with an assertion of CS_n
signal (falling edge). The protocol for reading and writing is different and the selection
between a read and a write cycle is dependent on the first captured bit on the slave device.
A '1' denotes a read operation and a '0' denotes a write operation. The SPI protocol defined
in this section is shown in Figure3.
The following are the main features supported by this SPI implementation. Support of 1 MHz maximum clock frequency. Support for autoincrement of address for both read and write. Full duplex support for read operation. Daisy chain configuration support for write operation. Robust implementation that can filter glitches of up to 50 ns on the CS_n and SCL pins. Support for all 4 modes of SPI as defined by the CPHA, CPOL bits on SPICON.
5.1.1 Register reading
The following steps need to be followed for the register read through the SPI.
1. Assert CS_n by driving a '0' on this pin.
2. Drive a '1' on the first SCL launch clock on MOSI to select a read operation.
3. The next 7 bits on MOSI denote the 7-bit register address (MSB first).
4. The next address byte can now be transmitted on the MOSI. If the autoincrement bit is
set, the following address transmitted on the MOSI is ignored. Internally, the address is
incremented. If the autoincrement bit is not set, then the following byte denotes the
address of the register to be read next.
5. Read data is transmitted by the slave device on the MISO (MSB first), starting from the
launch clock following the last address bit on the MOSI.
6. Full duplex read operation is achieved by transmitting the next address on MOSI while
the data from the previous address is available on MISO.
7. To end the read operation, a dummy address of all 0's is sent on MOSI.
SPI interface STMPE811
16/65 Doc ID 14489 Rev 6
5.1.2 Register write
The following steps need to be followed for register write through SPI.
1. Assert CS_n by driving a '0' on this pin.
2. Drive a '0' on the first SCL launch clock on MOSI to select a write operation.
3. The next 7 bits on MOSI denote the 7-bit register address (MSB first).
4. The next byte on the MOSI denotes data to be written.
5. The following transmissions on MOSI are considered byte-sized data. The register
address to which the following data is written depends on whether the autoincrement
bit in the SPICON register is set. If this bit has been set previously, the register address
is incremented for data writes.
5.1.3 Termination of data transfer
A transfer can be terminated before the last launch edge by deasserting the CS_n signal. If
the last launch clock is detected, it is assumed that the data transfer is successful.
STMPE811 SPI interface
Doc ID 14489 Rev 6 17/65
5.2 SPI timing modes
The SPI timing modes are defined by CPHA and CPOL,CPHA and CPOL are read from the
"SDAT" and "A0" pins during power-up reset. The following four modes are defined
according to this setting.
The clocking diagrams of these modes are shown in ON reset. The device always operates
in mode 0. Once the bits are set in the SPICON register, the mode change takes effect on
the next transaction defined by the CS_n pin being deasserted and asserted.
5.2.1 SPI timing definition
Table 9. SPI timing modes
Table 10. SPI timing specification
SPI interface STMPE811
18/65 Doc ID 14489 Rev 6
Figure 7. SPI timing specification
Table 10. SPI timing specification (continued)
STMPE811 STMPE811 registers
Doc ID 14489 Rev 6 19/65
6 STMPE811 registers
This section lists and describes the registers of the STMPE811 device, starting with a
register map and then provides detailed descriptions of register types.
Table 11. Register summary map table
STMPE811 registers STMPE811
20/65 Doc ID 14489 Rev 6
Table 11. Register summary map table (continued)
STMPE811 STMPE811 registers
Doc ID 14489 Rev 6 21/65
Table 11. Register summary map table (continued)
System and identification registers STMPE811
22/65 Doc ID 14489 Rev 6 System and identification registers
Table 12. System and identification registers map
STMPE811 System and identification registers
Doc ID 14489 Rev 6 23/65
CHIP_ID Device identification
Address: 0x00
Type: R
Reset: 0x0811
Description: 16-bit device identification
ID_VER Revision number
Address: 0x02
Type: R
Reset: 0x03 (0x01 for engineering samples)
Description: 16-bit revision number
SYS_CTRL1 Reset control
Address: 0x03
Type: R/W
Reset: 0x00
Description: The reset control register enables to reset the device
SYS_CTRL2 Clock control
Address: 0x04
Type: R/W
Reset: 0x0F
Description: This register enables to switch off the clock supply
7654 3 2 1 0
[7:2] RESERVED
[1] SOFT_RESET: Reset the STMPE811 using the serial communication interface
[0] HIBERNATE: Force the device into hibernation mode.
Forcing the device into hibernation mode by writing ‘1’ to this bit would disable the hot-key
feature. If the hot-key feature is required, use the default auto-hibernation mode.
7654 3 2 1 0
[7:4] RESERVED
[3] TS_OFF: Switch off the clock supply to the temperature sensor
1: Switches off the clock supply to the temperature sensor
[2] GPIO_OFF: Switch off the clock supply to the GPIO
1: Switches off the clock supply to the GPIO
System and identification registers STMPE811
24/65 Doc ID 14489 Rev 6
SPI_CFG SPI interface configuration
Address: 0x08
Type: R/W
Reset: 0x01
Description: SPI interface configuration register
[1] TSC_OFF: Switch off the clock supplyto the touchscreen controller
1: Switches off the clock supply to the touchscreen controller
[0] ADC_OFF: Switch off the clock supply to the ADC
1: Switches off the clock supply to the ADC
7654 3 2 1 0
[7:3] RESERVED
[2] AUTO_INCR:
This bit defines whether the SPI transaction follows an addressing scheme that internally
autoincrements or not
[1] SPI_CLK_MOD1:
This bit reflects the value of the SCAD/A0 pin during power-up reset
[0] SPI_CLK_MOD0:
This bit reflects the value of the SCAD/A0 pin during power-up reset
STMPE811 Interrupt system
Doc ID 14489 Rev 6 25/65
8 Interrupt system
The STMPE811 uses a 2-tier interrupt structure. The ADC interrupts and GPIO interrupts
are ganged as a single bit in the “interrupt status register”. The interrupts from the
touchscreen controller and temperature sensor can be seen directly in the interrupt status
register.
Figure 8. Interrupt system diagram
Interrupt system STMPE811
26/65 Doc ID 14489 Rev 6
INT_CTRL Interrupt control register
Address: 0x09
Type: R/W
Reset: 0x00
Description: The interrupt control register is used to enable the interruption from a system-related
interrupt source to the host.
INT_EN Interrupt enable register
Address: 0x0A
Type: R/W
Reset: 0x00
Description: The interrupt enable register is used to enable the interruption from a system related
interrupt source to the host.
INT_STA Interrupt status register
7654 3 2 1 0
[7:3] RESERVED
[2] INT_POLARITY: This bit sets the INT pin polarity
1: Active high/rising edge
0: Active low/falling edge
[1] INT_TYPE: This bit sets the type of interrupt signal required by the host
1: Edge interrupt
0: Level interrupt
[0] GLOBAL_INT: This is master enable for the interrupt system
1: Global interrupt
0: Stops all interrupts
7654 3 2 1 0
[7] GPIO: Any enabled GPIO interrupts
[6] ADC: Any enabled ADC interrupts
[5] TEMP_SENS: Temperature threshold triggering
[4] FIFO_EMPTY: FIFO is empty
[3] FIFO_FULL: FIFO is full
[2] FIFO_OFLOW: FIFO is overflowed
[1] FIFO_TH: FIFO is equal or above threshold value.
[0] TOUCH_DET: Touch is detected
7654 3 2 1 0
STMPE811 Interrupt system
Doc ID 14489 Rev 6 27/65
Address: 0x0B
Type: R
Reset: 0x10
Description: The interrupt status register monitors the status of the interruption from a particular
interrupt source to the host. Regardless of whether the INT_EN bits are enabled, the
INT_STA bits are still updated. Writing '1' to this register clears the corresponding
bits. Writing '0' has no effect.
GPIO_INT_EN GPIO interrupt enable register
Address: 0x0C
Type: R/W
Reset: 0x00
Description: The GPIO interrupt register enables the GPIO interruption of a particular GPIO
source to the host.
GPIO_INT_STA GPIO interrupt status register
Address: 0x0D
Type: R
Reset: 0x00
Description: The GPIO interrupt status register monitors the status of the interruption from a
particular GPIO pin interrupt source to the host. Regardless of whether or not the
GPIO_INT_ST A bits are enabled, the corresponding GPIO_STA bits are still updated.
[7] GPIO: Any enabled GPIO interrupts
[6] ADC: Any enabled ADC interrupts
[5] TEMP_SENS: Temperature threshold triggering
[4] FIFO_EMPTY: FIFO is empty
[3] FIFO_FULL: FIFO is full
[2] FIFO_OFLOW: FIFO is overflowed
[1] FIFO_TH: FIFO is equal or above threshold value.
This bit is set when FIFO level equals to threshold value. It will only be asserted again if FIFO
level drops to < threshold value, and increased back to threshold value.
[0] TOUCH_DET: Touch is detected
7654 3 2 1 0
[7:0] IEG[x]: Interrupt enable GPIO mask (where x= 7 to 0)
1: Writing ‘1’ to the IE[x] bit enables the interruption to the host
7654 3 2 1 0
Interrupt system STMPE811
28/65 Doc ID 14489 Rev 6
The ISG[7:0] bits are the interrupt status bits corresponding to the GPIO[7:0] pins.
Writing '1' to this register clears the corresponding bits. Writing '0' has no effect.
ADC_INT_EN ADC interrupt enable register
Address: 0x0E
Type: R/W
Reset: 0x00
Description: The ADC enable register enables the interruption of a particular ADC source to the
host.
ADC_INT_STA ADC interrupt status register
Address: 0x0F
Type: R
Reset: 0x00
Description: The ADC interrupt status register monitors the status of the interruption from a
particular ADC source to the host. Regardless of whether or not the ADC_INT_EN
bits are enabled, the corresponding ADC_ST A bits are still updated. The ISA[7:0] bits
are the interrupt status bits corresponding to the ADC[7:0] pins. Writing '1' to this
register clears the corresponding bits. Writing '0' has no effect.
[7:0] ISG[x]: GPIO interrupt status (where x = 7 to 0)
Read:
Interrupt status of the GPIO[x]. Reading the register clears any bits that have been set to '1'
Write:
Writing to this register has no effect
7654 3 2 1 0
[7:0] IEAC[x]: Interrupt enable ADC mask (where x= 7 to 0)
1: Writing ‘1’ to the IE[x] bit enables the interruption to the host
7654 3 2 1 0
[7:0] ISA[x]: ADC interrupt status (where x = 7 to 0)
Read:
Interrupt status of the ADC[x]. Reading the register clears any bits that have been set to '1'
Write:
Writing to this register has no effect.
Note: Refer to Table 13 for the associated ADC intput pins to each ADC channels.
STMPE811 Analog-to-digital converter
Doc ID 14489 Rev 6 29/65
9 Analog-to-digital converter
An 8-input,12-bit analog-to-digital converter (ADC) is integrated in the STMPE811. The ADC
can be used as a generic analog-to-digital converter, or as a touchscreen controller capable
of controlling a 4-wire resistive touchscreen.
Table 13. ADC controller register summary table
Analog-to-digital converter STMPE811
30/65 Doc ID 14489 Rev 6
ADC_CTRL1 ADC control 1
Address: 0x20
Type: R/W
Reset: 0x1C
Description: ADC control register.
ADC_CTRL2 ADC control 2
Address: 0x21
Type: R/W
Reset: 0x01
Description: ADC control. 6 5 4 3 210
[7] RESERVED
[6:4] SAMPLE_TIMEn: ADC conversion time in number of clock
000: 36
001: 44
010: 56
011: 64
100: 80
101: 96
110: 124
111: Not valid
[3] MOD_12B: Selects 10 or 12-bit ADC operation
1: 12 bit ADC
0: 10 bit ADC
[2] RESERVED
[1] REF_SEL: Selects between internal or external reference for the ADC
1: External reference
0: Internal reference
[0] RESERVED
7654 3 2 1 0
[7] RESERVED
[6] RESERVED
[5] RESERVED
[4] RESERVED
[3] RESERVED
[2]
RESERVED
STMPE811 Analog-to-digital converter
Doc ID 14489 Rev 6 31/65
ADC_CAPT ADC channel data capture
Address: 0x22
Type: R/W
Reset: 0xFF
Description: To initiate ADC data acquisition.
ADC_DATA_CHn ADC channel data registers
Address: Add address
Type: R/W
Reset: 0x0000
Description: ADC data register 0-7 (DATA_CHn=0-7)
The ADC in STMPE811 operates on an internal RC clock with a typical frequency of
6.5 MHz. The total conversion time in ADC mode depends on the "SampleTime" setting,
and the clock division field 'Freq'.
The following table shows the conversion time based on 6.5 MHz, 3.25 MHz and 1.625 MHz
clock.
[1:0] ADC_FREQ: Selects the clock speed of ADC
00: 1.625 MHz typ.
01: 3.25 MHz typ.
10: 6.5 MHz typ.
11: 6.5 MHz typ.
7654 3 2 1 0
[7:0] CH[7:0]: ADC channel data capture
Write '1' to initiate data acquisition for the corresponding channel. Writing '0' has no effect.
Reads '1' if conversion is completed. Reads '0' if conversion is in progress. 10 987 6543 2 1 0
[11:0] DATA[11:0]: ADC channel data
If TSC is enabled, CH3-0 is used for TSC and all readings to these channels give 0x0000
Table 14. ADC conversion time
Analog-to-digital converter STMPE811
32/65 Doc ID 14489 Rev 6
Table 14. ADC conversion time
STMPE811 Touchscreen controller
Doc ID 14489 Rev 6 33/65
10 Touchscreen controller
The STMPE811 is integrated with a hard-wired touchscreen controller for 4-wire resistive
type touchscreen. The touchscreen controller is able to operate completely autonomously,
and interrupt the connected CPU only when a pre-defined event occurs.
Figure 9. Touchscreen controller block diagram
10.1 Driver and switch control unit
The driver and switch control unit allows coordination of the ADC and the MUX/switch. With
the coordination of this unit, a stream of data is produced at a selected frequency.
The touchscreen drivers can be configured with 2 current ratings: 20 mA or 50 mA. In the
case where multiple touch-down on the screen is causing a short, the current from the driver
is limited to these values. T olerance of these current setting is +/- 25%.
Movement tracking
The "Tracking Index" in the TSC_CTRL register specifies a value, which determines the
distance between the current touch position and the previous touch position. If the distance
is shorter than the tracking index, it is discarded.
The tracking is calculated by summation of the horizontal and vertical movement. Movement
is only reported if:
(Current X - Previously Reported X) + (Current Y - Previously Reported Y) > Tracking Index
If pressure reporting is enabled (X/Y/Z), an increase in pressure override the movement
tracking and report the new data set, even if X/Y is within the previous tracking index. This is
to ensure that a slow touch is not discarded.
If pressure data is not used, select X/Y mode in touchscreen data acquisition. (Opmode field
in TSCControl register).
