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STMPE801MTR-STMPE801QTR
8-bit port expander Xpander Logic
July 2007 Rev 4 1/26
STMPE8018-bit port expander
Xpander logic
Features 8 GPIO Operating voltage 1.65V - 3.6V I/O voltage 1.65V-3.6V Interrupt output pin Reset input pin Wake up feature on each I/O Up to 2 devices sharing the same bus
(1 address line) <1µA suspend current
Application Portable media player, Game console Mobile phone, Smart phone
DescriptionThe STMPE801 is a GPIO (General Purpose
Input / Output) port expander able to interface a
main digital ASIC via the two-line bidirectional bus 2 C); separate GPIO Expander IC is often used in
Mobile-Multimedia platforms to solve the
problems of the limited amounts of GPIOs usually
available on the Digital Engine.
The STMPE801 offers great flexibility as each
I/Os is configurable as input, output. This device
has been designed very low quiescent current,
and includes wake up feature for each I/O, to
optimize the power consumption of the IC.
Table 1. Device summary
Contents STMPE801
2/26
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 I2C address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5 Acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.6 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.7 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.8 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.9 Acknowledgement in read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.10 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.11 General call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Turning I2C block OFF and ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STMPE801 Contents
3/26 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 System and identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 System control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Interrupt, power supply & reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1 Interrupt enable GPIO mask register (IEGPIOR) . . . . . . . . . . . . . . . . . . . 16
8.2 Interrupt status GPIO register (ISGPIOR) . . . . . . . . . . . . . . . . . . . . . . . . 17
8.3 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.4 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block diagram STMPE801
4/26
1 Block diagram
Figure 1. Block diagram
STMPE801 Pin settings
5/26
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection
Pin settings STMPE801
6/26
2.2 Pin assignment
Table 2. Pin assignment
STMPE801 Maximum rating
7/26
3 Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
3.1 Absolute maximum rating
3.2 Thermal data
Table 3. Absolute maximum rating
Table 4. Thermal data
Electrical specification STMPE801
8/26
4 Electrical specification
4.1 DC electrical characteristics
Table 5. DC electrical characteristics
STMPE801 I2C module
9/26
5 I2 C module
STMPE801 is interface to the main processor using an I2C bus.
5.1 I2 C address
Addressing scheme of STMPE801 is designed to allow up to 2 devices to be connected to
the same I2 C bus.
Figure 3. Addressing scheme
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition anf followed by the slave device address. Accompanying the slave device address,
there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for write operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from
the bus by not responding to the transaction.
Table 6. Addresses
I2C module STMPE801
10/26
Figure 4. I2 C timing
5.2 I2 C features
The features that are supported by the I2 C interface are as below: I2 C slave device Operates at 1.8V Compliant to Philips I2 C specification version 2.1 Supports standard (uo to 100Kbps) and fast (up to 400Kbps) modes
Table 7. I2 C address
STMPE801 I2C module
11/26
5.3 Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and will not respond to any transaction unless one is
encountered.
5.4 Stop condition
A Stop condition is identified by a rising edge of SDAT A while SCLK is stable at high state.
A Stop condition terminates communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I2 C transaction. A Stop condition at the end of a write command stops the write
operation to registers.
5.5 Acknowledge bit
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it would to not acknowledge the receipt of the data.
5.6 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
I2C module STMPE801
12/26
5.7 Operation modes
Figure 5. Read and write modes (random and sequential)
Table 8. Operation modes
STMPE801 I2C module
13/26
5.8 Read operation
A write is first performed to load the register address into the Address Counter but without
sending a Stop condition. Then, the bus master sends a reStart condition and repeats the
Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the
content of the addressed byte. If no more data is to be read, the bus master must not
acknowledge the byte and terminates the transfer with a Stop condition.
If the bus master acknowledges the data byte, then it can continue to perform the data
reading. To terminate the stream of data byte, the bus master must not acknowledge the
last output byte and follow by a Stop condition. If the address of the register written into the
Address Counter falls within the range of addresses that has the auto-increment function,
the data being read will be coming from consecutive addresses, with the internal Address
Counter automatically increments after each byte output. After the last memory address,
the Address Counter 'rolls-over' and the device continue to output data from the memory
address of 0x00. Similarly, for the address of register that falls within non-increment range
of addresses, the output data byte comes from the same address (which is the address
pointed by the Address Counter).
5.9 Acknowledgement in read operation
For the above read command, the slave device waits, after each byte read, for an
acknowledgement during the ninth bit time. If the bus master does not drive the SDA to low
state, then the slave device terminates and switches back to its idle mode, waiting for the
next command.
5.10 Write operations
A write is first performed to load the register address into the Address Counter without
sending a Stop condition. After the bus master receives an acknowledgement from the
slave device, it may start to send a data byte to the register (pointed by the Address
Counter). The slave device again acknowledges and the bus master terminates the transfer
with a Stop condition.
If the bus master would like to continue to write more data, it can just continue write
operation without issuing the Stop condition. Whether the Address Counter auto-
increments or not after each data byte write, depends on the address of the register written
into the Address Counter. After the bus master writes the last data byte and the slave
device acknowledges the receipt of the last data, the bus master may terminates the write
operation by sending a Stop condition. When the Address Counter reaches the last
memory address, it 'rolls-over' on the next data byte write.
