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STMPE1601TBR
16-bit enhanced port expander with keypad and PWM controller Xpander Logic
February 2010 Doc ID 14318 Rev 6 1/62
STMPE160116-bit enhanced port expander with keypad and PWM controller
Xpander Logic™
Features 16 GPIOs
(8 operate at core supply VCC , 8 operate at IO
supply VIO) Operating voltage 1.8 −3.3V Hardware keypad controller (8*8 matrix with 4
optional dedicated keys max) Keypad controller capable of detecting key-
press in hibernation mode 4 basic PWM controllers for LED brightness
control Interrupt output (open drain) pin Optional 32 kHz clock input 8-channel programmable level translator Advanced power management system Ultra-low standby-mode current Package TFBGA25 (3x3 mm)
DescriptionThe STMPE1601 is a GPIO (general purpose
input/output) port expander able to interface a
main digital ASIC via the two-line bidirectional bus 2 C). A separate GPIO expander IC is often used
in mobile multimedia platforms to solve the
problems of the limited number of GPIOs typically
available on the digital engine.
The STMPE1601 offers great flexibility, as each
I/O can be configured as input, output or specific
functions. The device is able to scan a keyboard,
also provides PWM outputs for brightness control
in backlight, and GPIO function. This device has
been designed to include very low quiescent
current, and a wake-up feature for each I/O, to
optimize the power consumption of the IC.
Potential applications of the STMPE1601 include
portable media players, game consoles, mobile
and smart phones.
Table 1. Device summary
Contents STMPE16012/62 Doc ID 14318 Rev 6
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Pin assignment and TFBGA ball location . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Ball mapping to TFBGA (top through view) . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 GPIO pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94.1 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Input/Output DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126.1 Minimizing current drain on I2C address lines . . . . . . . . . . . . . . . . . . . . . 13
6.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.6 Slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.7 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.8 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.9 General call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177.1 States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 Autosleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.3 Keypress detect in the hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STMPE1601 ContentsDoc ID 14318 Rev 6 3/62
Clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.2 Power mode programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249.1 Interrupt system register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1.1 Interrupt latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3110.1 GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2 GPIO alternate function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.3 Hotkey feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.3.1 Programming sequence for Hotkey . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.3.2 Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.4 Level translator feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Basic PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3611.1 Interrupt on basic PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11.2 T rigger feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4312.1 Keypad configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.2 Keypad controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Keypad combination key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5615.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Block diagram STMPE1601
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1 Block diagram
Figure 1. STMPE1601 block diagram
STMPE1601 Pin settings
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2 Pin settings
2.1 Pin connection
Figure 2. Pin connection (top-through view)
2.2 Pin assignment and TFBGA ball location
Table 2. Pin assignment
Pin settings STMPE1601
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2.3 Ball mapping to TFBGA (top through view)
Table 2. Pin assignment (continued)
Table 3. Pin mapping
STMPE1601 Pin settings
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2.4 GPIO pin functions
Table 4. GPIO pin functions
Maximum ratings STMPE1601
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3 Maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
3.1 Absolute maximum ratings
3.2 Thermal data
Table 5. Absolute maximum ratings
Table 6. Thermal data
STMPE1601 Electrical specification
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4 Electrical specification
4.1 DC electrical characteristics
Table 7. DC electrical characteristics If only the basic GPIO function is required, the STMPE1601 can be designed to work mostly in hibernate
mode. Active mode is used only when there are changes in the I/O status.
Electrical specification STMPE1601
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4.2 Input/Output DC electrical characteristics
The 1.8 V I/O complies to the EIA/JEDEC standard JESD8-7.
Table 8. I/O DC electrical characteristic
Table 9. DC input specification (1.55V< VCC <1.95V)
Table 10. DC output specification (1.55 V < VCC < 1.95V) Applicable to GPIO_0 to GPIO_7. Applicable to GPIO_8 to GPIO_15.
STMPE1601 Register map
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5 Register map
All the registers have the size of 8-bit. For each of the module, their registers are residing
within the given address range.
Table 11. Register map summary table
I2C interface STMPE1601
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6 I2 C interface
The features supported by the I2 C interface are listed below: I2 C slave device Operates at VCC (1.8 - 3.3V) Compliant to Philips I2 C specification version 2.1 Supports standard (up to 100kbps) and fast (up to 400 kbps) modes 7-bit and 10-bit device addressing modes General Call Start/Restart/Stop Address up to 8 STMPE1601 devices via the I2 C interface
The address is selected by the state of 3 pins. The state of the pins is read upon reset and
then the pins can be configured for normal operation. The pins have a pull-up or pull-down
to set the address. The I2 C interface module allows the connected host system to access
the registers in the STMPE1601.
Table 12. I2 C addresses
STMPE1601 I2C interface
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6.1 Minimizing current drain on I2 C address lines
The GPIOs 13-15 are used as I2 C address input during POR. Pull-up/down resistor of
500 kΩ - 1.5 MΩ is recommended for these address lines. In the case that these pins are
driven to an opposite logic level during device operation, there would be a current drain of
VIO/R. This amounts to a significant current drain for portable devices. o minimize the current drain on I2 C lines, two methods are recommended: If maximum keypad size is not required, these shared lines should not be used for
keypad operation.
2. If the maximum keypad size is required, choose I2 C address 0x40, as this requires all 3
address lines to be pulled to ground, minimizing the current drain in the keypad
operation. In this mode of operation, the recommended pull up/down resistors on the 2 C lines are listed in Table 13.
A reset circuit with longer RC is used to ensure enough time for the address lines to
settle to the final values.
3. In system-controlled idle state, all the keypad pins are to be configured as hotkey with
interrupt function enabled. If any key is pressed, the system initiates the keypad
controller for scanning operation.
Table 13. Recommended pull up/down resistors on the I2 C lines Recommended values are chosen to minimize leakage current.
I2C interface STMPE1601
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6.2 Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.
A Start condition must precede any data/command transfer. The device continuously
monitors for a Start condition and does not respond to any transaction unless one is
encountered.
6.3 Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.
A Stop condition terminates the communication between the slave device and bus master. A
read command that is followed by NoAck can be followed by a Stop condition to force the
slave device into idle mode. When the slave device is in idle mode, it is ready to receive the
next I2 C transaction. A Stop condition at the end of a write command stops the write
operation to the registers.
6.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter
releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls
the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave
the SDATA in high state if it would to not acknowledge the receipt of the data.
6.5 Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA
signal must be stable during the rising edge of SCLK and the SDATA signal must change
only when SCLK is driven low.
6.6 Slave device address
The slave device address is a 7 or 10-bit address, where the least significant 3-bit are
programmable. These 3-bit values will be loaded in once upon reset and after that these 3
pins no longer be needed with the exception during General Call. Up to 8 STMPE1601
devices can be connected on a single I2 C bus.
6.7 Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start
condition and followed by the slave device address. Accompanying the slave device
address, there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for Write
operation.
If a match occurs on the slave device address, the corresponding device gives an
acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself
from the bus by not responding to the transaction.
STMPE1601 I2C interface
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6.8 Operating modes
Figure 3. I2 C transaction
Table 14. Operating modes
I2C interface STMPE1601
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6.9 General call address
A general call address is a transaction with the slave address of 0x00 and R/W = 0. When a
general call address is made, the STMPE1601 responds to this transaction with an
acknowledgement and behaves as a slave-receiver mode. The meaning of a general call
address is defined in the second byte sent by the master-transmitter.
Note: All other second byte values will be ignored.
Table 15. General call address
STMPE1601 System controller
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7 System controller
The system controller is the heart of the STMPE1601. It contains the registers for power
control and chip identification.
The system registers are:
CHIP_ID Chip identification register
VERSION_ID Version identification register
Table 16. System registers 654 3210 654 3210
System controller STMPE1601
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SYS_CTRL System control register
Address: 0x02
Type: R/W
Reset: 0x0F
Description: System control register. 6 54 32 10
[7] SOFT_RESET
Writing a ‘1’ to this bit will do a soft reset of the device. Once the reset is done, this bit will be
cleared to ‘0’ by the HW.
[6] CLOCK_SOURCE
Set to ‘1’ if external 32 kHz clock were to be used. ‘0’ by default.
[5] DIS_32 kHz:
Set this bit to disable the 32 kHz OSC, thus putting the device in hibernate mode.
[4] SLEEP:
Writing a ‘1’ to this bit will put the device in sleep mode. On going to sleep mode, this mode is
reset internally. When in sleep mode, the internal RC oscillator will output a slower sleep clock
which will be used in the device.
[3] EN_GPIO:
Writing a ‘0’ to this bit will gate off the clock to the GPIO module, thus stopping its operation
[2] RESERVED
[1] EN_KPC:
Writing a ‘0’ to this bit will gate off the clock to the keypad controller module, thus stopping its
operation
[0] EN_SPWM
Writing a ‘0’ to this bit will gate off the clock to the simple PWM controller module, thus
stopping its operation
STMPE1601 System controller
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SYS_CTRL_2 System control register 2
Address: 0x03
Type: R/W
Reset: 0x00
Description: System control register. 6 5 432 1 0
[7] RESERVED
[6] RESERVED
[5] RESERVED
[4] VIO_OFF:
Writing a ‘1’ to this bit is mandatory before shutting off the VIO supply while maintaining the
VCC supply.
This ensure that the level shifters for GPIOs 15-8 are properly powered down so as not to
induce high current and also not to affect the integrity of any external signals that are on the
bus where these GPIOs are connected.
[3] AUTOSLEEP_EN:
“1” to enable auto-sleep feature. “0” to disable auto-sleep.
[2:0] SLEEP:
000 for 4 ms delay
001 for 16 ms delay
010 for 32 ms delay
011: for 64 ms delay
100: for 128 ms delay
101: for 256 ms delay
110: for 512 ms delay
111: for 1024 ms delay
System controller STMPE1601
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7.1 States of operation
Figure 4. Modes of operation
The device has three main modes of operation: Operational mode: This is the mode, whereby normal operation of the device takes
place. In this mode, the RC clock is available and the main FSM unit routes this clock
and the 32 kHz clock to all the device blocks that are enabled. In this mode, individual
blocks that need not to be working can be turned off by the master by programming the
bits 3 to 0 of the SYS_CTRL register. Sleep mode: In this low-power mode, the RC oscillator is powered down. All the blocks
which need clocks derived from the 32 kHz clock will continue getting a 32 kHz clock. In
this mode also, iindividual blocks can be turned off by the master by programming the
bits 3 to 0 of the SYS_CTRL register. However, the master needs to program the
SYS_CTRL register before coming into this mode, as in the sleep mode, the I2C
interface is not active except to detect traffic for wakeup. Any activity on the I2 C port
(intended I2 C transaction for the device) or Wakeup pin or Hotkey activity will cause the
device to leave this mode and go into the Operational mode. When leaving this mode,
the I2 C will need to hold the SCLK till the RC clock is ready. Hibernate mode: This mode is entered when the system writes a ‘1’ to bit 5 of the
SYS_CTRL register. In this mode, the device is completely inactive as there is
absolutely no clock. Only a Reset or a wakeup on I2 C will bring back the system to
operational mode. A keypress detect will bring the system to Sleep mode, in which the
debounce of the key will take place.
Note: The 32 kHz clock mentioned in this section can be (1) an externally fed 32 kHz clock, or (2)
an internally generated (from RC OSC) clock. In case the internal clock is used, the clock
has a range of 25 to 45 kHz.
STMPE1601 System controller
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7.2 Autosleep
The host system may configure the STMPE1601 to go into sleep mode automatically
whenever there is a period of inactivity following a complete I2 C transaction with the
STMPE1601. This inactivity means there is no intended I2 C transaction for the device. For
example, if there is an I2 C transaction sent by the host to other slave devices, the
STMPE1601 device will still be counting down for the auto-sleep. The STMPE1601 device
resets the autosleep time-out counter only when it receives an I2 C transaction meant for the
device itself. This autosleep feature is controlled by the SYS_CTRL_2 (system control
register 2).
All those events that trigger an interrupt (KPC, hot-key) would result in a transition from
Sleep state to Operational state automatically. The wakeup can also be performed through
the I2 C transaction intended for the device.
7.3 Keypress detect in the hibernate mode
When in Hibernate mode, a keypress detect causes the system to go into sleep mode. The
sleep clock (32 kHz) is then used to debounce the key to detect a valid key. If the keypress is
detected to be valid, the system stays in sleep mode. If the key is detected to be invalid, the
system goes back into Hibernate mode.
Clocking system STMPE1601
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8 Clocking system
Figure 5. Clocking system
The decision on clocks is based on the bits written into the SYS_CTRL registers. Bits 0 to 3
of the SYS_CTRL register allow to control the gating of clocks to the keypad controller,
PWM and GPIO in the operational mode.
8.1 Clock source
By default, when the STMPE1601 powers up, it derives a 32 kHz clock from the internal RC
oscillator for its operation. If an external clock source is available, it must be configured to
accept an external clock through the SYS_CTRL register.
There are 4 sources of reset: Reset_N pin Low voltage detect (LVD) reset Soft reset bit of the SYS_CTRL register I2 C reset from the I2 C block.
STMPE1601 Clocking system
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8.2 Power mode programming sequence o put the device in sleep mode, the following needs to be done by the host: Write a '1' to bit 4 of the SYS_CTRL register. o wake up the device, the host is required to: Assert a wakeup routine on the I2 C bus by sending the Start bit, followed by the
device address and the Write bit. Subsequently, proceed with sending the Base
Register address and continue with a normal I2 C transaction. The device wakes
up upon receiving the correct device address and in Write direction. In other
words, the procedure of waking up the device is performed by just sending an I2C
transaction to the device. This procedure can be extended to wake up the device
that is in hibernate mode. o do a soft reset to the device, the host needs to do the following: Write a '1' to bit 7 of the SYS_CTRL register. This bit is automatically cleared upon
reset. o go into Hibernate mode, the following needs to be done by the host: Set the Disable_32K bit to '1' o come out of the Hibernate mode, the following needs to be done by the host: Assert a system reset or put a wakeup on the I2C
Interrupt system STMPE1601
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9 Interrupt system
The STMPE1601 uses a highly flexible interrupt system. It allows the host system to
configure the type of system events that should result in an interrupt, and pinpoints the
source of interrupt by status register. The INT pin can be configured as ACTIVE HIGH, or
ACTIVE LOW.
Once asserted, the INT pin would de-assert only if the corresponding bit in the interrupt
status register is cleared.
Figure 6. Interrupt system
9.1 Interrupt system register map
Table 17. Register map
STMPE1601 Interrupt system
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9.1.1 Interrupt latency
When the generation of interrupts by the GPIO as input is enabled, the latency (time taken
from actual transition at GPIO to time of INT pin assertion) is shown in the following table:
INT_CTRL Interrupt control register
Address: 0x10, 0x11
Type: R, R/W
Reset: 0x00
Description: The interrupt control register is used to configure the interrupt controller. It has a
global enable interrupt mask bit that controls the interruption to the host.
Table 18. Interrupt latency
14 13 12 11 10 987 654321 0
[15:3] RESERVED
[2] IC2: Output Interrupt polarity
‘0’ = Active low/falling edge
‘1’ = Active high/rising edge
[1] IC1: Output Interrupt Type
‘0’ = Level interrupt
‘1’ = Edge interrupt
[0] IC0: Global Interrupt Mask bit
When this bit is written a ‘1’, it will allow interruption to the host. If it is written with a ‘0’, then, it
disables all interruption to the host. Writing to this bit does not affect the INT_EN_MASK value.
Interrupt system STMPE1601
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INT_EN_MASK Interrupt enable mask register
Address: 0x12, 0x13
Type: R, R/W
Reset: 0x00
Description: The interrupt enable mask register is used to enable the interruption from a particular
interrupt source to the host.
14 13 12 11 10 9 8 7 6 543210
[15:9] RESERVED
[8] IE[x]:
Interrupt Enable Mask (where x = 8 to 0)
IE0: Wake-up interrupt mask
IE1: Keypad controller interrupt mask
IE2: Keypad controller FIFO overflow interrupt mask
IE3: Reserved
IE4: Basic PWM controller 0 interrupt mask
IE5: Basic PWM controller 1 interrupt mask
IE6: Basic PWM controller 2 interrupt mask
IE7: Basic PWM controller 3 interrupt mask
IE8: GPIO controller interrupt mask
Writing a ‘1’ to the IE[x] bit enables the interruption to the host.
STMPE1601 Interrupt system
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INT_STA Interrupt status register
Address: 0x14, 0x15
Type: R, R/W
Reset: 0x00
Description: The interrupt status register monitors the status of the interruption from a particular
interrupt source to the host. Regardless whether the INT_EN bits are enabled or not,
the INT_STA bits are still updated. 14 13 12 11 10 98 765 432 10
[15:9] RESERVED
[8:0] IS[x]:
Interrupt status (where x = 8 to 0)
Read:
IS0: Wake-up Interrupt Status
IS1: Keypad controller interrupt status
IS2: Keypad controller FIFO overflow interrupt status
IS3: Reserved
IS4: Basic PWM controller 0 interrupt status
IS5: Basic PWM controller 1 interrupt status
IS6: Basic PWM controller 2 Interrupt status
IS7: Basic PWM controller 3 interrupt status
IS8: GPIO Controller Interrupt Status
Write: a write to a IS[x] bit with a value of ‘1’ will clear the interrupt and a write with a value of ‘0’
has no effect on the IS[x] bit.
Interrupt system STMPE1601
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INT_EN_GPIO_MASK Interrupt enable GPIO mask register
Address: 0x16, 0x17
Type: R/W
Reset: 0x00
Description: The interrupt enable GPIO mask register is used to enable the interruption from a
particular GPIO interrupt source to the host. The IEG[15:0] bits are the interrupt
enable mask bits correspond to the GPIO[15:0] pins 14 13 12 11 10 98 765 432 10
[15:0] IEG[x]: interrupt enable GPIO mask (where x = 15 to 0)
Writing a ‘1’ to the IE[x] bit will enable the interruption to the host.
STMPE1601 Interrupt system
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INT_STA_GPIO Interrupt status GPIO register
Address: 0x18, 0x19
Type: R/W
Reset: 0x00
Description: The interrupt status GPIO register monitors the status of the interruption from a
particular GPIO pin interrupt source to the host. Regardless whether the
INT_EN_GPIO_MASK bits are enabled or not, the INT_STA_GPIO bits are still
updated. The INT_STA_G[15:0] bits are the interrupt status bits correspond to the
GPIO[15:0] pins.
14 13 12 11 10 9876543210
[15:0] ISG[x]
Interrupt status GPIO (where x = 15 to 0)
Read:
Interrupt status of the GPIO[x].
Write:
A write to a ISG[x] bit with a value of ‘1’ will clear the interrupt and a write with a value of ‘0’ has
no effect on the ISG[x] bit.
Interrupt system STMPE1601
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9.2 Programming sequence o configure and initialize the interrupt controller to allow interruption to host, observe the
following steps: Set the INT_EN_MASK and INT_EN_GPIO_MASK registers to the desired values to
enable the interrupt sources that are to be expected to receive from.
2. Configure the output interrupt type and polarity and enable the global interrupt mask by
writing to the INT_CTRL.
3. Wait for interrupt.
4. Upon receiving an interrupt, the INT pin is asserted.
5. The host comes to read the INT_ST A register through the I2 C interface. A ‘1’ in the
INT_STA bits indicates that the corresponding interrupt source is triggered.
6. If the IS8 bit in INT_STA register is set, the interrupt is coming from the GPIO controller.
Then, a subsequent read is performed on the INT_STA_GPIO register to obtain the
interrupt status of all 16 GPIOs to locate the GPIO that triggers the interrupt. This is a
feature so-called ‘Hot Key’.
7. After obtaining the interrupt source that triggers the interrupt, the host performs the
necessary processing and operations related to the interrupt source.
8. If the interrupt source is from the GPIO Controller, two write operations with value of ‘1’
are performed to the ISG[x] bit (INT_ST A_GPIO) and the IS[8] (INT_STA) to clear the
corresponding GPIO interrupt.
9. If the interrupt source is from other module, a write operation with value of ‘1’ is
performed to the IS[x] (INT_STA) to clear the corresponding interrupt.
10. Once the interrupt is being cleared, the INT pin will also be de-asserted if the interrupt
type is level interrupt. An edge interrupt will only assert a pulse width of 250ns.
11. When the interrupt is no longer required, the IC0 bit in INT_CTRL may be set to ‘0’ to
disable the global interrupt mask bit.
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10 GPIO controller
A total of 16 GPIOs are available in the STMPE1601 port expander device. Most of the
GPIOs are sharing physical pins with some alternate functions. The GPIO controller
contains the registers that allow the host system to configure each of the pins into either a
GPIO, or one of the alternate functions. Unused GPIOs should be configured as outputs to
minimize the power consumption.
Table 19. GPIO controller (Base address = 0 x 80)
