STM8S207R8T6C ,Mainstream Performance line 8-bit MCU with 64 Kbytes Flash, 24 MHz CPU, integrated EEPROMElectrical characteristics . . . . 5110.1 Parameter conditions 5110.1.1 Minimum and maxim ..
STM8S207RBT6 ,Mainstream Performance line 8-bit MCU with 128 Kbytes Flash, 24 MHz CPU, integrated EEPROMElectrical characteristics . . . . 5110.1 Parameter conditions 5110.1.1 Minimum and maxim ..
STM8S207RBT6C ,Mainstream Performance line 8-bit MCU with 128 Kbytes Flash, 24 MHz CPU, integrated EEPROMSTM8S207xxSTM8S208xxPerformance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash,integrated EEPROM, ..
STM8S207S6T3C ,Mainstream Performance line 8-bit MCU with 32 Kbytes Flash, 24 MHz CPU, integrated EEPROMSTM8S207xxSTM8S208xxPerformance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash,integrated EEPROM, ..
STM8S207S6T6C ,Mainstream Performance line 8-bit MCU with 32 Kbytes Flash, 24 MHz CPU, integrated EEPROMfeatures . . . . . . . 11Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 regis ..
STM8S207S8T3C ,Mainstream Performance line 8-bit MCU with 64 Kbytes Flash, 24 MHz CPU, integrated EEPROMBlock diagram . . . . . 124 Product overview . . 134.1 Central processing unit STM8 ..
SY88703VKG , 3.3V/5V 622Mbps PECL LOW-POWER LIMITING POST AMPLIFIER W/TTL LOS
SY88703VKG , 3.3V/5V 622Mbps PECL LOW-POWER LIMITING POST AMPLIFIER W/TTL LOS
SY88713VKG , 3.3V/5V 622 Mbps PECL LOW-POWER LIMITING POST AMPLIFIER W/PECL SIGNAL DETECT
SY88722VKG , 5V/3.3V 622Mbps LASER DIODE DRIVER WITH OUTPUT ENABLE
SY88722VKG , 5V/3.3V 622Mbps LASER DIODE DRIVER WITH OUTPUT ENABLE
SY88782LMG , 3.3V, 1.25 Gbps HIgh Current, Low Power Laser Driver for Datacom Telecom Applications
STM8S207C6T6-STM8S207C8T3-STM8S207C8T6-STM8S207CBT6-STM8S207K6T3C-STM8S207K6T3CTR-STM8S207K6T6C-STM8S207K8T6C-STM8S207M8T6B-STM8S207MBT6B-STM8S207R6T6-STM8S207R8T3-STM8S207R8T6-STM8S207R8T6C-STM8S207RBT6-STM8S207RBT6C-STM8S207S6T3C-STM8S207S6T6C-STM8S207S8T3C-STM8
Mainstream Performance line 8-bit MCU with 32 Kbytes Flash, 24 MHz CPU, integrated EEPROM
February 2012 Doc ID 14733 Rev 12 1/103
STM8S207xx
STM8S208xxPerformance line, 24 MHz STM8S 8-bit MCU, up to 128 KB Flash,
integrated EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN
Features Core
–Max fCPU: up to 24 MHz, 0 wait states @
fCPU ≤ 16 MHz Advanced STM8 core with Harvard
architecture and 3-stage pipeline Extended instruction set Max 20 MIPS @ 24 MHz Memories Program: up to 128 Kbytes Flash; data
retention 20 years at 55 °C after 10 kcycles Data: up to 2 Kbytes true data EEPROM;
endurance 300 kcycles RAM: up to 6 Kbytes Clock, reset and supply management 2.95 to 5.5 V operating voltage Low power crystal resonator oscillator External clock input Internal, user-trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitor Wait, active-halt, & halt low power modes Peripheral clocks switched off individually Permanently active, low consumption
power-on and power-down reset Interrupt management Nested interrupt controller with 32
interrupts Up to 37 external interrupts on 6 vectors Timers 2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM) Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-
time insertion and flexible synchronization 8-bit basic timer with 8-bit prescaler Auto wakeup timer Window watchdog, independent watchdog Communications interfaces High speed 1 Mbit/s active beCAN 2.0B UART with clock output for synchronous
operation - LIN master mode UART with LIN 2.1 compliant, master/slave
modes and automatic resynchronization SPI interface up to 10 Mbit/s2 C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os Up to 68 I/Os on an 80-pin package
including 18 high sink outputs Highly robust I/O design, immune against
current injection Development support Single wire interface module (SWIM) and
debug module (DM) 96-bit unique ID key for each device
Table 1. Device summary
Contents STM8S207xx, STM8S208xx
2/103 Doc ID 14733 Rev 12
Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14
4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18
4.12 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13 Analog-to-digital converter (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.2 UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14.4 I2 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.14.5 beCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM8S207xx, STM8S208xx Contents
Doc ID 14733 Rev 12 3/103
6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.4 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10.1.5 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.6 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.1.7 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
10.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
10.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 64
10.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 66
10.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.3.9 I2 C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.1.1 LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 96
Contents STM8S207xx, STM8S208xx
4/103 Doc ID 14733 Rev 12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
STM8S207xx, STM8S208xx List of tables
Doc ID 14733 Rev 12 5/103
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM8S20xxx performance line features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers. . . . . . . . . . . . . . . 16
Table 4. TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Legend/abbreviations for pinout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 11. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 13. Option byte description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 14. Unique ID registers (96 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 17. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 18. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 19. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 20. Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 57
Table 21. Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 58
Table 22. Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 23. Total current consumption in wait mode at VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24. Total current consumption in active halt mode at VDD = 5 V, TA -40 to 85° C . . . . . . . . . . 60
Table 25. Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 60
Table 26. Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 27. Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 28. Wakeup times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 29. Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 30. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 31. HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 32. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 33. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 34. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 35. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 36. Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 37. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 38. Output driving current (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 39. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 40. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 41. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 42. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 43. I2 C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 44. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 45. ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 46. ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 47. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 48. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
List of tables STM8S207xx, STM8S208xx
6/103 Doc ID 14733 Rev 12
Table 49. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 50. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 51. 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 52. 64-pin low profile quad flat package mechanical data (14 x 14) . . . . . . . . . . . . . . . . . . . . . 90
Table 53. 64-pin low profile quad flat package mechanical data (10 x 10) . . . . . . . . . . . . . . . . . . . . . 91
Table 54. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 55. 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 56. 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 57. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 58. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
STM8S207xx, STM8S208xx List of figures
Doc ID 14733 Rev 12 7/103
List of figures
Figure 1. STM8S20xxx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. LQFP 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 12. fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 13. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 14. Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 15. Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 16. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 17. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 18. Typical HSI frequency variation vs VDD at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 19. Typical LSI frequency variation vs VDD @ 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 20. Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 21. Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22. Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23. Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24. Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 25. Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 26. Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 27. Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 28. Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 29. Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 30. Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 31. Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 33. Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 34. Typical NRST pull-up resistance vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 35. Typical NRST pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 36. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 37. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 38. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 39. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 40. Typical application with I2 C bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 41. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 42. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 43. 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 44. 64-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 45. 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 46. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 47. 44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 48. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
List of figures STM8S207xx, STM8S208xx
8/103 Doc ID 14733 Rev 12
Figure 49. STM8S207xx/208xx performance line ordering information scheme(1) . . . . . . . . . . . . . . . 99
STM8S207xx, STM8S208xx Introduction
Doc ID 14733 Rev 12 9/103
1 Introduction
This datasheet contains the description of the STM8S20xxx performance line features,
pinout, electrical characteristics, mechanical data and ordering information. For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016). For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051). For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470). For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
Description STM8S207xx, STM8S208xx
10/103 Doc ID 14733 Rev 12
2 Description
The STM8S20xxx performance line 8-bit microcontrollers offer from 32 to 128 Kbytes Flash
program memory. They are referred to as high-density devices in the STM8S microcontroller
family reference manual.
All devices of the STM8S20xxx performance line provide the following benefits: reduced
system cost, performance robustness, short development cycles, and product longevity.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k
write/erase cycles and a high system integration level with internal clock oscillators,
watchdog, and brown-out reset.
Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced
characteristics which include robust I/O, independent watchdogs (with a separate clock
source), and a clock security system.
Short development cycles are guaranteed due to application scalability across a common
family product architecture with compatible pinout, memory map and and modular
peripherals. Full documentation is offered with a wide choice of development tools.
Product longevity is ensured in the STM8S family thanks to their advanced core which is
made in a state-of-the art technology for applications with 2.95 V to 5.5 V operating supply.
STM8S207xx, STM8S208xx Description
Doc ID 14733 Rev 12 11/103
Table 2. STM8S20xxx performance line features
Block diagram STM8S207xx, STM8S208xx
12/103 Doc ID 14733 Rev 12
3 Block diagram
Figure 1. STM8S20xxx performance line block diagram Legend:
ADC: Analog-to-digital converter
beCAN: Controller area network
BOR: Brownout reset
I²C: Inter-integrated circuit multimaster interface
Independent WDG: Independent watchdog
POR/PDR: Power on reset / power down reset
SPI: Serial peripheral interface
SWIM: Single wire interface module
UART: Universal asynchronous receiver transmitter
Window WDG: Window watchdog
STM8S207xx, STM8S208xx Product overview
Doc ID 14733 Rev 12 13/103
4 Product overview
The following section intends to give an overview of the basic features of the STM8S20xxx
performance line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1 Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers Harvard architecture 3-stage pipeline 32-bit wide program memory bus - single cycle fetching for most instructions X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-Mbyte linear memory space 16-bit stack pointer - access to a 64 K-level stack 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing 20 addressing modes Indexed indirect addressing mode for look-up tables located anywhere in the address
space Stack pointer relative addressing mode for local variables and parameter passing
Instruction set 80 instructions with 2-byte average instruction size Standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division Bit manipulation Data transfer between stack and accumulator (push/pop) with direct stack access Data transfer using the X and Y registers or direct memory-to-memory transfers
Product overview STM8S207xx, STM8S208xx
14/103 Doc ID 14733 Rev 12
4.2 Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-
circuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in real-
time by means of shadow registers. R/W to RAM and peripheral registers in real-time R/W access to all resources by stalling the CPU Breakpoints on all program-memory instructions (software breakpoints) Two advanced breakpoints, 23 predefined configurations
4.3 Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on six vectors including TLI Trap and reset interrupts
4.4 Flash program and data EEPROM memory Up to 128 Kbytes of high density Flash program single voltage Flash memory Up to 2K bytes true data EEPROM Read while write: Writing in data memory possible while executing code in program
memory. User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes. o perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to Figure 2.
STM8S207xx, STM8S208xx Product overview
Doc ID 14733 Rev 12 15/103
The size of the UBC is programmable through the UBC option byte (Table 13.), in
increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas: Main program memory: Up to 128 Kbytes minus UBC User-specific boot code (UBC): Configurable up to 128 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2. Flash memory organisation
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
Product overview STM8S207xx, STM8S208xx
16/103 Doc ID 14733 Rev 12
4.5 Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler. Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching. Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory. Master clock sources: Four different clock sources can be used to drive the master
clock: 1-24 MHz high-speed external crystal (HSE) Up to 24 MHz high-speed user-external clock (HSE user-ext) 16 MHz high-speed internal RC oscillator (HSI) 128 kHz low-speed internal RC (LSI) Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts. Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated. Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 3. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
STM8S207xx, STM8S208xx Product overview
Doc ID 14733 Rev 12 17/103
4.6 Power management
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources. Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset. Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower. Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
4.7 Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations: Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Product overview STM8S207xx, STM8S208xx
18/103 Doc ID 14733 Rev 12
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8 Auto wakeup counter Used for auto wakeup from active halt mode Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
4.10 TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver 16-bit up, down and up/down autoreload counter with 16-bit prescaler Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output Synchronization module to control the timer with external signals Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11 TIM2, TIM3 - 16-bit general purpose timers 16-bit autoreload (AR) up-counter 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768 Timers with 3 or 2 individually configurable capture/compare channels PWM mode Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
STM8S207xx, STM8S208xx Product overview
Doc ID 14733 Rev 12 19/103
4.12 TIM4 - 8-bit basic timer 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source: CPU clock Interrupt source: 1 x overflow/update
4.13 Analog-to-digital converter (ADC2)
STM8S20xxx performance line products contain a 10-bit successive approximation A/D
converter (ADC2) with up to 16 multiplexed input channels and the following main features: Input voltage range: 0 to VDDA Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices Conversion time: 14 clock cycles Single and continuous modes External trigger input Trigger from TIM1 TRGO End of conversion (EOC) interrupt
4.14 Communication interfaces
The following communication interfaces are implemented: UART1: Full feature UART, SPI emulation, LIN2.1 master capability, Smartcard mode,
IrDA mode, single wire mode. UART3: Full feature UART, LIN2.1 master/slave capability SPI : Full and half-duplex, 10 Mbit/s I²C: Up to 400 Kbit/s beCAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s
Table 4. TIM timer features
Product overview STM8S207xx, STM8S208xx
20/103 Doc ID 14733 Rev 12
4.14.1 UART1
Main features One Mbit/s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode
Asynchronous communication (UART mode) Full duplex communication - NRZ standard format (mark/space) Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes: Address bit (MSB) Idle line (interrupt) Transmission error detection with interrupt generation Parity control
Synchronous communication Full duplex synchronous transfers SPI master operation 8-bit data communication Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
LIN master mode Emission: Generates 13-bit synch break frame Reception: Detects 11-bit break frame
4.14.2 UART3
Main features 1 Mbit/s full duplex SCI LIN master capable High precision baud rate generator
STM8S207xx, STM8S208xx Product overview
Doc ID 14733 Rev 12 21/103
Asynchronous communication (UART mode) Full duplex communication - NRZ standard format (mark/space) Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes: Address bit (MSB) Idle line (interrupt) Transmission error detection with interrupt generation Parity control
LIN master capability Emission: Generates 13-bit synch break frame Reception: Detects 11-bit break frame
LIN slave mode Autonomous header handling - one single interrupt per valid message header Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 % Synch delimiter checking 11-bit LIN synch break detection - break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support
4.14.3 SPI Maximum speed: 10 Mbit/s (fMASTER/2) both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation - selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave/master selection input pin
Product overview STM8S207xx, STM8S208xx
22/103 Doc ID 14733 Rev 12
4.14.4 I2C I2 C master features: Clock generation Start and stop generation I2 C slave features: Programmable I2 C address detection Stop bit detection Generation and detection of 7-bit/10-bit addressing and general call Supports different communication speeds: Standard speed (up to 100 kHz) Fast speed (up to 400 kHz)
4.14.5 beCAN
The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the
CAN protocol version 2.0A and B. It has been designed to manage a high number of
incoming messages efficiently with a minimum CPU load.
For safety-critical applications the beCAN controller provides all hardware functions to
support the CAN time triggered communication option (TTCAN).
The maximum transmission speed is 1 Mbit.
Transmission Three transmit mailboxes Configurable transmit priority by identifier or order request Time stamp on SOF transmission
Reception 8-, 11- and 29-bit ID One receive FIFO (3 messages deep) Software-efficient mailbox mapping at a unique address space FMI (filter match index) stored with message Configurable FIFO overrun Time stamp on SOF reception Six filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking
configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID Filtering modes: Mask mode permitting ID range filtering ID list mode Time triggered communication option Disable automatic retransmission mode 16-bit free running timer Configurable timer resolution Time stamp sent in last two data bytes
STM8S207xx, STM8S208xx Pinouts and pin description
Doc ID 14733 Rev 12 23/103 Pinouts and pin description
5.1 Package pinouts
Figure 3. LQFP 80-pin pinout (HS) high sink capability. (T) True open drain (P-buffer and protection diode to VDD not implemented). [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function). CAN_RX and CAN_TX is available on STM8S208xx devices only.
Pinouts and pin description STM8S207xx, STM8S208xx
24/103 Doc ID 14733 Rev 12
STM8S207xx, STM8S208xx Pinouts and pin description
Doc ID 14733 Rev 12 25/103
Pinouts and pin description STM8S207xx, STM8S208xx
26/103 Doc ID 14733 Rev 12
STM8S207xx, STM8S208xx Pinouts and pin description
Doc ID 14733 Rev 12 27/103
Pinouts and pin description STM8S207xx, STM8S208xx
28/103 Doc ID 14733 Rev 12
Table 5. Legend/abbreviations for pinout table
Table 6. Pin description
STM8S207xx, STM8S208xx Pinouts and pin description
Doc ID 14733 Rev 12 29/103
Table 6. Pin description (continued)
Pinouts and pin description STM8S207xx, STM8S208xx
30/103 Doc ID 14733 Rev 12
Table 6. Pin description (continued)
STM8S207xx, STM8S208xx Pinouts and pin description
Doc ID 14733 Rev 12 31/103
Table 6. Pin description (continued)
Pinouts and pin description STM8S207xx, STM8S208xx
32/103 Doc ID 14733 Rev 12
5.2 Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. Refer to Section 8: Option bytes on page 46. When the remapping
option is active, the default alternate function is no longer available. o use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016). The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as
part of the bootloader activation process and returned to the floating state before a return from the bootloader. The beCAN interface is available on STM8S208xx devices only In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
not implemented). The PD1 pin is in input pull-up during the reset phase and after the internal reset release. Available in 44-pin package only. On other packages, the AFR4 bit is reserved and must be kept at 0.
Table 6. Pin description (continued)
STM8S207xx, STM8S208xx Memory and register map
Doc ID 14733 Rev 12 33/103 Memory and register map
6.1 Memory map
Figure 8. Memory map
Memory and register map STM8S207xx, STM8S208xx
34/103 Doc ID 14733 Rev 12
Table 7 lists the boundary addresses for each memory size. The top of the stack is at the
RAM end address in each case.
6.2 Register map
Table 7. Flash, Data EEPROM and RAM boundary addresses
Table 8. I/O port hardware register map
STM8S207xx, STM8S208xx Memory and register map
Doc ID 14733 Rev 12 35/103
Table 8. I/O port hardware register map (continued)
Memory and register map STM8S207xx, STM8S208xx
36/103 Doc ID 14733 Rev 12
Table 9. General hardware register map
STM8S207xx, STM8S208xx Memory and register map
Doc ID 14733 Rev 12 37/103
Table 9. General hardware register map (continued)
Memory and register map STM8S207xx, STM8S208xx
38/103 Doc ID 14733 Rev 12
Table 9. General hardware register map (continued)
STM8S207xx, STM8S208xx Memory and register map
Doc ID 14733 Rev 12 39/103
Table 9. General hardware register map (continued)
Memory and register map STM8S207xx, STM8S208xx
40/103 Doc ID 14733 Rev 12
Table 9. General hardware register map (continued)
STM8S207xx, STM8S208xx Memory and register map
Doc ID 14733 Rev 12 41/103
Table 9. General hardware register map (continued)
Memory and register map STM8S207xx, STM8S208xx
42/103 Doc ID 14733 Rev 12
Depends on the previous reset source. Write only register. If the bootloader is enabled, it is initialized to 0x00.
Table 9. General hardware register map (continued)
STM8S207xx, STM8S208xx Memory and register map
Doc ID 14733 Rev 12 43/103
Table 10. CPU/SWIM/debug module/interrupt controller registers
Memory and register map STM8S207xx, STM8S208xx
44/103 Doc ID 14733 Rev 12 Accessible by debug module only Product dependent value, see Figure 8: Memory map.
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
STM8S207xx, STM8S208xx Interrupt vector mapping
Doc ID 14733 Rev 12 45/103 Interrupt vector mapping
Table 11. Interrupt mapping Except PA1
Option bytes STM8S207xx, STM8S208xx
46/103 Doc ID 14733 Rev 12
8 Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the
application in IAP mode, except the ROP option that can only be modified in ICP mode (via
SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 12. Option bytes
STM8S207xx, STM8S208xx Option bytes
Doc ID 14733 Rev 12 47/103
Table 13. Option byte description
Option bytes STM8S207xx, STM8S208xx
48/103 Doc ID 14733 Rev 12
Table 13. Option byte description (continued)
STM8S207xx, STM8S208xx Option bytes
Doc ID 14733 Rev 12 49/103
Table 13. Option byte description (continued)
Unique ID STM8S207xx, STM8S208xx
50/103 Doc ID 14733 Rev 12
9 Unique ID
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single bytes and may then be concatenated
using a custom algorithm.
The unique device identifier is ideally suited: For use as serial numbers For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software crytograhic primitives and protocols
before programming the internal memory. To activate secure boot processes
Table 14. Unique ID registers (96 bits)
STM8S207xx, STM8S208xx Electrical characteristics
Doc ID 14733 Rev 12 51/103
10 Electrical characteristics
10.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
10.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3 Σ).
10.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested. ypical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
10.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
10.1.4 Typical current consumption
For typical current consumption measurements, VDD, VDDIO and VDDA are connected
together in the configuration shown in Figure 9.
Figure 9. Supply current measurement conditions
Electrical characteristics STM8S207xx, STM8S208xx
52/103 Doc ID 14733 Rev 12
10.1.5 Pin loading conditions
10.1.6 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Figure 10. Pin loading conditions
10.1.7 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 11. Pin input voltage
