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STM7E1ASTN/a437avai7 E 1 CHANNELS SWITCH ARRAY
STM7E1ARSTN/a583avai7 E 1 CHANNELS SWITCH ARRAY


STM7E1AR ,7 E 1 CHANNELS SWITCH ARRAYSTM7E1A7 E 1 CHANNELS SWITCH ARRAY■ MAIN SWITCHES MAX. R LESS THAN 2ΩON■ PROVIDES 7 AUXILIARY SWITC ..
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STM7E1A-STM7E1AR
7 E 1 CHANNELS SWITCH ARRAY
1/10December 2002 MAIN SWITCHES MAX.RON LESS THAN2Ω PROVIDES7 AUXILIARY SWITCHES WITH
RON <75Ω 6VPP AMPLITUDEOF ANALOG INPUT
SIGNAL DIGITAL INPUTS ARE TTL LEVELS
COMPATIBLE
DESCRIPTION

The STM7E1 consistsin7 identical ISDNE1
channels, each channel correspondingto4 main
low-resistant switches(a andb) and2 auxiliary
switches(c andd). The switches positionsinall
the channels are identical and controlledbya
unique control resource drivenbythe digital inputs
Lm,Ls andSc. each channel, theTX and RX lines canbe
switched betweena Main portora Spare-portby
the main switches:if both"a" switchesare closed
and both"b" switchesare open,the Main portis
connectedtothe line, whileif both"a" switches
are open and both"b' switches are closed, the
spare portis connectedtothe line.
The2 auxiliary switches enableto closea local
loop betweentheTX andRX accessofa port:if
"c"is closed,the Spare portRX andTX accessis
connected between each otherto forma local
loop, whileif"d"is closed,the Main portRX and accessis connected between each otherto
forma local loop.
The Spare portis only usedfortest purposeonthe
system board while the Main portis the
communication channel. Consequently, a
switching from the Main portto the Spare port
occurs very rarely (<10 timesa day).
The power suppliesof the chip needtobede
coupled properly. This means thatat least one
external capacitor C1 mustbe connectedin
between GND and VPOS, one external capacitor between GND and VNEG, and one external
capacitorC3 between each pairof VNEG and
VPOS.
ORDERING CODES
STM7E1A
E1 CHANNELS SWITCH ARRAY
STM7E1A
2/10
PIN CONFIGURATION
PIN DESCRIPTION
STM7E1A
3/10
NOTE1:All VNEGpinstobe connected togetheron board.
NOTE2:All VPOSpinstobe connected togetheron board.
STM7E1A
4/10
TYPICAL OPERATING CIRCUIT
STM7E1A
5/10
DECODINGOF FUNCTIONAL MODE1 (MODE=L)

When closingthe main port local loop (Lm high),itis external system responsibilityto ensure thatthe main
porthas previously been disconnected fromtheline(Sc hastobe high). Thereisno internal mechanism ensure this.
When closingthe spare port local loop(Ls high),itis external system responsibilityto ensure thatthe
spare port has previously been disconnected fromthe line (Sc hastobe high). Thereisno internal
mechanismto ensure this.
DECODINGOF FUNCTIONAL MODE2 (MODE=H)
= Closed
O=Open= Closed
O=Open
TEST MODE DESCRIPTION (MODE=0, TEST=1)
orderto testthe main switches (4-point measurement), test modesare foreseen where the main
switches canbe controlled independently from each other. One can enterin test modeby controllingthe
Sc,Lm andLs pins accordingtothe following table.
The digital part and auxiliary switches canbe testedin functional mode.
Note1: Although thereisan internal pulldown inthe TEST pin,anexternal hardware connection fromTESTto GNDis requiredonthe boardworkin functional, mode.
STM7E1A
6/10
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratingsare those values beyond which damagetothe devicemay occur. Functional operation under these conditionis
not implied.
RECOMMENDED OPERATING CONDITIONS
DIGITAL PART SPECIFICATIONS
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