STM706PAM6F ,3V SupervisorBlock diagram (STM708T/S/R) . . . . . . 10Figure 9. Hardware hookup 10Figure 10. Reset o ..
STM706PM6E ,3V SupervisorSTM706T/S/R, STM706P, STM708T/S/R3V Supervisor
STM706PM6F ,3V SupervisorAbsolute Maximum Ratings . . . . . . . 17DC and AC PARAMETERS . 18Table 5. Operating and ..
STM706RAM6F ,3V SupervisorApplications■ Terminals■ Computers■ Base stations■ Controllers■ Medical equipment■ Intelligent inst ..
STM706RM6E ,3V SupervisorFEATURES SUMMARY■ PRECISION V MONITOR Figure 1. PackagesCC– STM706/708 ≤ 3.15VT: 3.00V ≤ VRSTS: 2.8 ..
STM706RM6F ,3V SupervisorBlock Diagram (STM708T/S/R) . . . . . 7Figure 10.Hardware Hookup . . . . . . . 8OPERATIO ..
SY58027UMG , ULTRA PRECISION DUAL 2:1 400mV LVPECL MUX WITH INTERNAL TERMINATION
SY58027UMG , ULTRA PRECISION DUAL 2:1 400mV LVPECL MUX WITH INTERNAL TERMINATION
SY58028UMG , ULTRA PRECISION DIFFERENTIAL CML 4:1 MUX WITH 1:2 FANOUT AND INTERNAL I/O TERMINATION
SY58029UMG , ULTRA PRECISION DIFFERENTIAL LVPECL 4:1 MUX with 1:2 FANOUT and INTERNAL TERMINATION
SY58029UMG , ULTRA PRECISION DIFFERENTIAL LVPECL 4:1 MUX with 1:2 FANOUT and INTERNAL TERMINATION
SY58029UMG-TR , ULTRA PRECISION DIFFERENTIAL LVPECL 4:1 MUX with 1:2 FANOUT and INTERNAL TERMINATION
STM706PAM6F-STM706RAM6F-STM706SAM6F-STM706TAM6F-STM708SAM6F-STM708TAM6F
3V Supervisor
August 2012 Doc ID 10518 Rev 12 1/32
STM706T/S/R, STM706P , STM708T/S/R3 V supervisor
Datasheet − production data
Features Precision VCC monitor T: 3.00 V ≤ VRST ≤ 3.15 V S: 2.88 V ≤ VRST ≤ 3.00 V R: STM706P: 2.59 V ≤ VRST ≤ 2.70 V RST and RST outputs 200 ms (typ.) trec Watchdog timer - 1.6 s (typ.) Manual reset input (MR) Power-fail comparator (PFI/PFO) Low supply current - 40 µA (typ.) Guaranteed RST (RST) assertion down to
VCC = 1.0 V Operating temperature: –40 °C to 85 °C
(industrial grade) RoHS compliance Lead-free components are compliant with
the RoHS directive
Applications Computers Controllers Intelligent instruments Contact local ST sales office for availability.
Critical µP power monitoring Terminals Base stations Medical equipment Set-top box
Table 1. Device summary Push-pull output. The STM706P device is identical to the STM706R device, except its reset output is active high.
Contents STM706T/S/R, STM706P, STM708T/S/R2/32 Doc ID 10518 Rev 12
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 WDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7 PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Watchdog input (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . 11
3.4 Watchdog output (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . 11
3.5 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Ensuring a valid reset output down to VCC = 0 V . . . . . . . . . . . . . . . . . . . 12
3.7 Interfacing to microprocessors with bi-directional reset pins . . . . . . . . . . 13
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM706T/S/R, STM706P, STM708T/S/R List of tables
Doc ID 10518 Rev 12 3/32
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. SO8 - 8-lead plastic small outline, 150 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size,
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of figures STM706T/S/R, STM706P, STM708T/S/R
4/32 Doc ID 10518 Rev 12
List of figures
Figure 1. Logic diagram (STM706T/S/R and STM706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. STM706T/S/R and STM706P SO8 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. STM706T/S/R and STM706P TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. STM708T/S/R SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. STM708T/S/R TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Block diagram (STM706T/S/R and STM706P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Block diagram (STM708T/S/R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Reset output valid to ground circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Interfacing to microprocessors with bi-directional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14. Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15. Power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. Watchdog timeout period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. Output voltage vs. load current (VCC = 5 V; TA = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Power-fail comparator response time (assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 28. Watchdog timing (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 29. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical . . . . . . . . . 27
Figure 30. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline. . . . . . . . . . . . . . 28
STM706T/S/R, STM706P, STM708T/S/R Description
Doc ID 10518 Rev 12 5/32
1 Description
The STM70x supervisors are self-contained devices which provide microprocessor
supervisory functions. A precision voltage reference and comparator monitors the VCC input
for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output
(RST) is forced low (or high in the case of RST).
These devices also offer a watchdog timer (except for STM708T/S/R) as well as a power-fail
comparator to provide the system with an early warning of impending power failure.
The STM706P device is identical to the STM706R device, except its reset output is active
high. These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin
TSSOP package.
Figure 1. Logic diagram (STM706T/S/R and STM706P) For STM706P only.
Figure 2. Logic diagram (STM708T/S/R)
Description STM706T/S/R, STM706P, STM708T/S/R
6/32 Doc ID 10518 Rev 12
Figure 3. STM706T/S/R and STM706P SO8 connections For STM706P reset output is active high.
Figure 4. STM706T/S/R and STM706P TSSOP8 connections For STM706P reset output is active high.
Table 2. Signal names For STM706P and STM708T/S/R only.
STM706T/S/R, STM706P, STM708T/S/R Description
Doc ID 10518 Rev 12 7/32
Figure 5. STM708T/S/R SO8 connections
Figure 6. STM708T/S/R TSSOP8 connections
Pin descriptions STM706T/S/R, STM706P, STM708T/S/R
8/32 Doc ID 10518 Rev 12
2 Pin descriptions
2.1 MR
A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low
and for trec after MR returns high. This active low input has an internal pull-up. It can be
driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if
unused.
2.2 WDI
If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset (or
WDO) is triggered. The internal watchdog timer clears while reset is asserted or when WDI
sees a rising or falling edge.
The watchdog function can be disabled by allowing the WDI pin to float.
2.3 WDO
WDO goes low when a transition does not occur on WDI within 1.6 s, and remains low until
a transition occurs on WDI (indicating the watchdog interrupt has been serviced) or MR
input is asserted (goes low). WDO also goes low when VCC falls below the reset threshold;
however, unlike the reset output, WDO goes high as soon as VCC exceeds the reset
threshold. Output type is push-pull.
Note: For those devices with a WDO output, a watchdog timeout will not trigger reset unless WDO
is connected to MR.
2.4 RST
Pulses low for trec when triggered, and stays low whenever VCC is below the reset
threshold or when MR is a logic low. It remains low for trec after either VCC rises above the
reset threshold, the watchdog triggers a reset, or MR goes from low to high.
2.5 RST
Pulses high for trec when triggered, and stays high whenever VCC is above the reset
threshold or when MR is a logic high. It remains high for trec after either VCC falls below the
reset threshold, the watchdog triggers a reset, or MR goes from high to low.
2.6 PFI
When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Connect to
ground if unused.
STM706T/S/R, STM706P, STM708T/S/R Pin descriptions
Doc ID 10518 Rev 12 9/32
2.7 PFO
When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Output type is
push-pull. PFO pin is not supposed to be forced low by a processor. MR input is gated off
during the period PFO is forced low. Leave open if unused.
Figure 7. Block diagram (STM706T/S/R and STM706P) For STM706P only.
Table 3. Pin description
Pin descriptions STM706T/S/R, STM706P, STM708T/S/R
10/32 Doc ID 10518 Rev 12
Figure 8. Block diagram (STM708T/S/R)
Figure 9. Hardware hookup For STM706T/S/R and STM706P devices. For STM706P and STM708T/S/R devices.
STM706T/S/R, STM706P, STM708T/S/R Operation
Doc ID 10518 Rev 12 11/32
3 Operation
3.1 Reset output
The STM70x supervisor asserts a reset signal to the MCU whenever VCC goes below the
reset threshold (VRST ), a watchdog timeout occurs (if WDO is connected to MR), or when the
push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic high for
STM706P and STM708T/S/R) for VCC < VRST down to VCC =1 V for TA = 0 °C to 85 °C.
During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for
the reset timeout period, trec . After this interval RST returns high.
If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset timeout period (trec ). Any time VCC goes below the reset threshold
the internal timer clears. The reset timer starts when VCC returns above the reset threshold.
3.2 Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see
Figure 27) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing
it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with
open-drain / collector outputs. Connect a normally open momentary switch from MR to GND
to create a manual reset function; external debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor
from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when
not used.
3.3 Watchdog input (STM706T/S/R and STM706P)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the watchdog input (WDI) within tWD (1.6 s), the watchdog output pin (WDO) is
asserted. The internal 1.6s timer is cleared by either: a reset pulse, or
2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
See Figure 28 for STM706T/S/R and STM706P.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
3.4 Watchdog output (STM706T/S/R and STM706P)
When VCC drops below the reset threshold, WDO will go low even if the watchdog timer has
not yet timed out. However, unlike the reset output, WDO goes high as soon as VCC
exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it
to the MR input.
Operation STM706T/S/R, STM706P, STM708T/S/R
12/32 Doc ID 10518 Rev 12
3.5 Power-fail input/output
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the power-fail
output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 9) to either the unregulated DC input (if it is available) or the regulated output of
the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below
VPFI several milliseconds before the regulated VCC input to the STM70x or the micro-
processor drops below the minimum operating voltage.
If the comparator is unused, PFI should be connected to VSS and PFO left unconnected.
PFO may be connected to MR on the STM70x so that a low voltage on PFI will generate
a reset output.
3.6 Ensuring a valid reset output down to VCC = 0 V
When VCC falls below 1 V, the state of the RST output can no longer be guaranteed, and
becomes essentially an open circuit. If a high value pulldown resistor is added to the RST
pin, the output will be held low during this condition. A resistor value of approximately
100 kΩ will be large enough to not load the output under operating conditions, but still
sufficient to pull RST to ground during this low voltage condition (see Figure 10).
Figure 10. Reset output valid to ground circuit
STM706T/S/R, STM706P, STM708T/S/R Operation
Doc ID 10518 Rev 12 13/32
3.7 Interfacing to microprocessors with bi-directional reset pins
Microprocessors with bi-directional reset pins can contend with the STM70x reset output.
For example, if the reset output is driven high and the micro wants to pull it low, signal
contention will result. To prevent this from occurring, connect a 4.7kΩ resistor between the
reset output and the micro's reset I/O as in Figure 11.
Figure 11. Interfacing to microprocessors with bi-directional reset I/O
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
14/32 Doc ID 10518 Rev 12 Typical operating characteristics ypical values are at TA = 25 °C.
Figure 12. Supply current vs. temperature (no load)
STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics
Doc ID 10518 Rev 12 15/32
Figure 13. VPFI threshold vs. temperature
Figure 14. Reset comparator propagation delay vs. temperature
Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R
16/32 Doc ID 10518 Rev 12
Figure 15. Power-up trec vs. temperature
Figure 16. Normalized reset threshold vs. temperature
