STM692AM6E ,5V Supervisor with Battery SwitchoverAbsolute Maximum Ratings . . . . . . . 23DC and AC PARAMETERS . 23Table 6. Operating and ..
STM692AM6F ,5V Supervisor with Battery SwitchoverSTM690A, STM692A, STM703STM704, STM802, STM805, STM817/8/95V Supervisor with Battery Switchover
STM6930 , Dual N-Channel Enhancement Mode Field Effect Transistor
STM6930 , Dual N-Channel Enhancement Mode Field Effect Transistor
STM6960 , Dual N-Channel Enhancement Mode Field Effect Transistor
STM6962 , Dual N-Channel E nhancement Mode F ield E ffect Transistor
SY58019UMG , ULTRA-PRECISION DIFFERENTIAL 400mV LVPECL 2:1 MUX with INTERNAL TERMINATION
SY58020UMGTR , 6GHz, 1:4 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION
SY58021UMG , 4GHz, 1:4 LVPECL Fanout Buffer/Translator with Internal Termination Precision Edge®
SY58021UMG , 4GHz, 1:4 LVPECL Fanout Buffer/Translator with Internal Termination Precision Edge®
SY58021UMG-TR , 4GHz, 1:4 LVPECL Fanout Buffer/Translator with Internal Termination Precision Edge®
SY58021UMG-TR , 4GHz, 1:4 LVPECL Fanout Buffer/Translator with Internal Termination Precision Edge®
STM692AM6E-STM692AM6F-STM703M6E-STM703M6F-STM802LM6E-STM802LM6F-STM802MM6E-STM802MM6F-STM805LM6E-STM805LM6F-STM817LM6E-STM817LM6F-STM817MM6E-STM817MM6F-STM819LM6E-STM819LM6F-STM819MM6E-STM819MM6F
5V Supervisor with Battery Switchover
1/33September 2004
STM690A, STM692A, STM703
STM704, STM802, STM805, STM817/8/95V Supervisor with Battery Switchover
* Contact local ST sales office for availability.
FEATURES SUMMARY 5V OPERATING VOLTAGE NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM CHIP-ENABLE GATING (STM818 only) FOR
EXTERNAL LPSRAM (7ns max PROP
DELAY) RST AND RST OUTPUTS 200ms (TYP) trec WATCHDOG TIMER - 1.6sec (TYP) AUTOMATIC BATTERY SWITCHOVER LOW BATTERY SUPPLY CURRENT - 0.4µA
(TYP) POWER-FAIL COMPARATOR (PFI/PFO) LOW SUPPLY CURRENT - 40µA (TYP) GUARANTEED RST (RST) ASSERTION
DOWN TO VCC = 1.0V OPERATING TEMPERATURE:
–40°C to 85°C (Industrial Grade)
Table 1. Device OptionsNote:1. All RST and RST outputs are push-pull.
STM690A/692A/703/704/802/805/817/818/819
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 2. Logic Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. Logic Diagram (STM703/704/819). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 4. Logic Diagram (STM818). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 5. STM690A/692A/802/805/817 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 6. STM703/704/819 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 7. STM818 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 8. Block Diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 9. Block Diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 10.Block Diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Push-button Reset Input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Watchdog Input (NOT available on STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip-Enable Gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable Input (STM818 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip Enable Output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 12.Chip-Enable Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 13.Chip Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power-fail Input/Output (NOT available on STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Figure 14.Power-fail Comparator Waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 15.Power-fail Comparator Waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . .13
Using a SuperCap™ as a Backup Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Negative-Going VCC Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Battery Freshness Seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Figure 16.Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 17.Freshness Seal Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 18.VBAT-to-VOUT On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 19.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/33
STM690A/692A/703/704/802/805/817/818/819Figure 20.VPFI Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 21.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 22.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 23.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 24.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 25.E to ECON On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 26.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 27.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 28.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 29.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 30.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 31.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 32.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 33.VCC to Reset Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 34.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . .22
Figure 35.E to ECON Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 36.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 37.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 38.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 39.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 7. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Figure 40.SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . .28
Table 8. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . .28
Figure 41.TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . .29
Table 9. TSSOP8 – 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . .29
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 11. Marking Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
STM690A/692A/703/704/802/805/817/818/819
SUMMARY DESCRIPTIONThe STM690A/692A/703/704/802/805/817/818/
819 Supervisors are self-contained devices which
provide microprocessor supervisory functions with
the ability to non-volatize and write-protect exter-
nal LPSRAM. A precision voltage reference and
comparator monitors the VCC input for an out-of-
tolerance condition. When an invalid VCC condi-
tion occurs, the reset output (RST) is forced low
(or high in the case of RST). These devices also
offer a watchdog timer (except for STM703/704/
819) as well as a power-fail comparator (except for
STM818) to provide the system with an early
warning of impending power failure.
These devices are available in a standard 8-pin
SOIC package or a space-saving 8-pin TSSOP
package.
5/33
STM690A/692A/703/704/802/805/817/818/819
STM690A/692A/703/704/802/805/817/818/819
Pin Descriptions
MR. A logic low on /MR asserts the reset output.
Reset remains asserted as long as MR is low and
for trec after MR returns high. This active-low input
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
WDI. If WDI remains high or low for 1.6sec, the in-
ternal watchdog timer runs out and reset is trig-
gered. The internal watchdog timer clears while
reset is asserted or when WDI sees a rising or fall-
ing edge.
The watchdog function can be disabled by allow-
ing the WDI pin to float.
RST. Pulses low for trec when triggered, and stays
low whenever VCC is below the reset threshold or
when MR is a logic low. It remains low for trec after
either VCC rises above the reset threshold, the
watchdog triggers a reset, or MR goes from low to
high.
RST. Pulses high for trec when triggered, and
stays high whenever VCC is above the reset
threshold or when MR is a logic high. It remains
high for trec after either VCC falls below the reset
threshold, the watchdog triggers a reset, or MR
goes from high to low.
VOUT. When VCC is above the switchover voltage
(VSO), VOUT is connected to VCC through a P-
channel MOSFET switch. When VCC falls below
VSO, VBAT connects to VOUT. Connect to VCC if no
battery is used.
VBAT. When VCC falls below VSO, VOUT switches
from VCC to VBAT. When VCC rises above VSO +
hysteresis, VOUT reconnects to VCC. VBAT may ex-
ceed VCC. Connect to VCC if no battery is used.
The input to the chip-enable gating circuit. Con-
nect to ground if unused.
ECON. ECON goes low only when E is low and re-
set is not asserted. If ECON is low when reset is as-
serted, ECON will remain low for 15µs or until E
goes high, whichever occurs first. In the disabled
mode, ECON is pulled up to VOUT.
PFI. When PFI is less than VPFI or when VCC falls
below 2.4V (or VSO), PFO goes low; otherwise,
PFO remains high. Connect to ground if unused.
PFO. When PFI is less than VPFI, or VCC falls be-
low 2.4V (or VSO), PFO goes low; otherwise, PFO
remains high. Leave open if unused.
Table 3. Pin Description
7/33
STM690A/692A/703/704/802/805/817/818/819
STM690A/692A/703/704/802/805/817/818/819
Figure 10. Block Diagram (STM818)
Figure 11. Hardware HookupNote:1. For STM690A/692A/802/805/817/818. For STM818 only. Not available on STM818. For STM703/704/819.
9/33
STM690A/692A/703/704/802/805/817/818/819
OPERATION
Reset OutputThe STM690A/692A/703/704/802/805/817/818/
819 Supervisor asserts a reset signal to the MCU
whenever VCC goes below the reset threshold
(VRST), a watchdog time-out occurs, or when the
Push-button Reset Input (MR) is taken low. RST is
guaranteed to be a logic low (logic high for
STM805) for 0V < VCC < VRST if VBAT is greater
than 1V. Without a back-up battery, RST is guar-
anteed valid down to VCC =1V.
During power-up, once VCC exceeds the reset
threshold an internal timer keeps RST low for the
reset time-out period, trec. After this interval RST
returns high.
If VCC drops below the reset threshold, RST goes
low. Each time RST is asserted, it stays low for at
least the reset time-out period (trec). Any time VCC
goes below the reset threshold the internal timer
clears. The reset timer starts when VCC returns
above the reset threshold.
Push-button Reset Input (STM703/704/819)A logic low on MR asserts reset. Reset remains
asserted while MR is low, and for trec (see Figure
38., page 24) after it returns high. The MR input
has an internal 40kΩ pull-up resistor, allowing it to
be left open if not used. This input can be driven
with TTL/CMOS-logic levels or with open-drain/
collector outputs. Connect a normally open mo-
mentary switch from MR to GND to create a man-
ual reset function; external debounce circuitry is
not required. If MR is driven from long cables or
the device is used in a noisy environment, connect
a 0.1µF capacitor from MR to GND to provide ad-
ditional noise immunity. MR may float, or be tied to
VCC when not used.
Watchdog Input (NOT available on STM703/
704/819)The watchdog timer can be used to detect an out-
of-control MCU. If the MCU does not toggle the
Watchdog Input (WDI) within tWD (1.6sec typ), the
reset is asserted. The internal watchdog timer is
cleared by either: a reset pulse, or by toggling WDI (high-to-low or low-to-high),
which can detect pulses as short as 50ns. If
WDI is tied high or low, a reset pulse is
triggered every 1.8sec (tWD + trec).
The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is re-
leased, the timer starts counting (see Figure
39., page 24).
Note: The watchdog function may be disabled byfloating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maxi-
mum allowable leakage current is 10uA and the
maximum allowable load capacitance is 200pF.
Note: Input frequency greater than 20ns (50MHz)will be filtered.
STM690A/692A/703/704/802/805/817/818/819
Back-up Battery SwitchoverIn the event of a power failure, it may be necessary
to preserve the contents of external SRAM
through VOUT. With a backup battery installed with
voltage VBAT, the devices automatically switch the
SRAM to the back-up supply when VCC falls.
Note: If back-up battery is not used, connect bothVBAT and VOUT to VCC.
This family of Supervisors does not always con-
nect VBAT to VOUT when VBAT is greater than VCC.
VBAT connects to VOUT (through a 100Ω switch)
when VCC is below VRST and VBAT. This is done to
allow the back-up battery (e.g., a 3.6V lithium cell)
to have a higher voltage than VCC.
Assuming VBAT > 2.0V, switchover at VSO ensures
that battery back-up mode is entered before VOUT
gets too close to the 2.0V minimum required to re-
liably retain data in most external SRAMs. When
VCC recovers, hysteresis is used to avoid oscilla-
tion around the VSO point. VOUT is connected to
VCC through a 3Ω PMOS power switch.
Note: The back-up battery may be removed whileVCC is valid, assuming VBAT is adequately decou-
pled (0.1µF typ), without danger of triggering a re-
set.
Table 4. I/O Status in Battery Back-up
Chip-Enable Gating (STM818 only)Internal gating of the chip enable (E) signal pre-
vents erroneous data from corrupting the external
CMOS RAM in the event of an undervoltage con-
dition. The STM818 uses a series transmission
gate from E to ECON (see Figure 12., page 11).
During normal operation (reset not asserted), the
E transmission gate is enabled and passes all E
transitions. When reset is asserted, this path be-
comes disabled, preventing erroneous data from
corrupting the CMOS RAM. The short E propaga-
tion delay from E to ECON enables the STM818 to
be used with most µPs. If E is low when reset as-
serts, ECON remains low for typically 15µs to per-
mit the current WRITE cycle to complete. Connect
E to VSS if unused.
Chip Enable Input (STM818 only)The chip-enable transmission gate is disabled and
E is high impedance (disabled mode) while reset
is asserted. During a power-down sequence when
VCC passes the reset threshold, the chip-enable
transmission gate disables and E immediately be-
comes high impedance if the voltage at E is high.
If E is low when reset asserts, the chip-enable
transmission gate will disable 15µs after reset as-
serts (see Figure 13., page 11). This permits the
current WRITE cycle to complete during power-
down.
Any time a reset is generated, the chip-enable
transmission gate remains disabled and E remains
high impedance (regardless of E activity) for the
reset time-out period. When the chip enable trans-
mission gate is enabled, the impedance of E ap-
pears as a 40Ω resistor in series with the load at
ECON. The propagation delay through the chip-en-
able transmission gate depends on VCC, the
source impedance of the drive connected to E,
and the loading on ECON. The chip enable propa-
gation delay is production tested from the 50%
point on E to the 50% point on ECON using a 50Ω
driver and a 50pF load capacitance (see Figure
37., page 24). For minimum propagation delay,
minimize the capacitive load at ECON and use a
low-output impedance driver.
Chip Enable Output (STM818 only)When the chip-enable transmission gate is en-
abled, the impedance of ECON is equivalent to a
40Ω resistor in series with the source driving E. In
the disabled mode, the transmission gate is off
and an active pull-up connects ECON to VOUT (see
Figure 12., page 11). This pull-up turns off when
the transmission gate is enabled.
11/33
STM690A/692A/703/704/802/805/817/818/819
STM690A/692A/703/704/802/805/817/818/819
Power-fail Input/Output (NOT available on STM818)The Power-fail Input (PFI) is compared to an inter-
nal reference voltage (independent from the VRST
comparator). If PFI is less than the power-fail
threshold (VPFI), the Power-Fail Output (PFO) will
go low. This function is intended for use as an un-
dervoltage detector to signal a failing power sup-
ply. Typically PFI is connected through an external
voltage divider (see Figure 11., page 8) to either
the unregulated DC input (if it is available) or the
regulated output of the VCC regulator. The voltage
divider can be set up such that the voltage at PFI
falls below VPFI several milliseconds before the
regulated VCC input to the STM690A/692A/703/
704/802/805/817/818/819 Supervisor or the mi-
croprocessor drops below the minimum operating
voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low (see Fig-
ure 14 and Figure 15., page 13). This occurs after
VCC drops below 2.4V (or VSO). When power re-
turns, PFO is forced high (STM817/819 only), irre-
spective of VPFI for the WRITE protect time (trec).
At the end of this time, the power-fail comparator
is enabled and PFO follows PFI. If the comparator
is unused, PFI should be connected to VSS and
PFO left unconnected. PFO may be connected to
MR on the STM703/704/818 so that a low voltage
on PFI will generate a reset output.
Applications InformationThese Supervisor circuits are not short-circuit pro-
tected. Shorting VOUT to ground - excluding pow-
er-up transients such as charging a decoupling
capacitor - destroys the device. Decouple both
VCC and VBAT pins to ground by placing 0.1µF ca-
pacitors as close to the device as possible.
Figure 14. Power-fail Comparator Waveform (STM817/818/819)
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STM690A/692A/703/704/802/805/817/818/819
STM690A/692A/703/704/802/805/817/818/819
Using a SuperCap™ as a Backup Power SourceSuperCaps™ are capacitors with extremely high
capacitance values (e.g., order of 0.47F) for their
size. Figure 16 shows how to use a SuperCap as
a back-up power source. The SuperCap may be
connected through a diode to the 5V input. Since
VBAT can exceed VCC while VCC is above the reset
threshold, there are no special precautions when
using these supervisors with a SuperCap.
Negative-Going VCC TransientsThe STM690A/692A/703/704/802/805/817/818/
819 Supervisor are relatively immune to negative-
going VCC transients (glitches). Figure
34., page 22 shows typical transient duration ver-
sus reset comparator overdrive (for which the
STM690A/692A/703/704/802/805/817/818/819
will NOT generate a reset pulse). The graph was
generated using a negative pulse applied to VCC,
starting at VRST + 0.3V and ending below the reset
threshold by the magnitude indicated (comparator
overdrive). The graph indicates the maximum
pulse width a negative VCC transient can have
without causing a reset pulse. As the magnitude of
the transient increases (further below the thresh-
old), the maximum allowable pulse width decreas-
es. Any combination of duration and overdrive
which lies under the curve will NOT generate a re-
set signal. Typically, a VCC transient that goes
100mV below the reset threshold and lasts 40µs or
less will not cause a reset pulse. A 0.1µF bypass
capacitor mounted as close as possible to the VCC
pin provides additional transient immunity.
Battery Freshness Seal (STM817/818/819)The battery freshness seal disconnects the back-
up battery from internal circuitry and VOUT until it is
needed. This allows an OEM to ensure that the
back-up battery connected to VBAT will be fresh
when the final product is put to use. To enable the
freshness seal: Connect a battery to VBAT; Ground PFO; Bring VCC above the reset threshold and hold
it there until reset is deasserted following the
reset timeout period; and
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STM690A/692A/703/704/802/805/817/818/819
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at TA = 25°C
Figure 18. VBAT-to-VOUT On-Resistance vs. Temperature
Figure 19. Supply Current vs. Temperature (no load)
STM690A/692A/703/704/802/805/817/818/819
Figure 20. VPFI Threshold vs. Temperature
Figure 21. Reset Comparator Propagation Delay vs. Temperature
Figure 22. Power-up trec vs. Temperature
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STM690A/692A/703/704/802/805/817/818/819
Figure 23. Normalized Reset Threshold vs. Temperature
Figure 24. Watchdog Time-out Period vs. Temperature
Figure 25. E to ECON On-Resistance vs. Temperature
