STM6719TZWB6F ,Dual/triple ultra-low voltage supervisors with push-button reset (with delay option)Logic diagram (STM6777/78) 6Figure 3.
STM6720SFWB6F ,Dual/triple ultra-low voltage supervisors with push-button reset (with delay option)Block diagram . . . . 9Figure 10. Hardware hookup . 9Figure 11. STM67xx interface to ..
STM6720SYWB6F ,Dual/triple ultra-low voltage supervisors with push-button reset (with delay option)STM6717/6718/6719/6720STM6777/6778/6779/6780Dual/triple ultra-low voltage supervisorswith push-butt ..
STM6720TWWB6F ,Dual/triple ultra-low voltage supervisors with push-button reset (with delay option)Logic diagram (STM6719/20) 6Figure 4.
STM6777SVWB6F ,Dual/triple ultra-low voltage supervisors with push-button reset (with delay option)Logic diagram (STM6779/80) 6Figure 5. STM6717/18 SOT23-5 connections . . . 7Figure 6. ST ..
STM6779YWB6F ,Dual/triple ultra-low voltage supervisors with push-button reset (with delay option)Logic diagram (STM6717/18) 6Figure 2.
SY55857LKG , 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR
SY55857LKG , 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR
SY55857LKI , 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR
SY55857LKI , 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR
SY55858UHG , 2.5V/3.3V 3.0GHZ DUAL 2 x 2 CML CROSSPOINT SWITCH W/INTERNAL TERMINATION
SY55858UHG , 2.5V/3.3V 3.0GHZ DUAL 2 x 2 CML CROSSPOINT SWITCH W/INTERNAL TERMINATION
STM6719SFWB6F-STM6719SHWB6F-STM6719TGWB6F-STM6719TZWB6F-STM6720SFWB6F-STM6720SYWB6F-STM6720TWWB6F-STM6777SVWB6F-STM6779YWB6F
Dual/Triple Ultra-Low Voltage Supervisors with Push-Button Reset
August 2011 Doc ID 11469 Rev 8 1/30
STM6717/6718/6719/6720
STM6777/6778/6779/6780Dual/triple ultra-low voltage supervisors
with push-button reset (with delay option)
Features Primary supply (VCC1) monitor.
Fixed (factory-programmed) reset thresholds:
4.63 V to 1.58 V Secondary supply (VCC2) monitor
(STM6717/18/19/20/77/78) Fixed (factory-programmed) reset thresholds:
3.08 V to 0.79 V Tertiary supply monitor (using externally
adjustable RSTIN): 0.626 V internal reference RST outputs (push-pull or open drain); state
guaranteed if VCC1 or VCC2 ≥ 0.8 V Reset delay time (trec) on power-up: 13.2 ms,
210 ms, 900 ms (typ) Manual reset input (MR) Optional delayed manual reset input (MRC)
with external capacitor (STM6777/78/79/80) Low supply current - 11 µA (typ),
VCC1 = VCC2 = 3.6 V Operating temperature: –40 °C to 85 °C
(industrial grade)
Table 1. Device summary
Contents STM6717/6718/6719/6720/STM6777/6778/6779/67802/30 Doc ID 11469 Rev 8
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80 . . . . . . . . 7
1.1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79 . . . . . . . 7
1.1.3 Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.4 Manual reset delay input (MRC) - STM6777/78/79/80) . . . . . . . . . . . . . . 8
1.1.5 Primary supply voltage monitoring input (VCC1) . . . . . . . . . . . . . . . . . . . 8
1.1.6 Secondary supply voltage monitoring input (VCC2) . . . . . . . . . . . . . . . . . 8
1.1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80) . . . . . . 8
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STM6717/6718/6719/6720/STM6777/6778/6779/6780 List of tables
Doc ID 11469 Rev 8 3/30
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. tMLMH minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. SOT23-5 – 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 23
Table 9. SOT23-6 – 6-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 24
Table 10. Carrier tape dimensions for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
List of figures STM6717/6718/6719/6720/STM6777/6778/6779/6780
4/30 Doc ID 11469 Rev 8
List of figures
Figure 1. Logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic diagram (STM6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Logic diagram (STM6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Logic diagram (STM6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. STM6717/18 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. STM6777/78 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. STM6719/20 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. STM6779/80 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. STM67xx interface to processor with bi-directional reset pins . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12. Ensuring RST valid to VCC = 0 (active-low, push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 10
Figure 13. Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V) . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14. Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.75 V) . . . . . . . . . . . . . . . . . . . . . 11
Figure 15. Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V) . . . . . . . . . . . . . . . . . . . . . . 12
Figure 16. Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V) . . . . . . . . . . . . . . . . . . . . . . 12
Figure 17. Normalized VCC reset time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18. Maximum VCC transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . 13
Figure 19. Normalized VRST1 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20. Normalized VRST2 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 21. Reset input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. VCC1-to-reset delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Reset input-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 24. MR-to-reset output delay vs. temperature (VCC1 = 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. AC testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. MR timing waveform (STM6717/18/19/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27. MR timing waveform (STM6777/78/79/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28. SOT23-5 – 5-lead small outline transistor package mechanical drawing. . . . . . . . . . . . . . 23
Figure 29. SOT23-6 – 6-lead small outline transistor package mechanical drawing. . . . . . . . . . . . . . 24
Figure 30. Carrier tape for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description
Doc ID 11469 Rev 8 5/30
1 Description
The STM6717/18/19/20 and STM6777/78/79/80 supervisors are a family of low-voltage/low-
supply current processor (micro or DSP) supervisors, designed to monitor two (or three)
system power supply voltages. They are targeted at applications such as set-top boxes
(STBs), portable, battery-powered systems, networking, and communication systems.
All device options have a push-button-type manual reset input (MR). The
STM6777/78/79/80 also includes an option which enables the user to delay the start of the
manual reset process from 6 µs (MRC pin left open) or more with external capacitor. The
delay is implemented by connecting the appropriately sized capacitor between the MRC pin
and VSS (typical 4 s delay with a 3.3 µF capacitor, see Table 7 on page 21). wo of the three supplies monitored (VCC1 and VCC2) have fixed (customer-selectable,
factory-trimmed) thresholds (VRST1 and VRST2). The third voltage is monitored using an
externally adjustable RSTIN threshold (0.626 V internal reference).
If any of the three monitored voltages drop below its factory-trimmed or adjustable
thresholds, or if MR is asserted to logic low, a RST is asserted (driven low). Once asserted,
RST is maintained at low for a minimum delay period (trec) after ALL supplies rise above
their respective thresholds and MR returns to high. These devices are guaranteed to be in
the correct reset output logic state when VCC1 and/or VCC2 is greater than 0.8 V.
These devices are available in standard 5-pin or 6-pin SOT23 packages (see Table 1 on
page1).
Description STM6717/6718/6719/6720/STM6777/6778/6779/6780
6/30 Doc ID 11469 Rev 8
Table 2. Signal names
Figure 1. Logic diagram (STM6717/18) Figure 2. Logic diagram (STM6777/78)
Figure 3. Logic diagram (STM6719/20) Figure 4. Logic diagram (STM6779/80)
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description
Doc ID 11469 Rev 8 7/30
1.1 Pin descriptions
1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80
The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its
factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low
for trec after ALL supply voltages being monitored rise above their reset thresholds and MR
goes from low to high. (Push-pull outputs are referenced to VCC1.)
1.1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79
The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its
factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low
for trec after ALL supply voltages being monitored rise above their reset thresholds and MR
goes from low to high. Connect an external pull-up resistor to VCC1 . A 10 kΩ pull-up resistor
should be sufficient for most applications.
1.1.3 Push-button reset input (MR)
When MR goes low the RST output is driven low. RST remains low as long as MR is low and
for trec after MR returns to high. This active-low input has an internal 50 kΩ pull-up resistor to
Figure 5. STM6717/18 SOT23-5 connections Figure 6. STM6777/78 SOT23-6 connections
Figure 7. STM6719/20 SOT23-6 connections Figure 8. STM6779/80 SOT23-6 connections
Description STM6717/6718/6719/6720/STM6777/6778/6779/6780
8/30 Doc ID 11469 Rev 8
VCC1. It can be driven from a TTL or CMOS logic line, or with open drain/collector outputs,
or connected to VSS through a switch. If unused, leave this pin open or connect it to VCC1.
Connect a normally open momentary switch from MR to VSS; external debounce circuitry is
not required. (If MR is driven from long cables or if the device is used in noisy environments,
connecting a 0.1µF capacitor from MR to VSS provides additional noise immunity.
1.1.4 Manual reset delay input (MRC) - STM6777/78/79/80)
This pin is either left open or connected to VSS via a capacitor. By selecting the appropriate
capacitor, the manual reset process, initiated by pressing the push-button manual reset
input, can be delayed by any value from 6 µs or more (see Table 7 on page 21).
1.1.5 Primary supply voltage monitoring input (V CC1)
It also is the input for the primary reset threshold monitor. Available fixed (customer-
selectable, factory-programmed) reset thresholds include 4.63 V to 1.58 V.
1.1.6 Secondary supply voltage monitoring input (V CC2)
This function is available on the STM6717/18/19/20/77/78. Fixed (customer-selectable,
factory-programmed) reset thresholds include 3.08 V to 0.79 V.
1.1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80)
This is a high impedance input. RST is driven low when the voltage at the RSTIN pin falls
below 0.626 V (internal reference voltage at this comparator). The monitored voltage reset
threshold is set with an external resistor-divider network.
Table 3. Pin functions
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description
Doc ID 11469 Rev 8 9/30
Figure 9. Block diagram VCC2 input is available on STM6717/18/19/20/77/78. RSTIN available only on STM6719/20/79/80. MRC available only on STM6777/78/79/80.
Figure 10. Hardware hookup VCC2 is available only on STM6717/18/19/20/77/78. RSTIN available only on STM6719/20/79/80. MRC available only on STM6777/78/79/80.
Operation STM6717/6718/6719/6720/STM6777/6778/6779/6780
10/30 Doc ID 11469 Rev 8
2 Operation
2.1 Applications information Interfacing to processors with bi-directional reset pins
Most processors with bi-directional reset pins can interface directly to the open drain
RST outputs (STM6717/19/77/79). Systems simultaneously requiring a push-pull RST
output and a bi-directional reset interface can be in logic contention. To prevent this
contention, connect a 4.7 kΩ resistor between RST and the processor’s reset I/O as
shown in Figure11.
2. Ensuring a valid RST output down to VCC =0 V
The STM67xx supervisors are guaranteed to be in the correct RST output logic state
when VCC1 and/or VCC2 is greater than 0.8 V. In applications which require valid reset
levels down to VCC = 0, a pull-down resistor to active-low outputs (push-pull only, see
Figure 12) will ensure that the reset line is valid while the reset output can no longer
sink or source current. This scheme does NOT work with the open drain outputs of the
STM6717/19/77/79.
The resistor value used is not critical, but it must be large enough not to load the reset
output when VCC is above the reset threshold. For most applications, 100 kΩ is
adequate.
Figure 11. STM67xx interface to processor with bi-directional reset pins
Figure 12. Ensuring RST valid to VCC = 0 (active-low, push-pull outputs)
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics
Doc ID 11469 Rev 8 11/30 Typical operating characteristics
Note: T ypical values are at TA = 25 °C unless otherwise noted.
Figure 13. Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V)
Figure 14. Supply current vs. temperature (V = 3.6 V; V = 2.75 V)
Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780
12/30 Doc ID 11469 Rev 8
Figure 15. Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V)
Figure 16. Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V)
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics
Doc ID 11469 Rev 8 13/30
Figure 17. Normalized VCC reset time-out period vs. temperature
Figure 18. Maximum VCC transient duration vs. reset threshold overdrive
Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780
14/30 Doc ID 11469 Rev 8
Figure 19. Normalized VRST1 threshold vs. temperature
Figure 20. Normalized VRST2 threshold vs. temperature
STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics
Doc ID 11469 Rev 8 15/30
Figure 21. Reset input threshold vs. temperature
Figure 22.VCC1 -to-reset delay vs. temperature
